Embedded flash memory high voltage device and preparation method thereof

Abstract

The present invention discloses an embedded flash memory high voltage device and a preparation method thereof, wherein the embedded flash memory high voltage device is an HVNMOS device, and its gate is a P-type gate. Thus, the threshold voltage of the obtained embedded flash memory HVNMOS device is about -0.9V; while the threshold voltage of a conventional embedded flash memory HVNMOS device with an N-type gate is about -1.5V; it can be seen that compared with the conventional embedded flash memory HVNMOS device, the threshold voltage of the embedded flash memory HVNMOS of the present application is reduced, the read current is increased, and the read window is increased, thereby providing convenience for the reduction of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an embedded flash memory high voltage device and a preparation method thereof. Background Art

[0002] Embedded Flash (eFlash) is a non-volatile storage technology integrated into integrated circuits that allows data to be retained in the event of a power outage. This technology is widely used in microcontrollers, system-on-chips (SoCs), and other applications that require storage of program code or data.

[0003] High voltage devices play an important role in embedded flash memory technology because they are able to handle the higher voltages required for programming and erasing operations. These high voltage devices usually need to be specially designed to withstand the high voltage stress generated during the programming and erasing process of the memory cells.

[0004] Currently, in 0.18um~90nm embedded flash memory technology, a floating gate (FG) is generally used as the gate of a high voltage (HV) device.

[0005] However, the inventors have found that after reaching the 55nm embedded FG flash memory technology node (less than 55nm), embedded flash memory high-voltage devices are difficult to manufacture, or the manufactured results are not ideal. Summary of the invention

[0006] In order to solve at least one of the above problems, the inventors conducted a lot of research and found that after reaching the 55nm embedded FG flash memory technology node, the reason why embedded flash memory high-voltage devices are difficult to prepare is mainly that the structure of the high-voltage devices in the prior art is mainly: the gate of the HVNMOS structure is an N-type gate, and the gate of the HVPMOS (High Voltage P-channel Metal-Oxide-Semiconductor, High Voltage P-doped Metal Oxide Semiconductor) structure is a P-type gate; in particular, the threshold voltage of the embedded flash memory HVNMOS device with an N-type gate is high, which leads to a small read current and a small read window after writing, which not only leads to poor device performance, but also is not conducive to the miniaturization of the device. Based on this discovery, the inventors conducted a lot of experiments and found that in the HVNMOS structure of the embedded flash memory high-voltage device, setting its gate to a P-type gate can reduce its threshold voltage. Therefore, according to one aspect of the present invention, an embedded flash memory high-voltage device is provided.

[0007] The embedded flash memory high voltage device is a HVNMOS (High Voltage N-channel Metal-Oxide-Semiconductor) device, and its gate is a P-type gate.

[0008] After setting the gate of the embedded flash memory HVNMOS device to a P-type gate, the inventors found that the threshold voltage of the embedded flash memory HVNMOS of the present application is approximately -0.9V; while the threshold voltage of a conventional embedded flash memory HVNMOS device with an N-type gate is approximately -1.5V; it can be seen that compared with the conventional embedded flash memory HVNMOS device, the threshold voltage of the embedded flash memory HVNMOS of the present application is lowered, the read current is increased, and the read window is increased, thereby providing convenience for the miniaturization of the device.

[0009] In some embodiments, the P-type gate includes a floating gate layer, and the floating gate layer is a P-type floating gate layer. That is, the present invention designs a FG_P type (p-type doped floating gate) embedded flash memory high voltage device so that the threshold voltage can be reduced.

[0010] In some embodiments, the channel length of the HVNMOS device is set to range from 0.4 to 0.8 μm.

[0011] For low voltage MOS devices, since only logic gates are set at the gates and there is no floating gate, there is no question of whether the floating gate is P-type or N-type. However, when the device is an HVNMOS device, since a floating gate is set in the gate of the HVNMOS device, as mentioned above, if the floating gate in the HVNMOS device is a common N-type gate, it will result in a higher threshold voltage.

[0012] Although the present invention can effectively reduce the threshold voltage by setting the floating gate layer of the HVNMOS device as a P-type floating gate layer, setting the floating gate layer of the HVNMOS device as a P-type floating gate layer will cause the energy band to change, the conduction channel to move downward, form a buried channel, and cause leakage.

[0013] In order to solve the problem that the conduction channel moves downward, forms a buried channel, reduces the conduction capability, and causes leakage due to the floating gate layer of the HVNMOS device being set as a P-type floating gate layer, the inventors have conducted many research experiments and found that limiting the channel length range of the HVNMOS device to 0.4~0.8μm can effectively avoid the leakage problem.

[0014] In some embodiments, the P-type floating gate layer is made of P-type polysilicon.

[0015] In some embodiments, the P-type gate includes a logic gate layer, and the logic gate layer is a P-type logic gate layer, so as to facilitate the fabrication of the logic gate and the floating gate.

[0016] In some embodiments, the P-type logic gate layer is made of P-type polysilicon.

[0017] In some embodiments, the P-type gate includes a HVOX (high threshold voltage oxide layer, High Voltage Oxide) layer, a floating gate layer and a logic gate layer connected in sequence, and an ONO (Oxide-Nitride-Oxide, usually composed of two layers of silicon oxide (SiO2) sandwiched by a layer of silicon nitride (Si3N4)) layer separating the HVOX layer from the logic gate layer.

[0018] In some embodiments, the HVNMOS is located in a High Voltage P-Well (HVPW).

[0019] In some embodiments, the source region and / or the drain region of the embedded flash memory high voltage device is N-type.

[0020] Preferably, the embedded flash memory high voltage device further includes an STI (Shallow Trench Isolation) structure arranged at intervals, wherein the STI structure is arranged on both sides of the substrate and is located below the gate.

[0021] Preferably, the embedded flash memory high voltage device further comprises an N-type source region and an N-type drain region which are arranged at intervals, and the N-type source region and the N-type drain region are respectively located on two sides of the gate.

[0022] According to another aspect of the present invention, a method for preparing the aforementioned embedded flash memory high-voltage device is provided, in which the high-voltage device is an HVNMOS device, and P-type doping is performed when preparing the gate of the HVNMOS device. The traditional preparation method is to perform P-type doping after preparing the gate. This method of performing P-type doping after preparing the gate requires a high concentration of P-type doping in the gate, and then the P-type doping is diffused uniformly by high-temperature heating. Moreover, a mask is required during the preparation process, which makes the traditional preparation method not only complicated in process but also expensive. However, the present application performs P-type doping while preparing the gate, which not only does not require the use of a high concentration of P-type doping, but also does not require high-temperature heating for diffusion treatment, and does not require the use of a mask, which is easy to operate and saves costs.

[0023] Since the embedded flash high voltage device has reached 55nm, the cell is getting smaller and smaller. If the self-aligned (Self_aligned) FG process technology is not used in the preparation process, the deviation of the preparation will be large, and the misalignment of FG_PH (floating gate pattern) will cause the formation of FG to fail to achieve the ideal effect (for example, the success rate is low). Therefore, in some embodiments, the P-type doping is to perform P-type doping on the floating gate when the floating gate in the gate is self-aligned. In this way, the problem of poor performance and preparation failure caused by misalignment in the preparation process can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a top view of an embedded flash memory high voltage device according to an embodiment of the present invention;

[0025] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of an embedded flash memory high voltage device is shown;

[0026] Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure of an embedded flash memory high voltage device is shown;

[0027] Figure 4 It is a schematic cross-sectional structure diagram of a 2T_Cell of an embedded flash memory high voltage device according to an embodiment of the present invention;

[0028] Figure 5 A schematic flow chart of a method for preparing an embedded flash memory high voltage device according to an embodiment of the present invention;

[0029] Figure numerals: 21, substrate; 22, STI structure; 23, HVPW; 24, HVOX; 25, FG; 26, ONO; 27, LG (logic gate); 28, N-type source region; 29, N-type drain region; 31, spacer (spacer); 41, SL (source line); 42, CG (control gate); 43, SG (select gate); 44, BL (bit line); 45, internal electrode. DETAILED DESCRIPTION

[0030] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0031] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include" and "comprise" include not only those elements, but also other elements that are not explicitly listed, or also include elements inherent to such processes, methods, articles or equipment. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or equipment that includes the elements. The terms used in this article are generally commonly used terms by those skilled in the art. If they are inconsistent with commonly used terms, the terms in this article shall prevail.

[0032] In the present invention, “PH” in the term “FG_PH” means photo.

[0033] In the present invention, the term "Cell" refers to a storage unit, which is generally composed of multiple parts, including FG, control gate (CG), source (S), drain (D) and substrate, among which the floating gate is used to store charges, and these charges represent the stored data. The floating gate is surrounded by insulating materials, so that the charges stored in it can be maintained for a long time, thereby realizing non-volatile storage; the control gate is located above the floating gate, and the reading, programming (writing) and erasing operations of the storage cell can be controlled by changing the voltage on the control gate; the source and drain are the two endpoints of the storage cell, which are used for input and output current respectively. In programming and erasing operations, the source and drain are used to control the flow of current.

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] Figures 1 to 4 The embedded flash memory high voltage device according to one embodiment of the present invention is schematically shown. Figure 3As shown, the embedded flash memory high voltage device is a HVNMOS (High Voltage N-channel Metal-Oxide-Semiconductor) device, and its gate is a P-type gate. The inventor sets the gate as a P-type gate in the HVNMOS structure of the embedded flash memory high voltage device, which can reduce the threshold voltage, increase the read current, and increase the read window, thereby facilitating the miniaturization of the device.

[0036] In some preferred embodiments, the P-type gate includes a floating gate layer, and the floating gate layer is a P-type floating gate layer. The present invention designs a FG_P type (p-type doped floating gate) embedded flash memory high voltage device so that the threshold voltage can be reduced. Preferably, the P-type floating gate layer is made of P-type polysilicon.

[0037] Although the present invention can effectively reduce the threshold voltage by setting the floating gate layer of the HVNMOS device as a P-type floating gate layer. However, setting the floating gate layer of the HVNMOS device as a P-type floating gate layer will cause the energy band to change, the conduction channel to move down, form a buried channel, and leakage to occur. In order to solve the problem of the conduction channel moving down, forming a buried channel, reduced conduction capability, and leakage to occur due to the floating gate layer of the HVNMOS device being set as a P-type floating gate layer. In some preferred embodiments, the channel length range of the HVNMOS device is limited to 0.4~0.8μm, such as 0.4μm, 0.5μm, 0.6μm, 0.8μm, etc., thereby improving the conduction capability and effectively avoiding the problem of leakage.

[0038] In some preferred embodiments, the P-type gate includes a logic gate layer, and the logic gate layer is a P-type logic gate layer. Preferably, the P-type logic gate layer is made of P-type polysilicon.

[0039] In some preferred embodiments, the P-type gate includes a HVOX (high threshold voltage oxide layer, High Voltage Oxide) layer, a floating gate layer and a logic gate layer connected in sequence, and an ONO (Oxide-Nitride-Oxide, usually composed of two layers of silicon oxide (SiO2) sandwiched by a layer of silicon nitride (Si3N4)) layer separating the HVOX layer from the logic gate layer.

[0040] In some preferred embodiments, the HVNMOS is located in a HVPW (High Voltage P-Well).

[0041] In some preferred embodiments, the source region and / or the drain region of the embedded flash memory high voltage device is of N type.

[0042] Preferably, the embedded flash memory high voltage device further includes an STI (Shallow Trench Isolation) structure arranged at intervals, wherein the STI structure is arranged on both sides of the substrate and is located below the gate.

[0043] Preferably, the embedded flash memory high voltage device further comprises an N-type source region and an N-type drain region which are arranged at intervals, and the N-type source region and the N-type drain region are respectively located on two sides of the gate.

[0044] In some preferred embodiments, the high voltage device is an HVNMOS device, and P-type doping is performed when preparing the gate of the HVNMOS device. In the present application, by performing P-type doping while preparing the gate, not only is it unnecessary to use a high concentration of P-type doping, but it is also unnecessary to perform high temperature heating for diffusion treatment, and it is also unnecessary to use a mask, which is simple to operate and saves costs.

[0045] In some preferred embodiments, the P-type doping is to perform P-type doping on the floating gate when the floating gate in the gate is self-aligned, thereby avoiding the problem of poor performance and manufacturing failure caused by misalignment in the manufacturing process.

[0046] The method for preparing the embedded flash memory high voltage device of the present invention is described in detail below in conjunction with specific embodiments.

[0047] Example 1

[0048] S11: Formation of STI.

[0049] In step S11 , STI is prepared by HARP Deposition (High Aspect Ratio Process Deposition).

[0050] S12: Prepare Cell and IMP (Implant Profile) layer related to high pressure.

[0051] In step S12, when preparing the Cell and / or HV well, the threshold voltage is adjusted, for example, by increasing the P-type implantation dose so that the threshold voltage reaches above 0.85V.

[0052] S13: Preparation of high voltage and Cell GOX (Gate Oxide, referred to as gate oxide layer).

[0053] S14: Prepare FG using Self_aligned FG process technology.

[0054] In step S14, P-type doping is performed on the FG while the FG is being prepared.

[0055] S15: preparing an ONO layer.

[0056] S16: preparing an LV GOX (Low Voltage Gate Oxide, a gate oxide layer of a transistor for low voltage operation) layer.

[0057] S17: performing a first deposition on the LG layer.

[0058] S18: Perform P3 etching.

[0059] In step S18, P3 etching is performed by etching the LG layer and the ONO layer.

[0060] In the present application, P3 etching is the etching performed when preparing the LG layer. Specifically, when preparing the LG layer, it is generally prepared in two times. For example, when a 1000 angstrom LG layer needs to be prepared, a 300 angstrom first layer can be prepared first, and then the first layer is locally etched until the FG layer is etched. Then, a second layer is grown on the etched first layer, and it is ensured that the second layer can contact the FG layer, and at the same time, it is ensured that the sum of the thickness of the first layer and the second layer is 1000 angstroms. The etching in this preparation process is P3 etching.

[0061] S19: performing a second deposition on the LG layer.

[0062] S20: performing passivation (PH) and etching processing on the LG layer.

[0063] S21: High voltage and memory cell gate passivation and etching processing.

[0064] S22: Preparation of high voltage, memory cell, and low voltage (LV) LDD (lightly doped drain) layers.

[0065] S23: Preparation of spacer.

[0066] S24: Perform N-type doping.

[0067] S25: Perform P-type doping.

[0068] S26: Perform SAB (Source / Drain Asymmetric Bias) operation.

[0069] S27: Perform CT (Charge Trap) operation.

[0070] S28: BEOL (Back-End-Of-Line) preparation.

[0071] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. An embedded flash memory high voltage device, characterized in that: The high voltage device is a HVNMOS device, and its gate is a P-type gate; The channel length range of the HVNMOS device is set to 0.4-0.8 μm; Also included are STI structures arranged at intervals, wherein the STI structures are arranged on both sides of the substrate and are located below the gate; The P-type gate includes a HVOX layer, a floating gate layer and a logic gate layer connected in sequence, and an ONO layer separating the HVOX layer from the logic gate layer; The floating gate layer is a P-type floating gate layer; The logic gate layer is a P-type logic gate layer.

2. The embedded flash memory high voltage device according to claim 1, characterized in that: The HVNMOS is located in the HVPW.

3. The embedded flash memory high voltage device according to claim 1, characterized in that: Its source region and / or drain region is of N type.

4. The method for preparing an embedded flash memory high voltage device according to any one of claims 1 to 3, characterized in that: The high-voltage device is a HVNMOS device, and P-type doping is performed when preparing the gate of the HVNMOS device.

5. The method for preparing an embedded flash memory high voltage device according to claim 4, characterized in that: The P-type doping is to perform P-type doping on the floating gate when the floating gate in the gate is self-aligned.

Images