Asymmetric half bridge control circuit, control method thereof and asymmetric half bridge switching power supply

Abstract

The application provides an asymmetric half-bridge control circuit, a control method thereof and an asymmetric half-bridge switching power supply. The asymmetric half-bridge control circuit is used for generating a first driving signal and a second driving signal. The asymmetric half-bridge control circuit comprises a peak current dithering generation circuit and an on-time dithering generation circuit. The peak current dithering generation circuit is used for generating a peak current dithering signal with amplitude dithering at a preset period according to a peak current signal. The on-time dithering generation circuit is used for generating an on-time dithering signal according to a preset on-time signal of the second driving signal and a superimposed signal. The on-time dithering generation circuit controls the superimposed signal to change in size at a preset period, and the superimposed signal and the peak current dithering signal are synchronously increased and / or synchronously decreased at least part of the time in the preset period. The asymmetric half-bridge control circuit, the control method thereof and the asymmetric half-bridge switching power supply can obtain better dithering effect.

Description

Technical Field

[0001] This invention belongs to the field of power electronics, and relates to an asymmetric half-bridge drive control technology, particularly to an asymmetric half-bridge control circuit and its control method, and an asymmetric half-bridge switching power supply. Background Technology

[0002] Improving the power density and efficiency of power supply systems has always been an important research direction. One method is to use switching power supplies and increase the switching frequency; however, increasing the frequency also affects switching losses. Therefore, soft-switching technology is employed in switching power supply systems.

[0003] An asymmetric half-bridge is a type of DC / DC zero-voltage switching converter circuit suitable for medium to low power applications. The asymmetric half-bridge circuit employs a complementary PWM control method with a fixed dead time, requiring no external components. It fully utilizes the distributed characteristics of the circuit itself, achieving zero-voltage switching through the resonance of transformer leakage inductance and switch parasitic capacitance. This circuit maintains the low switching conduction losses of PWM switching mode while eliminating them, thus achieving high efficiency.

[0004] like Figure 1 As shown, the asymmetric half-bridge switching power supply includes a primary-side circuit and a secondary-side circuit. The primary-side circuit includes an input capacitor, a half-bridge circuit, and a resonant circuit. The half-bridge circuit includes a first switching transistor Q1 and a second switching transistor Q2. Figure 2 This is a waveform diagram of each signal in an asymmetric half-bridge switching power supply, combined with... Figure 1 and Figure 2 It can be seen that after the first switch Q1 is turned off, the magnetizing current IMAG is a positive current. The switching power supply uses the magnetizing current IMAG to charge the parasitic capacitance of the first switch and discharge the parasitic capacitance of the second switch. The voltage across the first switch Q1 rises, and the voltage across the second switch Q2 falls. The voltage across the second switch Q2 corresponds to the midpoint voltage VHB of the bridge arm. When the voltage across the second switch Q2 drops to zero, the drive control circuit controls the second switch Q2 to turn on, thereby achieving zero-voltage turn-on (ZVS) of the second switch Q2. The specific modal analysis of the asymmetric half-bridge switching power supply is as follows, such as... Figure 2In the current signal, the dashed segment represents the magnetizing current IMAG, and the solid segment represents the bridge arm current IHB. There is some overlap between the magnetizing current IMAG and the bridge arm current IHB. The time period t1-t2 is the energy storage stage. During this stage, the input voltage Vin charges the resonant inductor Lr, the magnetizing inductor Lm, and the resonant capacitor Cr. The bridge arm current IHB increases, and the capacitor voltage Vcr of the resonant capacitor increases. If the conduction time TonH of the first switch is short, it can be approximated that Vcr = N * Vout. The bridge arm current IHB and the magnetizing current IMAG increase linearly with a slope of (Vin - N * Vout) / (Lm + Lr), where N is the transformer turns ratio, Vout is the output voltage, Lm is the inductance of the magnetizing inductor, and Lr is the inductance of the resonant inductor. The time interval t2-t3 is the dead zone, during which the second switching transistor can achieve ZVS. During this phase, both the upper and lower transistors are off. The magnetizing current is the peak magnetizing current IMAGpos. The magnetizing current discharges the junction capacitance of the lower transistor and charges the junction capacitance of the upper transistor, causing the midpoint voltage VHB of the bridge arm to change from Vin to 0V. Turning on the lower transistor then achieves zero-voltage turn-on. The time interval t3-t4 is the energy transfer phase. During this phase, the secondary diode conducts, and energy is transferred from the primary circuit to the secondary circuit. The voltage Vpr i of the magnetizing inductor Lm is clamped by the secondary side, Vpr i≈N*Vout, and the magnetizing current IMAG decreases linearly. The bridge arm current IHB is determined by the resonance of the resonant inductor Lr and the resonant capacitor Cr. The time interval t4-t5 is the circulating current phase. At time t4, the resonant current and the magnetizing current converge, the secondary current reaches zero, and the secondary diode turns off. Afterwards, the excitation voltage is no longer clamped by the secondary side, and the excitation inductor Lm re-participates in the resonance process. The resonant capacitor Cr resonates with the resonant inductor and the excitation inductor. The time period t5-t6 is a dead zone, during which the upper transistor can achieve zero-voltage switching (ZVS); this process is similar to that of the time period t2-t3. Both the upper and lower transistors are turned off. At this time, the excitation current is a negative current IMAGneg. The excitation current discharges the junction capacitance of the upper transistor and charges the junction capacitance of the lower transistor, causing the bridge arm midpoint voltage VHB to change from 0V to Vin. After that, turning on the upper transistor achieves zero-voltage turn-on.

[0005] From the modal analysis above, it can be seen that the turn-off of the first switch Q1 typically depends on peak current control, i.e., the bridge arm current IHB. When the bridge arm current IHB exceeds the excitation peak current IMAGpos, GH turns off. The negative current IMAGneg corresponding to the turn-off of the lower switch depends on the adaptive ZVS control result and can be considered a fixed parameter under given system and input / output conditions. Therefore, without additional processing, the AHB operating frequency is fixed under given system and operating conditions. Fixed-frequency operation leads to difficulties in electromagnetic interference (EMI) debugging, thus requiring frequency dithering technology to optimize EMI processing. For fixed-frequency control systems, frequency dithering can be directly applied, but for systems like... Figure 1 The asymmetric half-bridge switching power supply is obviously not a fixed-frequency system, so the method of directly jittering the frequency is not suitable for solving the EMI problem.

[0006] In view of this, there is a need to provide a new structure or control method to solve at least some of the above problems. Summary of the Invention

[0007] To address one or more problems in the prior art, this invention proposes an asymmetric half-bridge control circuit and its control method, as well as an asymmetric half-bridge switching power supply.

[0008] According to one aspect of the present invention, an asymmetric half-bridge control circuit is disclosed. The asymmetric half-bridge control circuit generates a first drive signal to drive a first switch in the half-bridge circuit, and generates a second drive signal to drive a second switch in the half-bridge circuit. The asymmetric half-bridge control circuit includes:

[0009] A peak current frequency dithering generation circuit, whose input terminal is used to receive a peak current signal used to control the excitation peak current, and used to generate a peak current frequency dithering signal with amplitude dithering at a preset period based on the peak current signal; and

[0010] An on-time jitter generation circuit, whose input is coupled to a peak current jitter generation circuit, is used to generate an on-time jitter signal based on a preset on-time signal and a superimposed signal of the second driving signal. The on-time jitter generation circuit controls the superimposed signal to vary in magnitude according to the preset period, and the superimposed signal and the peak current jitter signal increase and / or decrease synchronously for at least a portion of the preset period. The asymmetric half-bridge control circuit controls the excitation peak current according to the peak current jitter signal and controls the on-time of the second driving signal according to the on-time jitter signal.

[0011] In one embodiment, the preset period includes a first time interval and a second time interval. The turn-on time dithering generation circuit controls the superimposed signal to be zero or within a preset range during the second time interval. The second switch is turned on with zero voltage during the second time interval.

[0012] In one embodiment, within a first time interval, the superimposed signal and the peak current dithering signal are synchronously increased or decreased.

[0013] In one embodiment, the preset period is a fixed value or varies according to the switching frequency of the first switching transistor.

[0014] In one embodiment, the peak current dithering generation circuit is further configured to receive a first drive signal and control the preset period according to the first drive signal.

[0015] In one embodiment, the peak current dithering generation circuit includes:

[0016] The first processing circuit has an input terminal for receiving the peak current signal and for generating a minimum threshold for the peak current based on the peak current signal.

[0017] The second processing circuit has its input terminal used to receive the peak current signal and to generate the peak current maximum threshold based on the peak current signal.

[0018] The first comparator circuit has its first input terminal coupled to the output terminal of the first processing circuit, and its second input terminal receiving the peak current dithering signal.

[0019] The second comparator circuit has a first input terminal that receives the peak current dithering signal and a second input terminal that is coupled to the output terminal of the second processing circuit.

[0020] The trigger circuit has its set terminal coupled to the output terminal of the first comparator circuit and its reset terminal coupled to the output terminal of the second comparator circuit.

[0021] A first current source is used to provide the first current;

[0022] A first switch, the first terminal of which is coupled to a first current source;

[0023] The second current source has its first terminal coupled to the second terminal of the first switch, and its second terminal coupled to ground.

[0024] A second switch, connected in series with a second current source, controls the on / off state of the second current source; and

[0025] The first capacitor has its first terminal coupled to the second terminal of the first switch, and its second terminal coupled to ground. Its first terminal is used to output the peak current jitter signal.

[0026] In one embodiment, the turn-on time dithering generation circuit includes a superimposed signal generation circuit, which controls the superimposed signal to increase or decrease synchronously within a first time interval according to the peak current dithering signal within a range of variation, and controls the superimposed signal to remain zero within a second time interval.

[0027] According to another aspect of the present invention, an asymmetric half-bridge switching power supply is disclosed, the asymmetric half-bridge switching power supply including a primary side circuit, a secondary side circuit and a transformer winding, wherein the primary side circuit includes the asymmetric half-bridge control circuit as described in any of the preceding claims.

[0028] According to another aspect of the present invention, an asymmetric half-bridge control method is disclosed for controlling an asymmetric half-bridge control circuit. The asymmetric half-bridge control circuit is used to generate a first drive signal to drive a first switch in the half-bridge circuit, and to generate a second drive signal to drive a second switch in the half-bridge circuit. The asymmetric half-bridge control method includes:

[0029] Receives a peak current signal used to control the excitation peak current, and generates a peak current frequency dithering signal with amplitude dithering at a preset period based on the peak current signal; and

[0030] An on-time jitter signal is generated based on the preset on-time signal and the superimposed signal of the second driving signal; the superimposed signal is controlled to change in magnitude at a preset period, and the superimposed signal and the peak current jitter signal are synchronously increased and / or synchronously decreased for at least a part of the preset period.

[0031] In one embodiment, the asymmetric half-bridge control method further includes: a preset period including a first time interval and a second time interval, controlling the superimposed signal to be zero or within a preset range during the second time interval; and the second switching transistor to be turned on at zero voltage during the second time interval.

[0032] In one embodiment, within a first time interval, the superimposed signal and the peak current dithering signal are synchronously increased or decreased.

[0033] In one embodiment, the preset period is a fixed value or varies according to the switching frequency of the first switching transistor.

[0034] This invention proposes an asymmetric half-bridge control circuit and its control method, as well as an asymmetric half-bridge switching power supply. The asymmetric half-bridge control circuit generates a first drive signal to drive a first switch in the half-bridge circuit, and also generates a second drive signal to drive a second switch in the half-bridge circuit. The asymmetric half-bridge control circuit includes a peak current jitter generation circuit and a turn-on time jitter generation circuit. The input of the peak current jitter generation circuit receives a peak current signal used to control the excitation peak current, and generates a peak current jitter signal with amplitude jittering at a preset period based on the peak current signal. The input of the turn-on time jitter generation circuit is coupled to the peak current jitter generation circuit, and generates a turn-on time jitter signal based on a preset turn-on time signal of the second drive signal and a superimposed signal. The turn-on time jitter generation circuit controls the superimposed signal to change magnitude at the preset period, and for at least a portion of the preset period, the superimposed signal and the peak current jitter signal increase and / or decrease synchronously. The asymmetric half-bridge control circuit controls the excitation peak current based on the peak current dithering signal and controls the turn-on time of the second drive signal based on the turn-on time dithering signal. The asymmetric half-bridge control circuit and its control method proposed in this invention, along with the asymmetric half-bridge switching power supply, can achieve better dithering effects, thereby effectively solving the electromagnetic interference problem. Furthermore, it does not affect the zero-voltage switching effect of the asymmetric half-bridge switching power supply. Attached Figure Description

[0035] The accompanying drawings are provided to further illustrate the invention and, together with the description, serve to explain embodiments of the invention, but do not constitute a limitation thereof. In the drawings:

[0036] Figure 1 A schematic diagram of the circuit structure of a prior art asymmetric half-bridge switching power supply is shown.

[0037] Figure 2 A waveform diagram of a portion of the signals in a prior art asymmetric half-bridge switching power supply is shown.

[0038] Figure 3 A schematic diagram of the circuit structure of an asymmetric half-bridge control circuit according to an embodiment of the present invention is shown.

[0039] Figure 4 A waveform diagram of a portion of the signals of an asymmetric half-bridge control circuit according to an embodiment of the present invention is shown.

[0040] Figure 5 A schematic diagram of the circuit structure of another asymmetric half-bridge control circuit according to an embodiment of the present invention is shown.

[0041] Figure 6 A waveform diagram of a portion of the signals of another asymmetric half-bridge control circuit according to an embodiment of the present invention is shown.

[0042] Figure 7 The diagram shows a waveform of a portion of the signals of an asymmetric half-bridge control circuit according to an embodiment of the present invention. Detailed Implementation

[0043] To further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, and not for limiting the scope of the claims of the present invention.

[0044] The description in this section pertains to only a few typical embodiments, and the present invention is not limited to the scope of the embodiments described. Combinations of different embodiments, substitution of some technical features in different embodiments, and substitution of similar or identical prior art with some technical features in the embodiments are also within the scope of the description and protection of the present invention.

[0045] The terms "coupled" or "connected" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection through an electrically conductive medium like a conductor, which may contain parasitic inductance or capacitance. It can also be a connection through intermediate circuits or components described in the embodiments of this specification. Indirect connections may also include connections through other active or passive devices that achieve the same or similar functions, such as connections through switches, signal amplification circuits, follower circuits, or other circuits or components. "A plurality of" or "more" indicates two or more. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship or order between these technical features.

[0046] One embodiment of the present invention discloses an asymmetric half-bridge control circuit, which is used to control the half-bridge circuit in an asymmetric half-bridge switching power supply. The half-bridge circuit includes a first switching transistor and a second switching transistor. The first switching transistor is the upper transistor of the half-bridge circuit, and the second switching transistor is the lower transistor of the half-bridge circuit. The asymmetric half-bridge control circuit generates a first drive signal to drive the first switching transistor, and also generates a second drive signal to drive the second switching transistor. Figure 3 As shown, the asymmetric half-bridge control circuit includes a peak current jitter generation circuit 10 and an on-time jitter generation circuit 20. The input of the peak current jitter generation circuit 10 receives a peak current signal Vcs used to control the excitation peak current. The peak current jitter generation circuit 10 generates a peak current jitter signal Vcs_jitter that jitters at a preset period based on the peak current signal Vcs. The excitation peak current can be the peak current flowing through the excitation inductor. In one embodiment, the peak current signal can be a voltage signal. In a typical scheme, the peak current signal is a fixed value, and the peak current signal Vcs is used to control the peak current flowing through the excitation inductor. In this invention, the peak current signal is used as the initial signal, and after processing, a peak current jitter signal is obtained. The peak current jitter signal is a signal with fluctuating amplitude. Specifically, the peak current jitter signal changes amplitude within a preset period and a preset range. In a specific embodiment, a sampling resistor is provided in the resonant cavity of the asymmetric half-bridge switching power supply. The asymmetric half-bridge control circuit obtains a sampling signal through a sampling resistor and generates a first drive signal based on the sampling signal and the peak current jitter signal. When the sampling signal reaches the peak current jitter signal, the asymmetric half-bridge control circuit controls the first switch to turn off. When the sampling signal has not yet reached the peak current jitter signal, the asymmetric half-bridge control circuit can control the first switch to remain on. Therefore, the asymmetric half-bridge control circuit controls the excitation peak current according to the peak current jitter signal.

[0047] like Figure 3As shown, the input terminal of the turn-on time jitter generation circuit 20 is coupled to the peak current jitter generation circuit 10. The turn-on time jitter generation circuit 20 is used to generate a turn-on time jitter signal TonL based on the preset turn-on time signal of the second driving signal and the superimposed signal. The oscillation circuit in the asymmetric half-bridge switching power supply generates a driving signal GL to control the second driving signal. The preset turn-on time signal of the second driving signal can be obtained through the driving signal GL. The turn-on time jitter generation circuit controls the superimposed signal to change in magnitude with a preset period. For at least a portion of the preset period, the superimposed signal and the peak current jitter signal increase synchronously, that is, when the peak current jitter signal increases for at least a portion of the preset period, the superimposed signal increases. In another embodiment, for at least a portion of the preset period, the superimposed signal and the peak current jitter signal decrease synchronously, that is, when the peak current jitter signal decreases for at least a portion of the preset period, the superimposed signal decreases. In yet another embodiment, for at least a portion of the preset period, the superimposed signal and the peak current jitter signal increase and decrease synchronously. The asymmetric half-bridge control circuit controls the turn-on time of the second driving signal based on the turn-on time jitter signal.

[0048] In another embodiment of the invention, such as Figure 4 As shown, Figure 4 The figure above shows the numerical change of the signal dVcs / Vcs over time. It can be seen that the amplitude of the peak current dithering signal varies from -a%*Vcs to a%*Vcs. Figure 4 The figure below shows the numerical change of the superimposed signal ΔTonL over time. The preset period includes a first time interval D1 and a second time interval D2. Within the first time interval D1, the superimposed signal ΔTonL increases and decreases synchronously with the peak current jitter signal; that is, when the peak current jitter signal increases, the superimposed signal increases; and when the peak current jitter signal decreases, the superimposed signal decreases. Within the second time interval D2, the superimposed signal is zero, thus not affecting the zero-voltage turn-on of the second switch during the second time interval.

[0049] In this invention, to achieve better frequency jittering in the asymmetric half-bridge switching power supply, the peak current jittering signal of the first switching transistor and the turn-on time TonL of the second switching transistor are controlled to jitter synchronously. Considering that the turn-on time TonL of the second switching transistor affects the adaptive zero-voltage turn-on effect, the preset period is divided into a first time interval D1 and a second time interval D2. The advantage of this invention is that the existence of the second time interval D2 does not affect the control effect of adaptive zero-voltage turn-on. Furthermore, when the peak current jittering signal increases, the peak current IMAGpos increases, the turn-on time TonH of the first drive signal increases, and the turn-on time TonL of the second drive signal also increases according to the setting, increasing the overall switching cycle and resulting in a significant frequency change. The increase in the turn-on time TonL of the second drive signal causes a decrease in the negative current IMAGneg of the excitation current (i.e., an increase in the absolute value of IMAGneg), which, together with the increase in the peak current IMAGpos, precisely offsets the increase in the average current, resulting in a small change in output power and a minimal increase in output ripple. In addition, the scheme of this invention makes it easier to achieve frequency divergence, resulting in a better frequency jittering effect. In summary, the technical solution of the present invention can effectively improve the electromagnetic interference problem.

[0050] In one embodiment, the preset period is a fixed value. Both the peak current jitter signal and the turn-on time jitter signal vary in magnitude according to the preset period. In another embodiment, the asymmetric half-bridge control circuit varies according to the switching frequency of the first switching transistor. The peak current jitter generation circuit is also used to receive a first drive signal and control the preset period according to the first drive signal.

[0051] like Figure 5As shown, one embodiment provides an asymmetric half-bridge control circuit. The peak current jitter generation circuit includes a first processing circuit, a second processing circuit, a first comparison circuit U1, a second comparison circuit U2, a trigger circuit U3, a first current source I1, a second current source I2, a first switch S1, a second switch S2, and a first capacitor C1. The input terminal of the first processing circuit receives the peak current signal Vcs and generates a minimum peak current threshold Vcs*(1-a%) based on the peak current signal Vcs. The input terminal of the second processing circuit receives the peak current signal Vcs and generates a maximum peak current threshold Vcs*(1+a%) based on the peak current signal Vcs. The first input terminal of the first comparison circuit U1 is coupled to the output terminal of the first processing circuit, the second input terminal of the first comparison circuit U1 receives the peak current jitter signal Vcs_jitter, and the output of the first comparison circuit U1 is a first comparison result. The first input terminal of the second comparator circuit U2 receives the peak current jitter signal Vcs_jitter. The second input terminal of the second comparator circuit U2 is coupled to the output terminal of the second processing circuit. The output of the second comparator circuit U2 is the second comparison result. The set terminal of the trigger circuit U3 is coupled to the output terminal of the first comparator circuit, and the reset terminal of the trigger circuit U3 is coupled to the output terminal of the second comparator circuit. The first current source I1 provides a first current I1, I1 = Vcs * gm, where Vcs is the peak current signal and gm is the gain coefficient. The first terminal of the first switch S1 is coupled to the first current source. The first terminal of the second current source I2 is coupled to the second terminal of the first switch S1, and the second terminal of the second current source I2 is coupled to ground. The second current source I2 provides a second current, I2 = Vcs * gm, where Vcs is the peak current signal and gm is the gain coefficient. The second switch S2 is connected in series with the second current source I1 to control the on / off state of the second current source. The second switch S2 can be coupled between the first switch and the second current source, or the second switch S2 can be coupled between the second current source and ground. The first output terminal of the trigger circuit U3 is coupled to the switching control terminal of the first switch S1, and the second output terminal of the trigger circuit U3 is coupled to the switching control terminal of the second switch S2. The first terminal of the first capacitor C1 is coupled to the second terminal of the first switch S1, and the second terminal of the first capacitor C1 is coupled to ground. The first terminal of the first capacitor C1 is used to output the peak current jitter signal Vcs_jitter.

[0052] like Figure 5As shown, the turn-on time jitter generation circuit includes a third processing circuit, a third comparator circuit U4, and a fourth processing circuit. The input of the third processing circuit receives the peak current signal Vcs and generates a processed signal based on Vcs, which is Vcs*(1-a%+2a%*D2). The first input of the third comparator circuit U4 receives the peak current jitter signal Vcs_jitter, and the second input of the third comparator circuit U4 is coupled to the output of the third processing circuit. The output of the third comparator circuit U4 outputs the signal TonL_jitter_on. The first input of the fourth processing circuit is coupled to the first output of the trigger circuit, and the second input of the fourth processing circuit is coupled to the second output of the trigger circuit. The clock port of the fourth processing circuit is coupled to the drive signal GL, and the enable port of the fourth processing circuit is coupled to the output of the third comparator circuit U4. When the receive signal of the enable port is at a first level (e.g., high level), and the charge signal is at a first level (e.g., high level), the on-time TonL of the second drive signal increases; when the discharge signal is at a first level (e.g., high level), the on-time TonL of the second drive signal decreases. (Combined with...) Figure 5 and Figure 6 It can be seen that when the signal charge output from the first output terminal of the trigger circuit is at the first level (e.g., high level), the peak current jitter signal Vcs_jitter gradually increases; when the signal charge output from the first output terminal of the trigger circuit is at the second level (e.g., low level), the peak current jitter signal Vcs_jitter gradually decreases. Within the first time interval D1, that is, when the peak current jitter signal Vcs_jitter is greater than the processed signal Vcs*(1-a%+2a%*D2), the superimposed signal increases and decreases synchronously with the peak current jitter signal. Within the second time interval D2, the superimposed signal remains zero. In this embodiment, the preset period is Tjitter = 4a%*C1 / gm, where C1 is the capacitance value of the first capacitor and gm is the gain coefficient. It should be noted that... Figure 5 Only for the purpose of implementing this invention Figure 4 One specific embodiment, which can be understood by those skilled in the art based on Figure 4 The principle is used to obtain other implementation circuits.

[0053] like Figure 7 The figure shows the frequency jitter effect of an asymmetric half-bridge switching power supply. The CS peak jitter waveform is the peak current jitter signal Vcs_jitter. TonL is the turn-on time of the second drive signal; zero-voltage turn-on can be achieved during the time period from ta to tb. ILm is the transformer magnetizing current, and its envelope characterizes the period.

[0054] Another embodiment of the present invention discloses an asymmetric half-bridge switching power supply, which includes a primary circuit, a secondary circuit, and a transformer winding. The primary circuit includes the asymmetric half-bridge control circuit as described in any of the preceding claims.

[0055] Another embodiment of the present invention discloses an asymmetric half-bridge control method for controlling an asymmetric half-bridge control circuit. The asymmetric half-bridge control circuit generates a first drive signal to drive a first switch in the half-bridge circuit and generates a second drive signal to drive a second switch in the half-bridge circuit. The asymmetric half-bridge control method includes:

[0056] Receives a peak current signal used to control the excitation peak current, and generates a peak current frequency dithering signal with amplitude dithering at a preset period based on the peak current signal; and

[0057] An on-time jitter signal is generated based on the preset on-time signal and the superimposed signal of the second driving signal; the superimposed signal is controlled to change in magnitude at a preset period, and the superimposed signal and the peak current jitter signal are synchronously increased and / or synchronously decreased for at least a part of the preset period.

[0058] In one embodiment, the asymmetric half-bridge control method further includes: a preset period including a first time interval and a second time interval, controlling the superimposed signal to be zero or within a preset range during the second time interval; and the second switch being turned on at zero voltage during the second time interval.

[0059] In another embodiment, within a first time interval, the superimposed signal and the peak current dithering signal are synchronously increased or decreased.

[0060] In another embodiment, the preset period is a fixed value or varies according to the switching frequency of the first switching transistor.

[0061] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input" and "inverting input" in the logic control involved in the specification or drawings can be interchanged or changed, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic control.

[0062] The description and application of the present invention herein are illustrative and not intended to limit the scope of the invention to the embodiments described above. The effects or advantages described in the specification may not be apparent in actual experimental cases due to uncertainties in specific conditions or other factors, and such descriptions are not intended to limit the scope of the invention. Variations and modifications to the embodiments disclosed herein are possible, and various substitutions and equivalents of the components in the embodiments are well known to those skilled in the art. It should be understood by those skilled in the art that the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the invention. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.

Claims

1. An asymmetric half-bridge control circuit, used to generate a first drive signal to drive a first switch in the half-bridge circuit, and used to generate a second drive signal to drive a second switch in the half-bridge circuit, characterized in that, The asymmetric half-bridge control circuit includes: A peak current frequency dithering generation circuit, whose input terminal is used to receive a peak current signal used to control the excitation peak current, and used to generate a peak current frequency dithering signal with amplitude dithering at a preset period based on the peak current signal; and An on-time jitter generation circuit, whose input is coupled to a peak current jitter generation circuit, is used to generate an on-time jitter signal based on a preset on-time signal and a superimposed signal of a second driving signal. The on-time jitter generation circuit controls the superimposed signal to vary in magnitude according to the preset period, and the superimposed signal and the peak current jitter signal increase and / or decrease synchronously for at least a portion of the preset period. The asymmetric half-bridge control circuit controls the excitation peak current based on the peak current jitter signal and controls the on-time of the second driving signal based on the on-time jitter signal. The asymmetric half-bridge control circuit obtains a sampling signal through a sampling resistor and controls the generation of a first driving signal based on the sampling signal and the peak current jitter signal.

2. The asymmetric half-bridge control circuit as described in claim 1, characterized in that, The preset period includes a first time interval and a second time interval. The turn-on time dithering generation circuit controls the superimposed signal to be zero or within a preset range in the second time interval. The second switch is turned on with zero voltage in the second time interval.

3. The asymmetric half-bridge control circuit as described in claim 2, characterized in that, Within the first time interval, the superimposed signal and the peak current dithering signal are increased and decreased synchronously.

4. The asymmetric half-bridge control circuit as described in claim 1, characterized in that, The preset period is a fixed value or varies according to the switching frequency of the first switching transistor.

5. The asymmetric half-bridge control circuit as described in claim 4, characterized in that, The peak current dithering generation circuit is also used to receive a first driving signal and control the preset period according to the first driving signal.

6. The asymmetric half-bridge control circuit as described in claim 1, characterized in that, The peak current dithering generation circuit includes: The first processing circuit has an input terminal for receiving the peak current signal and for generating a minimum threshold for the peak current based on the peak current signal. The second processing circuit has its input terminal used to receive the peak current signal and to generate the peak current maximum threshold based on the peak current signal. The first comparator circuit has its first input terminal coupled to the output terminal of the first processing circuit, and its second input terminal receiving the peak current dithering signal. The second comparator circuit has a first input terminal that receives the peak current dithering signal and a second input terminal that is coupled to the output terminal of the second processing circuit. The trigger circuit has its set terminal coupled to the output terminal of the first comparator circuit and its reset terminal coupled to the output terminal of the second comparator circuit. The first current source is used to provide the first current; The first switch has its first terminal coupled to the first current source; The second current source has its first terminal coupled to the second terminal of the first switch, and its second terminal coupled to ground. A second switch, connected in series with a second current source, controls the on / off state of the second current source; and The first capacitor has its first terminal coupled to the second terminal of the first switch, and its second terminal coupled to ground. Its first terminal is used to output the peak current jitter signal.

7. The asymmetric half-bridge control circuit as described in claim 2, characterized in that, The turn-on time dithering generation circuit includes a superimposed signal generation circuit. The superimposed signal generation circuit controls the superimposed signal to increase or decrease synchronously within a range according to the peak current dithering signal in a first time interval, and controls the superimposed signal to remain zero in a second time interval.

8. An asymmetrical half-bridge switching power supply, the asymmetrical half-bridge switching power supply comprising a primary circuit, a secondary circuit, and a transformer winding, characterized in that, The primary-side circuit includes the asymmetric half-bridge control circuit as described in any one of claims 1-7.

9. An asymmetric half-bridge control method for controlling an asymmetric half-bridge control circuit, wherein the asymmetric half-bridge control circuit generates a first drive signal to drive a first switch in the half-bridge circuit, and generates a second drive signal to drive a second switch in the half-bridge circuit, characterized in that... The asymmetric half-bridge control circuit controls the excitation peak current based on the peak current dithering signal, and controls the turn-on time of the second drive signal based on the turn-on time dithering signal. The asymmetric half-bridge control circuit obtains the sampling signal through the sampling resistor, and controls the generation of the first drive signal based on the sampling signal and the peak current dithering signal; The asymmetric half-bridge control method includes: Receives a peak current signal used to control the excitation peak current, and generates a peak current jittering signal with amplitude jittering at a preset period based on the peak current signal; as well as An on-time jitter signal is generated based on the preset on-time signal and the superimposed signal of the second driving signal; the superimposed signal is controlled to change in magnitude at a preset period, and the superimposed signal and the peak current jitter signal are synchronously increased and / or synchronously decreased for at least a part of the preset period.

10. The asymmetric half-bridge control method as described in claim 9, characterized in that, The asymmetric half-bridge control method also includes: a preset period including a first time interval and a second time interval, controlling the superimposed signal to be zero or within a preset range during the second time interval; and the second switching transistor to be turned on at zero voltage during the second time interval.

11. The asymmetric half-bridge control method as described in claim 10, characterized in that, Within the first time interval, the superimposed signal and the peak current dithering signal are increased and decreased synchronously.

12. The asymmetric half-bridge control method as described in claim 9, characterized in that, The preset period is a fixed value or varies according to the switching frequency of the first switching transistor.

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