A driving circuit for Hys hybrid parallel motor

Abstract

The present application discloses a driving circuit for a Hys hybrid parallel motor. The driving circuit includes a delay circuit module, a comparison circuit module, an amplifier circuit module, a gate drive circuit module, a main control chip, and an isolation drive chip; the isolation drive chip is used to convert the PWM signal transmitted by the main control chip into a drive signal, and output it to the delay circuit module; the delay circuit module delays the drive signal; the comparison circuit module compares the delayed drive signal with the reference voltage, and outputs a control current to the amplifier circuit module, and the amplifier circuit module amplifies the control current and outputs it to the gate drive circuit module; the gate drive circuit module is used to adjust the SiC switch and the IGBT switch respectively. The driving circuit of the present application realizes precise adjustment of two different types of power semiconductor devices, SiC and IGBT, respectively, and realizes real-time optimization of losses according to load.

Description

Technical Field

[0001] The present application relates to the technical field of drive circuits, and in particular to a drive circuit for a Hys hybrid parallel motor. Background Art

[0002] New energy motor systems mostly use HyS (Hybrid Switch) hybrid parallel drive circuits, which play an important role in the field of new energy, especially in electric vehicles and hybrid electric vehicles. The drive circuit is mainly used to control the operation of the motor system, realize the conversion and transmission of electric energy, and drive the vehicle. In new energy motor systems, the HyS hybrid parallel drive circuit improves the efficiency, reliability and economy of the system by optimizing parameters such as switch timing and drive voltage, thereby meeting the power requirements of the vehicle under different working conditions.

[0003] Although the Hys hybrid parallel drive circuit has many advantages in new energy systems, there are still some problems in practical application. The Hys hybrid parallel drive circuit requires the setting of multiple SiC MOSFETs and multiple IGBT MOSFETs to achieve the regulation of switching timing through multiple MOSFETs. However, the current drive circuit design does not take into account the differences in electrical characteristics and working conditions between SiC MOSFET and multiple IGBT MOSFETs. SiC MOSFET and IGBT MOSFET use the same set of drive parameters and can only be turned on or off at the same time. The drive voltages of SiC MOSFET and IGBT MOSFET cannot be differentiated, resulting in high switching losses. Summary of the invention

[0004] To this end, an embodiment of the present application provides a drive circuit for a Hys hybrid parallel motor, which achieves precise adjustment of different types of switching devices and reduces turn-on and turn-off losses.

[0005] This application is achieved through the following technical solutions:

[0006] A driving circuit for a Hys hybrid parallel motor, the driving circuit comprising:

[0007] Delay circuit module, comparison circuit module, amplifier circuit module, gate drive circuit module, main control chip, isolation drive chip; wherein the delay circuit module includes a first delay unit and a second delay unit, the comparison circuit module includes a first comparison unit and a second comparison unit, the amplifier circuit module includes a first amplifier unit and a second amplifier unit; the gate drive circuit module includes a first drive unit and a second drive unit;

[0008] The main control chip is used to transmit PWM signals to the isolation drive chip;

[0009] The isolation driving chip is used to convert the PWM signal into a driving signal and output it to the delay circuit module;

[0010] The delay circuit module is used to delay the received driving signal through the first delay unit and the second delay unit, and transmit two different first delay signals and second delay signals to the comparison circuit module;

[0011] The comparison circuit module is used to compare the received first delayed signal with the reference voltage through the first comparison unit, and output the first control current to the first amplification unit of the amplification circuit module; and is also used to compare the received second delayed signal with the reference voltage through the second comparison unit, and output the second control current to the second amplification unit of the amplification circuit module;

[0012] The amplifying circuit module is used to amplify the first control current and the second control current through the first amplifying unit and the second amplifying unit respectively and then output them to the gate driving circuit module;

[0013] The gate drive circuit module is used to adjust the SiC-MOSFET according to the amplified first control current through the first drive unit and to adjust the IGBT-MOSFET according to the amplified second control current through the second drive unit.

[0014] In a preferred example of the present application, it can be further configured that the first delay unit includes a diode D1, a diode D2, a resistor R1, a resistor R2 and a capacitor C1;

[0015] Among them, the anode of the diode D1 is connected to the output end of the isolation driving chip, the cathode of the diode D1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded; the cathode of the diode D2 is connected to the output end of the isolation driving chip and the anode of the diode D1, the anode of the diode D2 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to one end of the capacitor C1 and the inverting input end of the first comparison unit.

[0016] In a preferred example of the present application, it can be further configured that the second delay unit includes a diode D5, a resistor R5 and a capacitor C2;

[0017] Among them, the cathode of the diode D5 is connected to the output end of the isolation driving chip, and the anode of the diode D5 is connected to the non-inverting input end of the second comparison unit; one end of the resistor R5 is connected to the output end of the isolation driving chip and the cathode of the diode D5, and the other end of the resistor R5 is connected to the anode of the diode D5 and one end of the capacitor C2, and the other end of the capacitor C2 is grounded.

[0018] In a preferred example of the present application, it can be further configured that the first comparison unit includes a comparator N1; the non-phase input terminal of the comparator N1 is connected to the reference voltage, the inverting input terminal of the comparator N1 is connected to the output terminal of the first delay unit, and the output terminal of the comparator N1 is connected to the input terminal of the first amplification unit of the amplification circuit module.

[0019] In a preferred example of the present application, it can be further configured that the second comparison unit includes a comparator N2; the inverting input terminal of the comparator N2 is connected to the reference voltage, the non-phase input terminal of the comparator N2 is connected to the output terminal of the second delay unit, and the output terminal of the comparator N2 is connected to the input terminal of the second amplification unit in the amplification circuit module.

[0020] In a preferred example of the present application, it can be further configured that the first amplifying unit includes: a transistor Q20, a transistor Q21, and the transistor Q20 and the transistor Q21 form a push-pull pair; the base of the transistor Q20 is connected to the output end of the first comparing unit, the collector of the transistor Q20 is connected to the positive electrode of the +18V power supply, and the emitter of the transistor Q20 is connected to the emitter of the transistor Q21 and the input end of the gate drive circuit module; the base of the transistor Q21 is connected to the output end of the second comparing unit, the emitter of the transistor Q21 is connected to the input end of the gate drive circuit module, and the collector of the transistor Q21 is connected to the negative electrode of the -4V power supply.

[0021] In a preferred example of the present application, it can be further configured that the transistor Q20 is an NPN transistor; and the transistor Q21 is a PNP transistor.

[0022] In a preferred example of the present application, it can be further configured that the second amplifying unit includes: a transistor Q22 and a transistor Q23, wherein the transistor Q22 and the transistor Q23 form a push-pull pair; wherein the base of the transistor Q22 and the base of the transistor Q23 are both connected to the output end of the second comparing unit, the collector of the transistor Q22 is connected to the positive electrode of the +18V power supply, the emitter of the transistor Q22 is connected to the emitter of the transistor Q23, the collector of the transistor Q23 is connected to the negative electrode of the -8V power supply, and the emitter of the transistor Q22 and the emitter of the transistor Q22 are connected to the input end of the gate drive circuit module.

[0023] In a preferred example of the present application, it can be further configured that the transistor Q22 is an NPN transistor; and the transistor Q23 is a PNP transistor.

[0024] In a preferred example of the present application, it can be further configured that an isolation optocoupler is also included between the main control chip and the comparison circuit module; the input end of the isolation optocoupler is connected to the output end of the main control chip, and the output end of the isolation optocoupler is connected to the input end of the comparison circuit module.

[0025] In summary, compared with the prior art, the technical solution provided in the embodiment of the present application has at least the following beneficial effects:

[0026] The driving circuit of the present application includes a delay circuit module, a comparison circuit module, an amplifier circuit module, a gate drive circuit module, a main control chip, and an isolation drive chip; the isolation drive chip is used to convert the PWM signal transmitted by the main control chip into a drive signal, and output it to the delay circuit module; the delay circuit module is used to delay the drive signal; the comparison circuit module compares the amplified drive signal with the reference voltage, and outputs the control current to the amplifier circuit module, and the amplifier circuit module amplifies the control current and outputs it to the gate drive circuit module; the gate drive circuit module is used to adjust SiC-MOSFET and IGBT-MOSFET respectively. The driving circuit of the present application realizes precise adjustment of two different types of power semiconductor devices, SiC-MOSFET and control IGBT-MOSFET, respectively, to reduce turn-on and turn-off losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of a drive circuit for a Hys hybrid parallel motor provided in an embodiment of the present application;

[0028] Figure 2 A schematic structural diagram of a driving circuit for a Hys hybrid parallel motor provided in yet another embodiment of the present application;

[0029] Figure 3 A schematic diagram of a drive circuit for a Hys hybrid parallel motor provided in another embodiment of the present application;

[0030] Description of reference numerals:

[0031] Main control chip-1, isolation drive chip-2, delay circuit module-3, comparison circuit module-4, amplifier circuit module-5, gate drive circuit module-6, first delay unit-31, second delay unit-32, first comparison unit-41, second comparison unit-42, first amplifier unit-51, second amplifier unit-52, first drive unit-61, second drive unit-62. DETAILED DESCRIPTION

[0032] This specific embodiment is merely an explanation of the present application and is not a limitation of the present application. After reading this specification, those skilled in the art may make modifications to the present embodiment without any creative contribution as needed. However, as long as it is within the scope of the claims of the present application, it shall be protected by the patent law.

[0033] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0034] In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more, unless otherwise clearly specified.

[0036] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0037] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0038] The embodiments of the present application are further described in detail below in conjunction with the drawings in the specification.

[0039] like Figure 1 As shown, the driving circuit proposed in this application includes:

[0040] A main control chip 1, an isolation driver chip 2, a delay circuit module 3, a comparison circuit module 4, an amplifier circuit module 5, and a gate driver circuit module 6; wherein the delay circuit module 3 includes two delay units, namely a first delay unit 31 and a second delay unit 32; the comparison circuit module 4 includes two comparison units, namely a first comparison unit 41 and a second comparison unit 42; wherein the amplifier circuit module 5 includes two amplifier units, namely a first amplifier unit 51 and a second amplifier unit 52; and the gate driver circuit module 6 includes two drive units, namely a first drive unit 61 and a second drive unit 62.

[0041] The output end of the main control chip 1 is connected to the input end of the isolation driver chip 2, and is used to transmit a PWM signal to the isolation driver chip 2; the output end of the isolation driver chip 2 is respectively connected to the first delay unit 31 and the second delay unit 32 in the delay circuit module 3, and the isolation driver chip 2 changes the voltage amplitude of the PWM signal received from the main control chip 1 and converts it into a drive signal, and the isolation driver chip 2 further transmits the drive signal to the first delay unit 31 and the second delay unit 32, and the first delay unit 31 and the second delay unit 32 delay the drive signal, and change the rising edge rate of the input drive signal, so that the time for the drive signal to reach the same voltage value is different, and two different first delay signals and second delay signals are obtained. RCD delay circuits are used in both the first delay unit 31 and the second delay unit 32.

[0042] The output end of the delay circuit module 3 is connected to the input end of the comparison circuit module 4. Specifically, the output end of the first delay unit 31 is connected to the input end of the first comparison unit 41, and the output end of the second delay unit 32 is connected to the input end of the second comparison unit 42. The first delay unit 31 transmits the first delay signal to the first comparison unit 41, and the first comparison unit 41 compares the first delay signal with the reference voltage V ref The second delay unit 32 transmits the second delay signal to the second comparison unit 42, and the second comparison unit 42 compares the second delay signal with the reference voltage V ref A comparison is performed, and a second control current is output according to the comparison result. The introduction of the delay circuit module 3 allows the rising edge rate of the drive signal to be adjusted. This helps to optimize the switching process of the MOSFET, reduce switching losses, and improve system efficiency. By changing the time when the drive signal reaches the same voltage value, fine control of the MOSFET switching process can be achieved.

[0043] The output end of the comparison circuit module 4 is connected to the input end of the amplifier circuit module 5. Specifically, the output end of the first comparison unit 41 is connected to the input end of the first amplifier unit 51, and the output end of the second comparison unit 42 is connected to the input end of the second amplifier unit 52. The first comparison unit 41 transmits the first control current to the first amplifier unit 51, and the first amplifier unit 51 amplifies it. The amplification ratio can be set according to actual needs so that the amplified control current can drive the load. The second comparison unit 42 transmits the second control current to the second amplifier unit 52, and the second amplifier unit 52 amplifies it. The amplification ratio can be set according to actual needs so that the amplified control current can drive the load. The comparison circuit module 4 compares the delayed drive signal with the reference voltage and outputs the control current according to the comparison result. This design helps to ensure that the drive signal triggers the switching action of the MOSFET at the appropriate time, thereby enhancing the stability and reliability of the system.

[0044] The output end of the amplifier circuit module 5 is connected to the input end of the gate drive circuit module 6. Specifically, the output end of the first amplifier unit 51 is connected to the input end of the first drive unit 61, and the output end of the second amplifier unit 52 is connected to the input end of the second drive unit 62. The first amplifier unit 51 transmits the amplified first control current to the first drive unit 61, so that the first drive unit 61 can adjust the SiC-MOSFET; the second amplifier unit 52 transmits the amplified second control current to the second drive unit 62, so that the second drive unit 62 can adjust the IGBT-MOSFET. The amplifier circuit module 5 amplifies the control current so that it can drive the load, and the amplification ratio can be set according to actual needs to ensure that the amplified control current can fully meet the driving requirements of the MOSFET, thereby improving the driving capability and the overall performance of the system.

[0045] The driving circuit proposed in this application sets independent driving units for SiC-MOSFET and IGBT-MOSFET respectively. Each MOSFET has its specific electrical characteristics and working requirements, and the control can control SiC-MOSFET and IGBT-MOSFET more accurately. At the same time, the design of the driving circuit allows flexible configuration and adjustment according to different application scenarios and requirements. For example, parameters such as delay time and amplification ratio can be adjusted according to different load characteristics and working requirements. In addition, the design also has certain scalability, and more driving units and control modules can be easily integrated to meet more complex application requirements.

[0046] In some embodiments, Figure 2 and Figure 3As shown, the first delay unit 31 includes a diode D1, a diode D2, a resistor R1, a resistor R2 and a capacitor C1; the anode of the diode D1 is connected to the output end of the isolation driver chip 2, the cathode of the diode D1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded GND-HV; the cathode of the diode D2 is connected to the output end of the isolation driver chip 2, and is connected to the anode of the diode D1, the anode of the diode D2 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the capacitor C1 and the inverting input end of the first comparison unit 41, and the diode D2 and the resistor R2 are connected in parallel with the diode D1 and the resistor R1. Among them, the diode D1, the resistor R1 and the capacitor C1 form a filter circuit, which is used to limit the magnitude of the current, prevent the capacitor C1 from generating excessive transient current when charging or discharging, and smooth the output signal from the isolation driver chip 2 to remove high-frequency noise. The diode D1 allows the current flowing from the output end of the isolation driver chip 2 to the capacitor C1 and the resistor R1 to pass. At the same time, it prevents the current from flowing back from the capacitor C1 and the resistor R1 to the isolation driver chip 2, thereby protecting the driver chip from the impact of the reverse current.

[0047] In some embodiments, the second delay unit includes a diode D5, a resistor R5 and a capacitor C2. Wherein, the cathode of the diode D5 is connected to the output end of the isolation driver chip 2, and the anode of the diode D5 is connected to the positive phase input end of the second comparison unit 42; one end of the resistor R5 is connected to the output end of the isolation driver chip 2 and the cathode of the diode D5, and the other end of the resistor R5 is connected to the anode of the diode D5 and one end of the capacitor C2, and the other end of the capacitor C2 is grounded. Wherein, the resistor R5 limits the current flowing to the second comparison unit 42, preventing damage to the comparison unit due to excessive current. The resistor R5 and the capacitor C2 form an open filter circuit, and when the drive signal passes through the resistor R5, the capacitor C2 starts to charge, and this charging process causes the signal to be delayed before reaching the second comparison unit 42. The delay time can be adjusted by adjusting the resistance value of the resistor R5 and the capacity of the capacitor C2. The input voltage of the subsequent second comparison unit 42 rises slower than the input voltage of the first comparison unit 41 , and the high level signal at the output end of the second comparison unit 42 is output with a delay compared with the high level signal at the output end of the first comparison unit 41 .

[0048] In some embodiments, the first comparison unit 41 includes a comparator N1; the non-phase input terminal of the comparator N1 is connected to the reference voltage, the inverting input terminal of the comparator N1 is connected to the output terminal of the first delay unit 31, and the output terminal of the comparator N1 is connected to the input terminal of the first amplification unit 51 of the amplification circuit module 5. The comparator N1 compares the voltage value of the inverting input terminal with the reference voltage of the non-phase input terminal, and according to the comparison result, the comparator N1 will output a high level or low level signal at the output terminal. Among them, the reference voltage of the non-phase input terminal of the comparator N1 is determined according to the duty cycle of the PWM signal of the main control chip.

[0049] In some embodiments, the second comparison unit includes a comparator N2; the inverting input terminal of the comparator N2 is connected to the reference voltage, the non-inverting input terminal of the comparator N2 is connected to the output terminal of the second delay unit 31, and the output terminal of the comparator N2 is connected to the input terminal of the second amplification unit 52 in the amplification circuit module 5. The comparator N2 compares the voltage value of the inverting input terminal with the reference voltage of the non-inverting input terminal, and according to the comparison result, the comparator N2 will output a high level or low level signal at the output terminal. Among them, the reference voltage of the non-inverting input terminal of the comparator N1 is determined according to the duty cycle of the PWM signal of the main control chip.

[0050] In some embodiments, the first amplifying unit 51 includes: a transistor Q20, a transistor Q21, and the transistor Q20 and the transistor Q21 form a push-pull pair; the base of the transistor Q20 is connected to the output end of the first comparison unit, the collector of the transistor Q20 is connected to the positive electrode of the +18V power supply, and the emitter of the transistor Q20 is connected to the emitter of the transistor Q21 and the input end of the gate drive circuit module; the base of the transistor Q21 is connected to the output end of the second comparison unit, the emitter of the transistor Q21 is connected to the input end of the gate drive circuit module 6, and the collector of the transistor Q21 is connected to the negative electrode of the -4V power supply. Among them, the transistor Q20 is an NPN transistor, and the transistor Q21 is a PNP transistor. Current is alternately provided or absorbed between the transistor Q20 and the transistor Q21.

[0051] In some embodiments, the second amplifying unit 52 includes: a transistor Q22 and a transistor Q23, wherein the transistor Q22 and the transistor Q23 form a push-pull pair; wherein the base of the transistor Q22 and the base of the transistor Q23 are both connected to the output end of the second comparing unit, the collector of the transistor Q22 is connected to the positive electrode of the +18V power supply, the emitter of the transistor Q22 is connected to the emitter of the transistor Q23, the collector of the transistor Q23 is connected to the negative electrode of the -8V power supply, and the emitter of the transistor Q22 and the emitter of the transistor Q22 are connected to the input end of the gate driving circuit module 6. wherein the transistor Q22 is an NPN transistor, and the transistor Q23 is a PNP transistor. current is alternately provided or absorbed between the transistor Q22 and the transistor Q23.

[0052] In some embodiments, an isolation optocoupler U3 is further included between the main control chip 1 and the comparison circuit module 4; the input end of the isolation optocoupler U3 is connected to the output end of the main control chip 1, and the output end of the isolation optocoupler U3 is connected to the input end of the comparison circuit module 4. The isolation optocoupler U3 plays a role of electrical isolation between the main control chip 1 and the comparison circuit module 4. The duty cycle of the PWM1 signal output by the main control chip 1 to the comparison circuit module 4 is D. Through the isolation optocoupler U3, the reference voltage Vref output by the secondary side is D*18V.

[0053] In some embodiments, the first driving unit 61 includes a diode D3, a diode D4, a resistor R3 and a resistor R4; wherein the anode of the diode D3 is connected to the output end of the first amplifying unit 51, the cathode of the diode D3 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the SiC-MOSFET module in the Hys system; the anode of the diode D4 is connected to the output end of the first amplifying unit 51, the anode of the diode D4 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the SiC-MOSFET module in the Hys system. The SiC-MOSFET module includes MOSQ1, MOSQ4, MOSQ7, MOSQ10, MOSQ13, and MOSQ16.

[0054] In some embodiments, the second driving unit 62 includes a diode D7, a diode D8, a resistor R6 and a resistor R7; wherein the anode of the diode D7 is connected to the output end of the second amplifying unit 52, the cathode of the diode D7 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the IGBT-MOSFET module in the Hys system; the cathode of the diode D8 is connected to the output end of the second amplifying unit 52, the anode of the diode D8 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the IGBT-MOSFET module in the Hys system. The IGBT-MOSFET module includes MOSQ2, MOSQ3, MOSQ5, MOSQ6, MOSQ8, MOSQ9, MOSQ11, MOSQ12, MOSQ14, MOSQ15, MOSQ17, and MOSQ18.

[0055] When turned on, the diode D1, the resistor R1, and the capacitor C1 form a turn-on filter circuit. Compared with the turn-on filter circuit composed of the comparison resistor R5 and the capacitor C2, by adjusting the resistance value of the resistor R5 and the capacity of the capacitor C2, the input voltage of the second comparison unit rises slower than the input voltage of the first comparison unit, so the high-level signal of the second comparison unit will be delayed than the high-level signal of the first comparison unit. The output can make the SiC-MOSFET turn on first and the IGBT-MOSFET turn on later, realizing the soft turn-on of the IGBT-MOSFET and reducing the turn-on loss.

[0056] When shutting down, the diode D5 and the capacitor C2 form a shutdown filter circuit. Compared with the shutdown filter circuit composed of the diode D2, the resistor R2 and the capacitor C2, by adjusting the resistance of the resistor R2 and the capacity of the capacitor C2, the input voltage of the first comparison unit drops slower than that of the second comparison unit. Therefore, the low level output of the first comparison unit is delayed compared with the low level signal output by the second comparison unit, resulting in the SiC-MOSFET being shut down later and the IGBT-MOSFET being shut down first, thereby realizing the ZVS shutdown of the IGBT-MOSFET and reducing the shutdown loss.

[0057] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the system described in the present application is divided into different functional units or modules to complete all or part of the functions described above.

Claims

1. A driving circuit for a Hys hybrid parallel motor, characterized in that: The driving circuit comprises: Delay circuit module, comparison circuit module, amplifier circuit module, gate drive circuit module, main control chip, isolation drive chip; wherein the delay circuit module includes a first delay unit and a second delay unit, the comparison circuit module includes a first comparison unit and a second comparison unit, the amplifier circuit module includes a first amplifier unit and a second amplifier unit; the gate drive circuit module includes a first drive unit and a second drive unit; The main control chip is used to transmit PWM signals to the isolation drive chip; The isolation driving chip is used to convert the PWM signal into a driving signal and output it to the delay circuit module; The delay circuit module is used to delay the received driving signal through the first delay unit and the second delay unit, and transmit two different first delay signals and second delay signals to the comparison circuit module; The comparison circuit module is used to compare the received first delayed signal with the reference voltage through the first comparison unit, and output the first control current to the first amplification unit of the amplification circuit module; and is also used to compare the received second delayed signal with the reference voltage through the second comparison unit, and output the second control current to the second amplification unit of the amplification circuit module; The amplifying circuit module is used to amplify the first control current and the second control current through the first amplifying unit and the second amplifying unit respectively and then output them to the gate driving circuit module; The gate drive circuit module is used to adjust the SiC-MOSFET according to the amplified first control current through the first drive unit and to adjust the IGBT-MOSFET according to the amplified second control current through the second drive unit.

2. The driving circuit for the Hys hybrid parallel motor according to claim 1, characterized in that: The first delay unit includes a diode D1, a diode D2, a resistor R1, a resistor R2 and a capacitor C1; Among them, the anode of the diode D1 is connected to the output end of the isolation driving chip, the cathode of the diode D1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded; the cathode of the diode D2 is connected to the output end of the isolation driving chip and the anode of the diode D1, the anode of the diode D2 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to one end of the capacitor C1 and the inverting input end of the first comparison unit.

3. The driving circuit for the Hys hybrid parallel motor according to claim 2, characterized in that: The second delay unit includes a diode D5, a resistor R5 and a capacitor C2; Among them, the cathode of the diode D5 is connected to the output end of the isolation driving chip, and the anode of the diode D5 is connected to the non-inverting input end of the second comparison unit; one end of the resistor R5 is connected to the output end of the isolation driving chip and the cathode of the diode D5, and the other end of the resistor R5 is connected to the anode of the diode D5 and one end of the capacitor C2, and the other end of the capacitor C2 is grounded.

4. The driving circuit for the Hys hybrid parallel motor according to claim 1, characterized in that: The first comparison unit includes a comparator N1; the non-inverting input terminal of the comparator N1 is connected to the reference voltage, the inverting input terminal of the comparator N1 is connected to the output terminal of the first delay unit, and the output terminal of the comparator N1 is connected to the input terminal of the first amplification unit of the amplification circuit module.

5. The driving circuit for the Hys hybrid parallel motor according to claim 4, characterized in that: The second comparison unit includes a comparator N2; the inverting input terminal of the comparator N2 is connected to the reference voltage, the non-inverting input terminal of the comparator N2 is connected to the output terminal of the second delay unit, and the output terminal of the comparator N2 is connected to the input terminal of the second amplification unit in the amplification circuit module.

6. The driving circuit for the Hys hybrid parallel motor according to claim 1, characterized in that: The first amplifying unit includes: a transistor Q20 and a transistor Q21, wherein the transistor Q20 and the transistor Q21 form a push-pull pair; the base of the transistor Q20 is connected to the output end of the first comparing unit, the collector of the transistor Q20 is connected to the positive electrode of the +18V power supply, and the emitter of the transistor Q20 is connected to the emitter of the transistor Q21 and the input end of the gate driving circuit module; the base of the transistor Q21 is connected to the output end of the second comparing unit, the emitter of the transistor Q21 is connected to the input end of the gate driving circuit module, and the collector of the transistor Q21 is connected to the negative electrode of the -4V power supply.

7. The driving circuit for the Hys hybrid parallel motor according to claim 6, characterized in that: The transistor Q20 is an NPN transistor; the transistor Q21 is a PNP transistor.

8. The driving circuit for the Hys hybrid parallel motor according to claim 1, characterized in that: The second amplifying unit includes: a transistor Q22 and a transistor Q23, wherein the transistor Q22 and the transistor Q23 form a push-pull pair; wherein the base of the transistor Q22 and the base of the transistor Q23 are both connected to the output end of the second comparing unit, the collector of the transistor Q22 is connected to the positive electrode of the +18V power supply, the emitter of the transistor Q22 is connected to the emitter of the transistor Q23, the collector of the transistor Q23 is connected to the negative electrode of the -8V power supply, and the emitter of the transistor Q22 and the emitter of the transistor Q22 are connected to the input end of the gate drive circuit module.

9. The driving circuit for the Hys hybrid parallel motor according to claim 8, characterized in that: The transistor Q22 is an NPN transistor; the transistor Q23 is a PNP transistor.

10. The driving circuit for a Hys hybrid parallel motor according to claim 1, characterized in that: An isolation optocoupler is also included between the main control chip and the comparison circuit module; the input end of the isolation optocoupler is connected to the output end of the main control chip, and the output end of the isolation optocoupler is connected to the input end of the comparison circuit module.

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