A detection circuit

Abstract

The present invention discloses a detection circuit. The circuit includes: an interface detection module for connecting a node to be detected and transmitting a first electrical signal to the node to be detected; the node to be detected is used to receive the first electrical signal and generate a second electrical signal according to the connection status between the target device and the node to be detected; a voltage detection module is connected to the interface detection module, the voltage detection module is used to connect the node to be detected, and is turned on or off according to the second electrical signal of the node to be detected, and outputs a third electrical signal; an adjustment module, the adjustment module is connected to the interface detection module, and the output end of the adjustment module and the output end of the voltage detection module are connected to the output interface; the adjustment module is used to adjust the voltage signal of the output interface according to the first electrical signal and the third electrical signal. The technical solution provided by the embodiment of the present invention is convenient for determining the connection status between the node to be detected and the target device, realizing floating detection of the target device, and has a simple structure and is easy to design.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a detection circuit. Background Art

[0002] In circuit configurations, the reliability of soldering components is crucial to stable circuit operation. This is especially true for circuits with pull-down resistors, which require circuit operation to be adjusted accordingly. However, factors such as poor solderability between the pad and the pull-down resistor, incorrect printing parameters, and improper reflow temperature and heating rate can cause cold solder joints. Cold solder joints can cause the pull-down resistor pins to open, leaving them floating and disrupting proper circuit operation.

[0003] However, the existing method for detecting floating solder pins has the problems of complex circuit structure, high design difficulty and high design cost. Summary of the Invention

[0004] The present invention provides a detection circuit to solve the problems of complex structure and difficult design of the detection circuit.

[0005] According to one aspect of the present invention, there is provided a detection circuit, comprising:

[0006] An interface detection module is configured to connect to a node to be detected and transmit a first electrical signal to the node to be detected; the node to be detected is configured to receive the first electrical signal and generate a second electrical signal based on a connection status between a target device and the node to be detected;

[0007] a voltage detection module connected to the interface detection module, the voltage detection module being configured to connect to the node to be detected and to be turned on or off according to the second electrical signal of the node to be detected, thereby outputting a third electrical signal;

[0008] An adjustment module, wherein the adjustment module is connected to the interface detection module, and the output end of the adjustment module and the output end of the voltage detection module are connected to the output interface; the adjustment module is used to adjust the voltage signal of the output interface according to the first electrical signal and the third electrical signal; the voltage signal is used to determine the connection status between the node to be detected and the target device.

[0009] Optionally, the interface detection module includes: a first switch unit and a current input unit; the current input unit is connected to the first switch unit, and the first switch unit is connected to the node to be detected; the current input unit is used to input the first electrical signal to the node to be detected, and the first switch unit is used to be turned on or off in response to a trigger control signal, and to generate a second electrical signal based on the first electrical signal and according to the connection status between the target device and the node to be detected;

[0010] Preferably, the first switch unit includes:

[0011] a first transistor, configured to transmit the first electrical signal to the node to be detected;

[0012] a second transistor, wherein the control terminal of the second transistor is connected to the first terminal of the first transistor, the first terminal of the second transistor is connected to the power supply terminal, and the second terminal of the second transistor is connected to the node to be detected; the second transistor is used to generate the second electrical signal;

[0013] Preferably, the current input unit includes:

[0014] A current source is connected to the second end of the first transistor, and the current source is used to output the first electrical signal to the first transistor.

[0015] Optionally, the interface detection module further includes: a second switch unit and a first comparison unit; the first comparison unit is connected to the first switch unit, the first switch unit is connected to the second switch unit, and the second switch unit is further connected to the power supply terminal; the first comparison unit is configured to receive a trigger signal and an enable signal and generate a trigger control signal, the trigger control signal being configured to control the on / off of the first switch unit, and the second switch unit being configured to pass the first electrical signal when being on;

[0016] Preferably, the second switch unit includes:

[0017] a third transistor, wherein a first terminal of the third transistor is connected to the power supply terminal, a second terminal of the third transistor is connected to the first terminal of the first transistor, and a control terminal of the third transistor is connected to the control terminal of the second transistor;

[0018] a fourth transistor, wherein a first terminal of the fourth transistor is connected to the power supply terminal, and a second terminal of the fourth transistor is connected to the second terminal of the third transistor;

[0019] Preferably, the first comparison unit includes:

[0020] A first comparator, wherein the output terminal of the first comparator is connected to the control terminal of the first transistor, and the first comparator is used to output a trigger control signal, and the trigger control signal is used to control the conduction or shutdown of the first transistor.

[0021] Optionally, the voltage detection module includes: a third switch unit, the third switch unit being configured to be connected to the node to be detected, and being turned on or off according to the second electrical signal of the node to be detected, and outputting a third electrical signal;

[0022] Preferably, the third switch unit includes: a fifth transistor, a first end of the fifth transistor is connected to the power supply end, a second end of the fifth transistor is connected to the output interface, and a control end of the fifth transistor is connected to the node to be detected.

[0023] Optionally, the voltage detection module further includes: a fourth switch unit; the fourth switch unit is connected to the third switch unit, and the fourth switch unit is used to switch on the third switch unit;

[0024] Preferably, the fourth switch unit includes: a sixth transistor, a first end of the sixth transistor is connected to the second end of the fifth transistor, and a second end of the sixth transistor is connected to the output interface.

[0025] Optionally, the regulation module includes: a storage unit and a fifth switch unit; a first end of the storage unit is connected to the output interface, a second end of the storage unit is connected to a ground end, a first end of the fifth switch unit is connected to the power end, a second end of the fifth switch unit is connected to the first end of the storage unit, a control end of the fifth switch unit is connected to the first switch unit, and a fourth end of the fifth switch unit is connected to the ground end; the fifth switch unit is configured to be turned on or off according to the first electrical signal; and the storage unit is configured to adjust the voltage signal of the output interface according to the conduction state of the fifth switch unit and the third electrical signal.

[0026] Preferably, the storage unit includes: a first capacitor, a first end of the first capacitor is connected to the output interface, and a second end of the first capacitor is grounded;

[0027] Preferably, the fifth switch unit includes:

[0028] a seventh transistor, wherein a first terminal of the seventh transistor is connected to the power supply terminal, and a control terminal of the seventh transistor is connected to the first terminal of the first transistor;

[0029] an eighth transistor, wherein a first terminal of the eighth transistor is connected to the second terminal of the seventh transistor, and a second terminal of the eighth transistor is grounded;

[0030] a ninth transistor, wherein a first end of the ninth transistor is connected to the output interface, a control end of the ninth transistor is connected to the control end of the eighth transistor, and a second end of the ninth transistor is grounded.

[0031] Optionally, the regulating module further includes: a sixth switch unit; the sixth switch unit is connected to the fifth switch unit, the control end of the sixth switch unit is used to receive the enable signal, and the sixth switch unit is used to ground the output interface when turned on;

[0032] Preferably, the sixth switch unit includes: a tenth transistor, a first end of the tenth transistor is connected to the first end of the ninth transistor, and a second end of the tenth transistor is connected to the second end of the ninth transistor.

[0033] Optionally, the detection circuit further includes:

[0034] A state trigger module, wherein a first output end of the state trigger module is connected to the voltage detection module and the regulation module, and a second output end of the state trigger module is connected to the interface detection module.

[0035] Optionally, the status triggering module includes:

[0036] a first inverter, wherein an output end of the first inverter serves as a first output end of the state trigger module, the output end of the first inverter is connected to the control end of the sixth transistor, and the output end of the first inverter is also connected to the control end of the tenth transistor;

[0037] a second inverter, wherein the input end of the second inverter is connected to the output end of the first inverter, the output end of the second inverter serves as the second output end of the state trigger module, the output end of the second inverter is connected to the control end of the fourth transistor, and the output end of the second inverter is also connected to the first comparator.

[0038] Optionally, the detection circuit further includes:

[0039] A state judgment module connected to the output interface; the state judgment module is used to generate a connection state signal according to the voltage signal; the connection state signal includes a connection signal between the node to be detected and the target device, or a floating signal between the node to be detected and the target device;

[0040] Preferably, the state judgment module includes:

[0041] A Schmitt trigger, wherein a first input terminal of the Schmitt trigger is connected to the output interface;

[0042] a second NAND gate, wherein a first input terminal of the second NAND gate is connected to an output terminal of the Schmitt trigger;

[0043] a third NAND gate, wherein the output terminal of the third NAND gate is connected to the second input terminal of the second NAND gate, the output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate, and the second input terminal of the third NAND gate is connected to the output terminal of the second inverter;

[0044] A third inverter, wherein the input end of the third inverter is connected to the output end of the second NAND gate, and the output end of the third inverter serves as the output end of the state judgment module.

[0045] The technical solution provided by the embodiment of the present invention, by providing an interface detection module, a voltage detection module, and an adjustment module, can output a first electrical signal from the interface detection module, and generate different second electrical signals based on the connection relationship between the target device and the node to be detected, thereby controlling the on or off state of the voltage detection module. The adjustment module outputs different voltage signals from the output interface based on the on or off state of the detection module, thereby reflecting the connection relationship between the target device and the node to be detected. The detection circuit provided by the embodiment of the present invention realizes the determination of the connection status between the node to be detected and the target device, and has a simple structure, which makes the circuit design less difficult and the design cost low.

[0046] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 is a module diagram of a detection circuit provided according to an embodiment of the present invention;

[0049] Figure 2 is a circuit diagram of a detection circuit provided according to an embodiment of the present invention;

[0050] Figure 3 is a module diagram of another detection circuit provided according to an embodiment of the present invention;

[0051] Figure 4 is a circuit diagram of another detection circuit provided according to an embodiment of the present invention;

[0052] Figure 5 is a circuit diagram of another detection circuit provided according to an embodiment of the present invention;

[0053] Figure 6 is a waveform diagram showing a floating connection status between a node to be detected and a target device provided by an embodiment of the present invention;

[0054] Figure 7This is a waveform diagram showing a good connection state between a node to be detected and a target device provided by an embodiment of the present invention;

[0055] Figure 8 is a circuit diagram of another detection circuit provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0056] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0057] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0058] An embodiment of the present invention provides a detection circuit. Figure 1 This is a module diagram of a detection circuit provided by an embodiment of the present invention. Figure 1 The circuit includes: an interface detection module 1, a voltage detection module 2 and an adjustment module 3. The interface detection module 1 is used to connect to the node to be detected 4 and transmit a first electrical signal to the node to be detected 4; the node to be detected 4 is used to receive the first electrical signal and generate a second electrical signal according to the connection status between the target device 5 and the node to be detected 4. The voltage detection module 2 is connected to the interface detection module 1. The voltage detection module 2 is used to connect to the node to be detected 4 and output a third electrical signal according to whether the second electrical signal of the node to be detected 4 is turned on or off. The adjustment module 3 is connected to the interface detection module 1. The output end of the adjustment module 3 and the output end of the voltage detection module 2 are connected to the output interface; the adjustment module 3 is used to adjust the voltage signal of the output interface according to the first electrical signal and the third electrical signal; the voltage signal is used to determine the connection status between the node to be detected 4 and the target device 5.

[0059] The interface detection module 1 can generate a first electrical signal and input it into the node to be detected 4, thereby transmitting the first electrical signal to the node to be detected 4. For example, the first electrical signal can be a current signal. Depending on the connection relationship between the node to be detected 4 and the target device 5, different second electrical signals can be generated. For example, when the connection between the node to be detected 4 and the target device 5 is good, a loop is formed between the interface detection module 1 and the ground terminal, and the second electrical signal is a voltage signal.

[0060] The voltage detection module 2 receives the second electrical signal and turns on, and outputs a third electrical signal to the regulation module 3. The third electrical signal may be a current signal, and the voltage signal of the output interface is adjusted by the first and third electrical signals. For example, the third electrical signal can generate a voltage signal after being input into the regulation module 3.

[0061] The adjustment module 3 can also receive the first electrical signal and convert it into an electrical signal with a lower current level. The current of the lower current signal is less than the current of the third electrical signal. The current difference between the lower current signal and the third electrical signal can pull the voltage signal output by the output interface to a high-level signal. When the voltage signal output by the output interface is a high-level signal, it indicates that the connection between the node to be detected 4 and the target device 5 is in good condition. For example, the target device 5 can be an impedance device such as a pull-down resistor or a sliding rheostat.

[0062] When the connection between the node to be detected 4 and the target device 5 is not reliably established, the connection between the node to be detected 4 and the target device 5 is in a floating state. A loop cannot be formed between the interface detection module 1 and the ground terminal, and a high-level second electrical signal can be output. At this point, the voltage detection module 2 is not conducting, the adjustment module 3 is not operating, and the voltage signal of the output interface cannot be adjusted, directly outputting a low-level signal, indicating that the connection between the node to be detected 4 and the target device 5 is in a floating state.

[0063] The technical solution provided by the embodiment of the present invention, by providing an interface detection module 1, a voltage detection module 2, and an adjustment module 3, can output a first electrical signal from the interface detection module 1, and generate different second electrical signals based on the connection relationship between the target device 5 and the node to be detected 4, thereby controlling the on or off state of the voltage detection module 2. The adjustment module 3 outputs different voltage signals from the output interface based on the on or off state of the detection module 2, thereby reflecting the connection relationship between the target device 5 and the node to be detected 4. The detection circuit provided by the embodiment of the present invention realizes the determination of the connection status between the node to be detected and the target device, and has a simple structure, which makes the circuit design less difficult and low-cost.

[0064] Figure 2 A circuit diagram of a detection circuit provided by an embodiment of the present invention. Figure 2Based on the above embodiments, the interface detection module 1 optionally includes: a first switch unit 11 and a current input unit 12. The current input unit 12 is connected to the first switch unit 11, and the first switch unit 11 is connected to the node to be detected 4. The current input unit 12 is configured to input a first electrical signal to the node to be detected 4. The first switch unit 11 is configured to be turned on or off in response to a trigger control signal and to generate a second electrical signal based on the first electrical signal and the connection status between the target device 5 and the node to be detected 4.

[0065] Specifically, the first switch unit 11 is turned on or off by a trigger control signal. When the first switch unit 11 is off, the connection between the current input unit 12 and the node to be detected 4 is disconnected, and the detection circuit does not perform detection. When the first switch unit 11 is on, the first electrical signal output by the current input unit 12 can flow through the first switch unit 11 into the node to be detected 4, and generate a second electrical signal based on the connection state between the target device 5 and the node to be detected 4.

[0066] Optional, continue to refer to Figure 2 Based on the above embodiments, the first switch unit 11 includes a first transistor MP1 and a second transistor MP2. The first transistor MP1 is configured to transmit a first electrical signal to the node 4 to be detected. The control terminal of the second transistor MP2 is connected to the first terminal of the first transistor MP1, the first terminal of the second transistor MP2 is connected to the power supply terminal, and the second terminal of the second transistor MP2 is connected to the node 4 to be detected. The second transistor MP2 is configured to generate a second electrical signal. The current input unit 12 includes a current source, which is connected to the second terminal of the first transistor MP1 and configured to output the first electrical signal to the first transistor MP1.

[0067] When the first transistor MP1 is turned on, the first electrical signal output by the current source is input into the second transistor MP2 via the first transistor MP1. The second end of the second transistor MP2 outputs a second electrical signal based on the connection state between the target device 5 and the node to be detected 4, and inputs the second electrical signal into the voltage detection module 2. The voltage detection module 2 is turned on or off based on the second electrical signal. For example, when the connection state between the node to be detected 4 and the target device 5 is good, a loop is formed between the second end of the second transistor MP2 and the ground end, and the second transistor MP2 outputs a second electrical signal to control the voltage detection module 2 to be turned on. When the connection between the node to be detected 4 and the target device 5 is in a floating state, a loop cannot be formed between the second end of the second transistor MP2 and the ground end, and the second transistor MP2 outputs a second electrical signal to control the voltage detection module 2 to be turned off. Transistors are small in size and have a fast response speed. By configuring the first switch unit 11 to be connected in a manner that multiple transistors are connected, the first switch unit 11 has better performance and a smaller size.

[0068] Continue to refer Figure 2 Based on the above embodiments, optionally, the interface detection module 1 further includes: a second switch unit 13 and a first comparison unit 14; the first comparison unit 14 is connected to the first switch unit 11, the first switch unit 11 is connected to the second switch unit 13, and the second switch unit 13 is also connected to the power supply end; the first comparison unit 14 is used to receive the trigger signal and the enable signal and generate a trigger control signal, the trigger control signal is used to control the on and off of the first switch unit 11, and the second switch unit 13 is used to pass the first electrical signal when it is turned on.

[0069] Exemplarily, the first comparison unit 14 may be a NAND gate. The first comparison unit 14 generates different trigger control signals to control the on and off of the first switch unit 11 according to the input reception trigger signal and the enable signal.

[0070] Optional, continue to refer to Figure 2 Based on the above embodiments, the second switching unit 13 includes a third transistor MP3 and a fourth transistor MP4. A first end of the third transistor MP3 is connected to the power supply terminal, a second end of the third transistor MP3 is connected to the first end of the first transistor MP1, and a control end of the third transistor MP3 is connected to the control end of the second transistor MP2. A first end of the fourth transistor MP4 is connected to the power supply terminal, and a second end of the fourth transistor MP4 is connected to the second end of the third transistor MP3. The first comparing unit 14 includes a first comparator nand1, an output end of the first comparator nand1 is connected to the control end of the first transistor MP1, and the first comparator nand1 is configured to output a trigger control signal, which is used to control the on / off state of the first transistor MP1.

[0071] By providing the fourth transistor MP4, the third transistor MP3 can be short-circuited when the fourth transistor MP4 is turned on, ensuring that no current flows through the third transistor MP3. When the detection circuit is operating normally, the fourth transistor MP4 is turned off, and the current from the current source can be input into the third transistor MP3. The first comparator nand1 can control the conduction or shutdown of the first transistor MP1 based on different input signals. For example, when the trigger signal and the enable signal are both high, the first transistor MP1 is turned on.

[0072] Continue to refer Figure 2 On the basis of the above embodiments, optionally, the voltage detection module 2 includes: a third switch unit 21; the third switch unit 21 is used to connect to the node to be detected 4, and is turned on or off according to the second electrical signal of the node to be detected 4, and outputs a third electrical signal.

[0073] Specifically, the third switch unit 21 can be controlled to be on or off based on its own voltage difference. For example, the detection node 4 and the power supply terminal are both connected to the third switch unit 21. When the voltage difference between the detection node 4 and the power supply terminal reaches the turn-on voltage of the third switch unit 21, the third switch unit 21 is turned on.

[0074] Optional, continue to refer to Figure 2 Based on the above embodiments, the third switch unit 21 includes: a fifth transistor MP5, a first end of the fifth transistor MP5 is connected to the power supply end, a second end of the fifth transistor MP5 is connected to the output interface, and a control end of the fifth transistor MP5 is connected to the node 4 to be detected.

[0075] When the first electrical signal flows through the target device 5, a voltage is generated across the target device 5. The control terminal of the fifth transistor MP5 can receive the voltage signal formed by the first electrical signal flowing through the target device 5 and compare it with the voltage of the power supply terminal connected to the first terminal. When the voltage difference between the two is greater than the turn-on voltage, the fifth transistor MP5 is turned on. Exemplarily, the turn-on voltage can be 0.7V. When the fifth transistor MP5 is turned on, the fifth transistor MP5 outputs a third electrical signal from the second terminal and generates a voltage signal in the adjustment module 3 based on the third electrical signal. The adjustment module 3 can also receive the first electrical signal and convert it into an electrical signal with a lower current level. The current of the lower electrical signal is less than the current of the third electrical signal. The difference between the current of the lower electrical signal and the current of the third electrical signal can pull the voltage signal output by the interface to a high level signal. When the voltage signal output by the output interface is a high level signal, it indicates that the connection between the node to be detected 4 and the target device 5 is in good condition.

[0076] Continue to refer Figure 2 On the basis of the above embodiments, optionally, the voltage detection module 2 further includes: a fourth switch unit 22 ; the fourth switch unit 22 is connected to the third switch unit 21 , and the fourth switch unit 22 is used to connect the third switch unit 21 .

[0077] Among them, by providing the fourth switch unit 22 between the output interface and the third switch unit 21, the connection between the third switch unit 21 and the output interface can be controlled by the fourth switch unit 22, thereby improving the safety of the circuit.

[0078] Optional, continue to refer to Figure 2 Based on the above embodiments, the fourth switch unit 22 includes a sixth transistor MP6 , a first end of the sixth transistor MP6 is connected to the second end of the fifth transistor MP5 , and a second end of the sixth transistor MP6 is connected to the output interface.

[0079] The sixth transistor MP6 is disposed between the fifth transistor MP5 and the output interface. When the sixth transistor MP6 is turned on, the third electrical signal is input into the regulation module 3 to generate a voltage signal, and the voltage signal is regulated by the regulation module 3. By providing the sixth transistor MP6, the third electrical signal is input only when the sixth transistor MP6 is turned on, thereby increasing the controllability of the circuit and improving safety.

[0080] Continue to refer Figure 2 On the basis of the above embodiments, optionally, the adjustment module 3 includes: a storage unit 31 and a fifth switch unit 32; a first end of the storage unit 31 is connected to the output interface, a second end of the storage unit 31 is connected to the ground end, a first end of the fifth switch unit 32 is connected to the power end, a second end of the fifth switch unit 32 is connected to the first end of the storage unit 31, a control end of the fifth switch unit 32 is connected to the first switch unit 11, and a fourth end of the fifth switch unit 32 is connected to the ground end; the fifth switch unit 32 is used to be turned on or off according to the first electrical signal; the storage unit 31 is used to adjust the voltage signal of the output interface according to the conduction state of the fifth switch unit and the third electrical signal.

[0081] The storage unit 31 may be used to generate a voltage signal and output it through the output interface. The fifth switch unit 32 may adjust the voltage signal and reflect the connection status between the node to be detected 4 and the target device 5 through the voltage signal.

[0082] Optional, continue to refer to Figure 2 Based on the above embodiments, the storage unit 31 includes: a first capacitor C1, a first end of the first capacitor C1 being connected to the output interface, and a second end of the first capacitor C2 being grounded; a fifth switch unit 32 including: a seventh transistor MP7, an eighth transistor MN8, and a ninth transistor MN9. A first end of the seventh transistor MP7 is connected to the power supply terminal, and a control end of the seventh transistor MP7 is connected to the first end of the first transistor MP1; a first end of the eighth transistor MN8 is connected to the second end of the seventh transistor MP7, and a second end of the eighth transistor MN8 is grounded; a first end of the ninth transistor MN9 is connected to the output interface, a control end of the ninth transistor MN9 is connected to the control end of the eighth transistor MN8, and a second end of the ninth transistor MN9 is grounded.

[0083] When the connection between the node to be detected 4 and the target device 5 is in good condition, the fifth transistor MP5 is turned on. The third electrical signal output by the fifth transistor MP5 can act on the first capacitor C1, generating a level signal on the first capacitor C1. The current generated by the seventh transistor MP7 is input into the eighth transistor MN8 and the ninth transistor MN9. The eighth transistor MN8 and the ninth transistor MN9 can regulate the current at the connection point between the ninth transistor MN9 and the first capacitor C1, generating a current signal at the first end of the ninth transistor MN9. The current of this current signal is less than the current generated by the second end of the seventh transistor MP7. Because the third transistor MP3 serves as the input transistor of the current source, the second transistor MP2 and the seventh transistor MP7 can be used to mirror the current of the third transistor MP3. Therefore, the second transistor MP2 and the seventh transistor MP7 can output the same current. In other words, the current value of the current signal at the first end of the ninth transistor MN9 is less than the current value output by the fifth transistor MP5. Because the first end of the ninth transistor MN9 and the second end of the sixth transistor MP6 are both connected to the first capacitor C1, the current difference generated by the ninth transistor MN9 and the fifth transistor MP5 can pull up the level signal generated by the first capacitor C1, so that the output interface outputs a high level, which can be used to indicate that the connection status between the node to be detected 4 and the target device 5 is good.

[0084] Continue to refer Figure 2 Based on the above embodiments, the regulating module 3 may optionally further include a sixth switch unit 33. The sixth switch unit 33 is connected to the fifth switch unit 32. The control terminal of the sixth switch unit 33 is used to receive an enable signal. The sixth switch unit 33 is used to ground the output interface when it is turned on.

[0085] The sixth switch unit 33 can serve as the ground terminal of the output interface when turned on, so as to prevent the occurrence of circuit leakage and ensure the safe operation of the detection circuit.

[0086] Optional, continue to refer to Figure 2 Based on the above embodiments, the sixth switch unit 33 includes a tenth transistor, a first end of the tenth transistor MN10 is connected to the first end of the ninth transistor MN9, and a second end of the tenth transistor MN10 is connected to the second end of the ninth transistor MN9.

[0087] For example, when the detection circuit has no start-up signal, the tenth transistor MN10 may connect the output interface to the ground terminal to prevent leakage of the detection circuit and ensure the safety of the detection circuit.

[0088] Figure 3 This is a module diagram of another detection circuit provided by an embodiment of the present invention. Figure 3Based on the above embodiments, optionally, the detection circuit further includes: a state trigger module 6, a first output end of the state trigger module 6 is connected to the voltage detection module 2 and the regulation module 3, and a second output end of the state trigger module 6 is connected to the interface detection module 1.

[0089] The state trigger module 6 is used to output an enable signal, which can control the opening and closing of the interface detection module 1 , the voltage detection module 2 and the regulation module 3 .

[0090] Figure 4 This is a circuit diagram of another detection circuit provided by an embodiment of the present invention. Figure 4 Based on the above embodiments, optionally, the state trigger module 6 includes: a first inverter Inv1 and a second inverter Inv2. The output terminal EnN of the first inverter Inv1 serves as the first output terminal of the state trigger module 6. The output terminal of the first inverter Inv1 is connected to the control terminal of the sixth transistor MP6. The output terminal of the first inverter Inv1 is also connected to the control terminal of the tenth transistor MN10. The input terminal of the second inverter Inv2 is connected to the output terminal of the first inverter Inv1. The output terminal EnA of the second inverter Inv2 serves as the second output terminal of the state trigger module 6. The output terminal of the second inverter Inv2 is connected to the control terminal of the fourth transistor MP4. The output terminal EnA of the second inverter Inv2 is also connected to the first comparator nand1.

[0091] The state trigger module 6 is used to control the startup of the detection circuit. When the state trigger module 6 receives an enable signal En, illustratively, the enable signal En can be a high-level signal, such as 1. The output terminal EnN of the first inverter Inv1 inverts the enable signal En from 1 to 0 and inputs it to the control terminals of the sixth transistor MP6 and the tenth transistor MN10. The sixth transistor MP6 is a P-type transistor, and the tenth transistor MN10 is an N-type transistor. The sixth transistor MP6 is turned on by receiving this control signal, and the tenth transistor MN10 is turned off by receiving this control signal. The output terminal EnA of the second inverter Inv2 inverts the 0 outputted by the output terminal EnN of the first inverter Inv1 to 1 and inputs it to the fourth transistor MP4 and the first comparator nand1. The fourth transistor MP4 is turned off by receiving this enable signal. The input terminal of the first comparator nand1 is also connected to the output terminal of the detection circuit for receiving the trigger signal outputted by the detection circuit. When the trigger signal outputted by the detection circuit is high, the first transistor MP1 is turned on.

[0092] Figure 5 A circuit diagram of another detection circuit provided by an embodiment of the present invention. Figure 5On the basis of the above embodiments, optionally, the detection circuit further includes: a state judgment module 7, the state judgment module 7 is connected to the output interface; the state judgment module 7 is used to generate a connection state signal according to the voltage signal; the connection state signal includes a connection signal between the node to be detected 4 and the target device 5, or a floating signal between the node to be detected 4 and the target device 5.

[0093] The state determination module 7 is configured to receive the voltage signal outputted by the output interface and convert it into a trigger signal. The trigger signal can be used to reflect the connection state between the node to be detected 4 and the target device 5. For example, the trigger signal can be a connection state signal.

[0094] Continue to refer Figure 5 Based on the above embodiments, optionally, the state judgment module 7 includes: a Schmitt trigger smit1, a second NAND gate nand2, a third NAND gate nand3, and a third inverter Inv3, wherein a first input end of the Schmitt trigger smit1 is connected to the output interface; a first input end of the second NAND gate nand2 is connected to the output end of the Schmitt trigger smit1; an output end of the third NAND gate nand3 is connected to the second input end of the second NAND gate nand2, an output end of the second NAND gate nand2 is connected to a first input end of the third NAND gate nand3, a second input end of the third NAND gate nand3 is connected to the output end EnA of the second inverter Inv2; an input end of the third inverter Inv3 is connected to the output end of the second NAND gate nand2, and an output end Flag of the third inverter Inv3 serves as an output end of the state judgment module 7.

[0095] Among them, the Schmitt trigger smit1 can invert the output signal of the output interface and input the output signal into the second NAND gate nand2. The second NAND gate nand2 and the third NAND gate nand3 can be combined to form a latch to prevent external signal interference and improve signal accuracy. The third inverter Inv3 then inverts the output signal and outputs it from the output terminal Flag of the third inverter Inv3. The output signal of the third inverter Inv3 can be used to reflect the connection status signal between the detection node 4 and the target device 5. For example, when the connection status signal is high, it is a floating signal between the node to be detected 4 and the target device 5, indicating that the node to be detected 4 and the target device 5 are not reliably connected. When the connection status signal is low, it is a connection signal between the node to be detected 4 and the target device 5, indicating that the node to be detected 4 and the target device 5 are reliably connected.

[0096] Figure 6 This is a waveform diagram showing the floating connection status between a node to be detected and a target device provided by an embodiment of the present invention. Figure 6Based on the above embodiments, optionally, when the enable signal En input to the state trigger module 6 is at a low level, the detection circuit is not in operation, and the detection circuit outputs a high-level signal. When the enable signal En input to the state trigger module 6 is at a high level, the first electrical signal flows, but because the connection between the detection node 4 and the target device 5 is in a floating state, the fifth transistor MP5 is not conductive, and the output interface is grounded through the ninth transistor MN9, thereby outputting a low-level signal, indicating that the connection between the detection node 4 and the target device 5 is in a floating state.

[0097] Figure 7 This is a waveform diagram showing that the connection between the node to be detected and the target device is in good condition. Figure 7 Based on the above embodiments, optionally, when the enable signal En input by the state trigger module 6 inverts from a low level to a high level, the first electrical signal flows, turning on the fifth transistor MP5. The third electrical signal continuously inputs current into the first capacitor C1, causing the output interface voltage signal to continuously rise. The adjustment module 3 raises the voltage signal output by the output interface to a high level signal. When the voltage signal output by the output interface is a high level signal, it indicates that the connection between the detection node 4 and the target device 5 is in good condition. The low-level signal output by the detection circuit is input to the first NAND gate nand1, which controls the fifth transistor MP5 to turn off, allowing the detection circuit to automatically shut down after completing the detection, thereby reducing circuit loss.

[0098] Figure 8 A circuit diagram of another detection circuit provided by an embodiment of the present invention. Figure 8 Based on the above embodiments, the target device 5 may optionally be a variable resistor 51. The voltage detection module 2 further includes an eleventh transistor MP11. By configuring the variable resistor 51 and the eleventh transistor MP11, the resistance of the variable resistor 51 can be adjusted to cause the eleventh transistor MP11 to generate different detection currents and to generate different voltages. When this voltage ensures that the fifth transistor MP5 is conductive, the detection circuit can perform detection. This configuration ensures that the detection circuit can complete detection when connected to target devices 5 with different resistance values, thereby improving the applicability of the present invention.

[0099] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0100] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A detection circuit, characterized in that: include: An interface detection module, configured to connect to a node to be detected and transmit a first electrical signal to the node to be detected; The node to be detected is used to receive the first electrical signal and generate a second electrical signal according to a connection state between the target device and the node to be detected; a voltage detection module connected to the interface detection module, the voltage detection module being configured to connect to the node to be detected and to be turned on or off according to the second electrical signal of the node to be detected, thereby outputting a third electrical signal; an adjustment module, the adjustment module being connected to the interface detection module, the output end of the adjustment module and the output end of the voltage detection module being connected to the output interface; the adjustment module being configured to adjust the voltage signal of the output interface to a high-level signal or a low-level signal based on the first electrical signal and the third electrical signal; the voltage signal being configured to determine the connection status between the node to be detected and the target device; When the connection state between the detection node and the target device is good, the third electrical signal inputs current to the regulating module, and the output interface outputs a high-level signal according to the third electrical signal and the first electrical signal; When the connection state between the detection node and the target device is floating, the voltage detection module is turned off according to the second electrical signal of the node to be detected and outputs a third electrical signal; The regulating module causes the output interface to output a low-level signal according to the first electrical signal and the third electrical signal; The regulating module includes: a storage unit and a fifth switch unit; The storage unit includes: a first capacitor, a first end of the first capacitor is connected to the output interface, and a second end of the first capacitor is grounded; The fifth switch unit includes: a seventh transistor, wherein a first end of the seventh transistor is connected to the power supply end, a control end of the seventh transistor is connected to the interface detection module, and the seventh transistor outputs an electrical signal that is the same as the first electrical signal; an eighth transistor, a first terminal of the eighth transistor being connected to the second terminal of the seventh transistor, and a second terminal of the eighth transistor being grounded; a ninth transistor, wherein a first end of the ninth transistor is connected to the output interface, a control end of the ninth transistor is connected to the control end of the eighth transistor, and a second end of the ninth transistor is grounded.

2. The detection circuit according to claim 1, characterized in that The interface detection module includes: a first switch unit and a current input unit; the current input unit is connected to the first switch unit, and the first switch unit is connected to the node to be detected; the current input unit is used to input the first electrical signal to the node to be detected, and the first switch unit is used to be turned on or off in response to a trigger control signal, and based on the first electrical signal, generates a second electrical signal according to the connection status between the target device and the node to be detected; The interface detection module further includes: a second switch unit and a first comparison unit; the first comparison unit is connected to the first switch unit, the first switch unit is connected to the second switch unit, and the second switch unit is further connected to the power supply terminal; the first comparison unit is configured to receive a trigger signal and an enable signal and generate a trigger control signal, the trigger control signal being configured to control the on / off of the first switch unit, and the second switch unit being configured to pass the first electrical signal when being on; The first switch unit includes: a first transistor, configured to transmit the first electrical signal to the node to be detected; a second transistor, wherein the control terminal of the second transistor is connected to the first terminal of the first transistor, the first terminal of the second transistor is connected to the power supply terminal, and the second terminal of the second transistor is connected to the node to be detected; the second transistor is used to generate the second electrical signal; The current input unit includes: a current source connected to the second end of the first transistor, the current source being configured to output the first electrical signal to the first transistor; The second switch unit includes: a third transistor, wherein a first end of the third transistor is connected to the power supply end, a second end of the third transistor is connected to the first end of the first transistor, a control end of the third transistor is connected to the control end of the second transistor, and the control end of the third transistor is also connected to the control end of the seventh transistor.

3. The detection circuit according to claim 2, characterized in that: The second switch unit further includes: a fourth transistor, wherein a first terminal of the fourth transistor is connected to the power supply terminal, and a second terminal of the fourth transistor is connected to the second terminal of the third transistor; The first comparing unit includes: A first comparator, wherein the output terminal of the first comparator is connected to the control terminal of the first transistor, and the first comparator is used to output a trigger control signal, and the trigger control signal is used to control the conduction or shutdown of the first transistor.

4. The detection circuit according to claim 3, characterized in that: The voltage detection module includes: a third switch unit, the third switch unit is used to connect to the node to be detected, and to be turned on or off according to the second electrical signal of the node to be detected, and output a third electrical signal; The third switch unit includes: a fifth transistor, a first end of the fifth transistor is connected to the power supply end, a second end of the fifth transistor is connected to the output interface, and a control end of the fifth transistor is connected to the node to be detected.

5. The detection circuit according to claim 4, characterized in that: The voltage detection module further includes: a fourth switch unit; the fourth switch unit is connected to the third switch unit, and the fourth switch unit is used to turn on the third switch unit; The fourth switch unit includes: a sixth transistor, a first end of the sixth transistor is connected to the second end of the fifth transistor, and a second end of the sixth transistor is connected to the output interface.

6. The detection circuit according to claim 5, characterized in that: The regulating module further includes: a sixth switch unit; the sixth switch unit is connected to the fifth switch unit, the control end of the sixth switch unit is used to receive the enable signal, and the sixth switch unit is used to ground the output interface when it is turned on; The sixth switch unit includes a tenth transistor, a first end of the tenth transistor is connected to the first end of the ninth transistor, and a second end of the tenth transistor is connected to the second end of the ninth transistor.

7. The detection circuit according to claim 6, characterized in that: Also includes: A state trigger module, wherein a first output end of the state trigger module is connected to the voltage detection module and the regulation module, and a second output end of the state trigger module is connected to the interface detection module.

8. The detection circuit according to claim 7, characterized in that: The state trigger module includes: a first inverter, wherein an output end of the first inverter serves as a first output end of the state trigger module, the output end of the first inverter is connected to the control end of the sixth transistor, and the output end of the first inverter is also connected to the control end of the tenth transistor; a second inverter, wherein the input end of the second inverter is connected to the output end of the first inverter, the output end of the second inverter serves as the second output end of the state trigger module, the output end of the second inverter is connected to the control end of the fourth transistor, and the output end of the second inverter is also connected to the first comparator.

9. The detection circuit according to claim 8, characterized in that: Also includes: A status judgment module, the status judgment module is connected to the output interface; The state judgment module is used to generate a connection state signal according to the voltage signal; the connection state signal includes a connection signal between the node to be detected and the target device, or a floating signal between the node to be detected and the target device; The state judgment module includes: A Schmitt trigger, wherein a first input terminal of the Schmitt trigger is connected to the output interface; a second NAND gate, wherein a first input terminal of the second NAND gate is connected to an output terminal of the Schmitt trigger; a third NAND gate, wherein the output terminal of the third NAND gate is connected to the second input terminal of the second NAND gate, the output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate, and the second input terminal of the third NAND gate is connected to the output terminal of the second inverter; A third inverter, wherein the input end of the third inverter is connected to the output end of the second NAND gate, and the output end of the third inverter serves as the output end of the state judgment module.

Images