A NAND Flash Error Analysis System for High-Speed ​​Flexibility Testing

Abstract

The present invention provides a NAND Flash error analysis system for high-speed flexibility testing. First, a host computer module sends a test instruction to a drive control module, and the test instruction causes the drive control module to start testing the flash memory chip. After receiving the test instruction, the drive control module tests the flash memory chip according to the test instruction and the test sequence, and the drive control module generates test data according to the test situation, and the drive control module sends the generated test data to the host computer module. On this basis, the host computer module receives the test data and parses the received test data to obtain the parsed result, i.e., the test result. The host computer module is provided with a real-time recording mechanism, and the host computer module summarizes the test results to form a traceable test report. According to the test report, the error situation of the flash memory chip can be analyzed.

Description

Technical Field

[0001] The present invention relates to the field of bit error analysis, and in particular to a NAND Flash bit error analysis system for high-speed flexibility testing. Background Art

[0002] At present, in the existing technology, as the demand for data storage in electronic devices continues to grow, NAND Flash, as a key non-volatile storage technology, has become the focus of research on its performance and reliability. NAND Flash memory has been widely used in portable devices, embedded systems, solid-state drives and other fields due to its high storage density, cost-effectiveness and the ability to retain data without power.

[0003] However, the existing NAND Flash testing methods have several limitations. First, traditional testing equipment often relies on lower-speed interfaces and cannot fully utilize NAND Flash, especially the high-speed performance of the NV-DDR3 mode. Second, most test processes only support single-station testing, which is difficult to meet the requirements of high efficiency in large-scale production environments.

[0004] In addition, existing test processes generally lack the ability to perform comprehensive functional tests on NAND Flash, such as reading UID, detecting factory bad blocks, and detecting errors during multi-plane erasing and programming. Moreover, existing technologies also have deficiencies in bad block management, making it difficult to effectively distinguish and classify factory bad blocks and original bad blocks. Furthermore, the storage unit of NAND Flash is composed of floating gate MOSFETs, and data is stored on the floating gate. The data is represented by 0 or 1 by changing the amount of charge on the floating gate. Multiple erase operations may cause damage to NAND Flash, and existing technologies have failed to effectively avoid this problem.

[0005] In terms of recording and managing test information, existing technologies usually lack a mechanism for real-time recording and document management, which makes it difficult to trace and analyze test data, affecting the convenience of subsequent data review. Summary of the invention

[0006] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0007] To this end, a first aspect of the present invention provides a NAND Flash error analysis system for high-speed flexibility testing.

[0008] In view of this, the first aspect of the present invention provides a NAND Flash error analysis system for high-speed flexibility testing, including: a host computer module sends a test instruction to a drive control module; based on the test instruction, the drive control module tests the flash memory chip and generates test data, and the drive control module sends the test data to the host computer module; the host computer module receives the test data, parses and processes the test data, and obtains the test result; based on the test result, the error situation of the flash memory chip is analyzed.

[0009] In addition, the NAND Flash error analysis system for high-speed flexibility testing in the above technical solution provided by the present invention may also have the following additional technical features:

[0010] In some technical solutions of the present invention, optionally, before the host computer module sends a test instruction to the drive module, the process includes: the host computer module establishes a network connection with the drive control module; and the host computer module performs an initialization operation to obtain test parameters.

[0011] In some technical solutions of the present invention, optionally, the test parameters include: an offset, a test quantity and a programming code length.

[0012] In some technical solutions of the present invention, optionally, based on the test instructions, the drive control module tests the flash memory module of the chip to generate test data, and the drive control module sends the test data to the host computer module, including: based on the test parameters, determining the test address of the flash memory chip; the drive control module performs a bad block test on the test address, obtains test data, and stores the test data in a first queue; based on the first queue, obtains the number of test data; when the number of test data reaches a preset number, the drive control module sends the test data in the first queue to the host computer module.

[0013] In some technical solutions of the present invention, optionally, the host computer module receives test data, parses and processes the test data, and obtains test results, including: the host computer module is provided with a timeout detection mechanism for detecting whether the test data from the drive control module is received within a preset time threshold; if the host computer module does not receive data within the preset time threshold, the host computer module issues a prompt, parses and processes the test data, and obtains the test results.

[0014] In some technical schemes of the present invention, optionally, the drive control module performs a bad block test on the test address to obtain test data, including: based on the block address in the test address, the drive control module executes a first erase instruction to the flash memory chip; reads a first erase state corresponding to the block address, and based on the first erase state and an erase reference value, performs an error check on the flash memory chip to obtain a first check result; based on the first check result, determines whether there is a bad block in the flash memory chip; the drive control module performs a first preprocessing on the flash memory chip to obtain test data.

[0015] In some technical schemes of the present invention, optionally, the drive control module performs a first preprocessing on the flash memory chip to obtain test data, including: based on the page address in the test address, reading the programming code at the page address; based on the page address and the programming code, performing an error check on the flash memory chip to obtain a second check result; based on the second check result, determining whether there are bad blocks in the flash memory chip; the drive control module performs a third preprocessing on the flash memory chip to obtain test data.

[0016] In some technical schemes of the present invention, optionally, the drive control module performs a third preprocessing on the flash memory chip to obtain test data, including: based on the block address, the drive control module performs a second erase instruction on the flash memory chip; reads the second erase state corresponding to the block address, and based on the second erase state and the erase reference value, performs an error check on the flash memory chip to obtain a third check result; based on the third check result, determines whether there are bad blocks in the flash memory chip; the drive control module performs a fourth preprocessing on the flash memory chip to obtain test data.

[0017] In some technical solutions of the present invention, optionally, the drive control module performs a fourth preprocessing on the flash memory chip to obtain test data, including: the drive control module reads the status register information of the flash memory chip; based on the status register information, performs complex verification on the status of existing bad blocks; and summarizes the test records to obtain test data.

[0018] The beneficial effects of the present invention are as follows:

[0019] 1. Multi-station parallel test architecture: An innovative parallel test architecture is implemented, which can independently and synchronously test multiple NAND Flash chips at the same time to improve the parallelism of the test and thus improve the overall test efficiency.

[0020] 2. Comprehensive test process: A comprehensive test process has been developed, covering key test points such as UID reading, factory bad block detection, multi-plane erase and programming cycle error detection. In addition, it also includes real-time reading of the status register status to ensure a thorough inspection of the various functions of the NAND Flash memory.

[0021] 3. Error code analysis and bad block management: This invention integrates deep error code analysis and bad block classification technology, which can accurately identify and distinguish factory bad blocks and original bad blocks. This function provides an important basis for chip quality management and reliability assessment.

[0022] 4. Flexibility and controllable operation: This system allows users to select individual test items according to specific needs, and provides a specified number of controllable operations based on bit offset and quantity. This flexibility is difficult to achieve in the prior art.

[0023] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0025] Figure 1 This is one of the flow charts of a NAND Flash error analysis system for high-speed flexibility testing according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0027] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0028] Refer to the following Figure 1 A NAND Flash error analysis system for high-speed flexibility testing according to some embodiments of the present invention is described.

[0029] like Figure 1 As shown, the first aspect of the present invention provides a NAND Flash error analysis system for high-speed flexibility testing, comprising:

[0030] Step 102, the host computer module sends a test instruction to the drive control module;

[0031] Step 104, based on the test instruction and the test sequence, the drive control module tests the flash memory chip to generate test data, and the drive control module sends the test data to the host computer module;

[0032] Step 106, the host computer module receives the test data, analyzes and processes the test data, and obtains the test results;

[0033] Step 108: Analyze the bit error situation of the flash memory chip based on the test results.

[0034] The present invention provides a NAND Flash error analysis system for high-speed flexibility testing. First, a host computer module sends a test instruction to a drive control module, and the test instruction enables the drive control module to start testing of a flash memory chip.

[0035] After receiving the test instruction, the drive control module tests the flash memory chip according to the test instruction and the test sequence, and generates test data according to the test situation, and sends the generated test data to the host computer module.

[0036] On this basis, the host computer module receives the test data and parses the received test data to obtain the parsed result, i.e. the test result. The host computer module is equipped with a real-time recording mechanism, which summarizes the test results to form a traceable test report. Traceability means that the specific location of the bad block in the flash memory chip and various test information such as UID can be found according to the test report. According to the test report, the error condition of the flash memory chip can be analyzed.

[0037] By testing the flash memory chip, we ensure that all functions of the NAND Flash memory are thoroughly inspected, which helps to discover and solve potential problems in advance and improve the overall quality of the product.

[0038] Specifically, the present invention can perform independent and synchronous testing on multiple NAND Flash chips at the same time to improve the parallelism of the testing, thereby improving the overall testing efficiency.

[0039] Specifically, the drive control module is composed of an FPGA and a socket chip test seat. It should be understood that a socket chip test seat, also known as an IC chip test seat or test socket, is a key tool used to test integrated circuit (IC) chips during the semiconductor manufacturing process. FPGA (Field-Programmable Gate Array), a field programmable logic gate array, is a programmable logic device that allows users to configure and program the chip according to specific needs after manufacturing.

[0040] Specifically, the test result includes an analysis of the bit error position of the flash memory chip in the test data, including the block position and page position of the bit error.

[0041] It is important to understand that NAND Flash, the full name of which is "Not AND Flash", is also known as NAND flash memory. It is a non-volatile memory based on NAND technology. It is a solid-state electronic memory that uses semiconductor materials and even spin-polarized charges, supplemented by physical operations based on flash cells, to store precise data models inside the chip to achieve fast data reading and writing. Its name "NAND" comes from the NAND Gate in the logic gate circuit, which uses multiple parallel NAND gate circuits to store and read data.

[0042] Preferably, the host computer module and the drive control module communicate based on the UDP protocol.

[0043] Furthermore, in some embodiments of the present invention, before the host computer module sends a test instruction to the driver module, the process includes:

[0044] The host computer module establishes a network connection with the drive control module;

[0045] The host computer module performs initialization operations and obtains test parameters.

[0046] In this embodiment, the host computer module and the drive control module establish a network connection based on the UDP protocol. After the host computer module and the drive control module are successfully connected, the host computer module performs an initialization operation.

[0047] The initialization operation includes selecting the storage mode of the flash memory chip, of which there are three storage modes: SLC (Single-Level Cell), TLC (Triple-Level Cell) and MLC (Multi-Level Cell).

[0048] The initialization operation also includes: configuration of test parameters, by setting the parameters of this test process, and then obtaining the test parameters. Through the initialization setting, the test parameters can be set based on the test requirements, thereby improving the flexibility of the test.

[0049] Specifically, when the host computer module fails to establish a network connection with the drive control module, the host computer module will detect the network cable connection and IP settings. Specifically, the initialization operation can be operated and processed on the UI interface of the host computer module.

[0050] Specifically, if the system has good portability, the host computer module establishes a link through IP and MAC, and the generation path of the test log can be selected.

[0051] Further, in some embodiments of the present invention, the test parameters include:

[0052] offset, number of tests and programming code length.

[0053] In this embodiment, based on these parameters, the test address of the flash memory chip can be confirmed, and the area to be tested in the flash memory chip can be accurately specified, thereby improving the test efficiency and enhancing the accuracy and reliability of the test.

[0054] Specifically, the test quantity includes the number of blocks that need to be tested in the flash memory chip and the number of pages that need to be tested in the flash memory chip.

[0055] Specifically, the offset includes a block offset and a page offset. The block address can be determined according to the block offset, the page address can be determined according to the page offset, and the base address, that is, the initial position of the test, can be confirmed according to the block address and the page address.

[0056] Specifically, the test parameters also include the mode of the programming code.

[0057] Specifically, the test parameters also include the test stations. During the test, it can be a single station or two stations, with a maximum of four stations.

[0058] Further, in some embodiments of the present invention, based on the test instruction, the driving control module tests the flash memory module of the chip to generate test data, and the driving control module sends the test data to the host computer module, including:

[0059] Based on the test parameters, determining a test address of the flash memory chip;

[0060] The drive control module performs a bad block test on the test address, obtains test data, and stores the test data in the first queue;

[0061] Based on the first queue, the number of test data is obtained;

[0062] When the number of test data reaches a preset number, the drive control module sends the test data in the first queue to the host computer module.

[0063] In this embodiment, "based on the test instruction, the driving control module tests the flash memory module of the chip" is a test content, which is essentially a cycle, wherein the test content includes, based on the base address, being able to confirm the address that the flash memory chip needs to be tested during the initial test, that is, the test address of the flash memory chip.

[0064] The drive control module performs a bad block test on the test address. After the bad block test, the drive module generates relevant data according to the condition of the bad block, that is, obtains the test data, and the drive control module stores the test data in the first queue.

[0065] According to the test data stored in the first queue, the number of test data can be obtained. The drive control module determines the number of test data. When the number of test data reaches the preset number, the drive control module sends the test data in the first queue to the host computer module as a data frame. Otherwise, the test parameters are incrementally processed to obtain the incrementally processed test parameters, and the drive control module tests the flash memory module of the chip based on the incrementally processed test parameters. By limiting the number of test data sent, a large amount of data congestion is avoided, so that the system can manage and process test data more efficiently, thereby optimizing the overall performance of the system.

[0066] It can be understood that only one specific test address can be obtained from the block position and the page position, that is, the test address corresponds one-to-one to the position combination composed of the block position and the page position.

[0067] It can be understood that the starting point of the test content of the present application is determined based on the test parameters. Therefore, when the number of test data does not reach the preset number, the drive control module will increment the test parameters to obtain a new test parameter, and obtain a new test address based on the new test parameter, and then test the new test address.

[0068] Specifically, the incremental processing of the test parameters includes: determining whether the number of blocks corresponding to the block position is greater than or equal to the number of blocks tested set in the test parameters; if the number corresponding to the block position is greater than or equal to the number of blocks tested, the test parameters are no longer incrementally processed; otherwise, determining the block position to be tested, determining whether the number of pages corresponding to the page position is greater than the number of pages tested set; if the number corresponding to the page position is greater than or equal to the number of pages tested, the page position is incrementally processed; otherwise, determining the page position to be tested.

[0069] It is understandable that, because the number of blocks and the number of pages in an independent storage unit are both limited, the block position will correspond to a certain block number, and the page number will correspond to a certain page number, that is, the block position has a corresponding block number, and the page position has a corresponding page number.

[0070] It is understandable that in the case of the first test, the block address to be tested is related to the block offset, and the page address to be tested is related to the page offset. In other words, during the initialization operation, even if the host computer module sets the address, the address will still be adjusted according to the block offset and page offset, and then the adjusted position will be used as the base address for testing.

[0071] Furthermore, in some embodiments of the present invention, the host computer module receives the test data, parses and processes the test data, and obtains the test results, including:

[0072] The host computer module is provided with a timeout detection mechanism for detecting whether the test data from the drive control module is received within a preset time threshold;

[0073] If the host computer module does not receive data within the preset time threshold, the host computer module will issue a prompt, analyze and process the test data, and obtain the test results.

[0074] In this embodiment, the host computer module is provided with a timeout detection mechanism. In the process of receiving data, if the host computer module does not receive data within a preset time threshold, the host computer module issues a prompt and parses and processes the test data to obtain the test result. By setting up a timeout detection mechanism, it is helpful to timely discover potential problems in the test process, improve the reliability of the test, and ensure the real-time nature of the test.

[0075] Specifically, the host computer module issues a prompt including: the host computer module issues an alarm signal and pops up a warning reminder on the UI interface. The warning reminder content includes: serial port opening failure, network connection establishment failure, reset failure, etc.

[0076] Furthermore, in some embodiments of the present invention, the drive control module performs a bad block test on the test address to obtain test data, including:

[0077] Based on the block address in the test address, the driving control module performs a first erase instruction on the flash memory chip;

[0078] Reading a first erasure state corresponding to the block address, and performing error checking on the flash memory chip based on the first erasure state and the erasure reference value to obtain a first checking result;

[0079] Based on the first verification result, determining whether there is a bad block in the flash memory chip;

[0080] The drive control module performs first preprocessing on the flash memory chip to obtain test data.

[0081] In this embodiment, based on the block address in the test address, the drive control module executes a first erase instruction to the flash memory chip, and the drive control module performs block erase on the flash memory chip. After the block address of the flash memory chip is erased, it will present a first erase state. On this basis, the first erase state is error-checked with a preset erase reference value to obtain a first check result. Then, based on the first check result, it is determined whether there is a bad block in the flash memory chip. The judgment ends here, and the drive control module stores the judgment situation, and the drive control module performs a first preprocessing on the flash memory chip, performs subsequent judgment and testing, and obtains test data.

[0082] Specifically, based on the block address in the test address, before the drive control module executes the first erase instruction on the flash memory chip, it includes: the drive control module performs bad block detection on the flash memory chip just shipped, and tests the bad blocks generated during the production process of the flash memory chip to facilitate the subsequent comparison of newly added bad blocks.

[0083] By performing a block erase readback test on the flash memory chip according to the block address, bad blocks can be detected, thereby improving the accuracy and reliability of the detection.

[0084] Furthermore, in some embodiments of the present invention, the drive control module performs a first preprocessing on the flash memory chip to obtain test data, including:

[0085] Based on the page address in the test address, reading the programming code at the page address;

[0086] Based on the page address and the programming code, error checking is performed on the flash memory chip to obtain a second checking result;

[0087] Based on the second verification result, determining whether there is a bad block in the flash memory chip;

[0088] The drive control module performs a third preprocessing on the flash memory chip to obtain test data.

[0089] In this embodiment, because the test parameters in the initialization operation include the length of the programming code and the content of the programming code, the flash memory chip will store these programming codes internally. Then, according to the page address, the programming code portion corresponding to the page address is read, and an error check can be performed based on the programming code and the read programming code to obtain a second check result.

[0090] On this basis, based on the second verification result, the drive control module determines whether there is a bad block in the flash memory chip, and the drive control module performs a third preprocessing on the flash memory chip to obtain test data.

[0091] By performing page programming readback tests on flash memory chips according to page addresses, the accuracy of detection is further improved, and the stability and reliability of the system are enhanced.

[0092] Furthermore, in some embodiments of the present invention, the drive control module performs a third preprocessing on the flash memory chip to obtain test data, including:

[0093] Based on the block address, the driving control module performs a second erase instruction on the flash memory chip;

[0094] Reading a second erasure state corresponding to the block address, and performing a code error check on the flash memory chip based on the second erasure state and the erasure reference value to obtain a third check result;

[0095] Based on the third verification result, determining whether there is a bad block in the flash memory chip;

[0096] The drive control module performs fourth preprocessing on the flash memory chip to obtain test data.

[0097] In this embodiment, because the page programming readback test is performed, the present invention performs a block erase readback test on the same block address again, and makes a judgment again based on the second erase state. By performing a block erase readback test on the flash memory chip according to the block address, the stability and reliability of the previous test results can be verified. If the test results are consistent for multiple times, the accuracy of the test results can be more assured, thereby enhancing the trust in the state of the flash memory chip.

[0098] Furthermore, in some embodiments of the present invention, the drive control module performs a fourth preprocessing on the flash memory chip to obtain test data, including:

[0099] The drive control module reads the register status information of the flash memory chip;

[0100] Based on the register status information, the status of the existing bad blocks is verified;

[0101] Summarize the test records and obtain the test data.

[0102] In this embodiment, the drive control module reads the status register information of the flash memory chip, verifies the status of the existing bad blocks, and analyzes the bad blocks of the flash memory chip according to the status register information. In addition to analyzing new bad blocks, it can also analyze the causes of the bad blocks. On this basis, the test records are summarized and processed to obtain test data. By judging the health status of the flash memory chip according to the status register information, the health status of the block can be judged more accurately, providing further guarantee for the stability and reliability of data storage.

[0103] Specifically, a test log can be generated based on the test data.

[0104] In the claims, specification and drawings of the present invention, the term "multiple" refers to two or more than two. Unless otherwise clearly defined, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the drawings, which is only for the purpose of more conveniently describing the present invention and making the description process simpler, rather than indicating or implying that the device or element referred to must have the specific orientation described, be constructed and operated in a specific orientation, so these descriptions cannot be understood as limiting the present invention; the terms "connect", "install", "fix" and the like should be understood in a broad sense. For example, "connection" can be a fixed connection between multiple objects, or a detachable connection between multiple objects, or an integral connection; it can be a direct connection between multiple objects, or an indirect connection between multiple objects through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood based on the specific circumstances of the above data.

[0105] In the claims, specification and drawings of the present invention, the description of the terms "one embodiment", "some embodiments", "specific embodiments" and the like means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In the claims, specification and drawings of the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0106] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A NAND Flash error analysis system for high-speed flexibility testing, characterized in that: include: The host computer module sends a test instruction to the drive control module; Based on the test instruction and the test sequence, the drive control module tests the flash memory chip to generate test data, and the drive control module sends the test data to the host computer module; The host computer module receives the test data, analyzes and processes the test data, and obtains the test results; Analyzing the bit error situation of the flash memory chip based on the test results; Based on the test instruction, the drive control module tests the flash memory module of the chip to generate test data, and the drive control module sends the test data to the host computer module, including: Based on the test parameters, determining a test address of the flash memory chip; The drive control module performs a bad block test on the test address, obtains the test data, and stores the test data in a first queue; Based on the first queue, obtaining the amount of test data; When the number of the test data reaches a preset number, the drive control module sends the test data in the first queue to the host computer module; The drive control module performs a bad block test on the test address to obtain the test data, including: Based on the block address in the test address, the drive control module performs a first erase instruction on the flash memory chip; Reading a first erasure state corresponding to the block address, and performing error checking on the flash memory chip based on the first erasure state and an erasure reference value to obtain a first checking result; Based on the first verification result, determining whether there is a bad block in the flash memory chip; The drive control module performs a first preprocessing on the flash memory chip to obtain the test data; The drive control module performs a first preprocessing on the flash memory chip to obtain the test data, including: Based on the page address in the test address, reading the programming code at the page address; Based on the page address and the programming code, performing error checking on the flash memory chip to obtain a second checking result; Based on the second verification result, determining whether the flash memory chip has a bad block; The drive control module performs a third preprocessing on the flash memory chip to obtain the test data; The drive control module performs a third preprocessing on the flash memory chip to obtain the test data, including: Based on the block address, the drive control module performs a second erase instruction on the flash memory chip; reading a second erasure state corresponding to the block address, and performing a code error check on the flash memory chip based on the second erasure state and the erasure reference value to obtain a third check result; Based on the third verification result, determining whether the flash memory chip has a bad block; The drive control module performs a fourth preprocessing on the flash memory chip to obtain the test data; The drive control module performs a fourth preprocessing on the flash memory chip to obtain the test data, including: The drive control module reads the register status information of the flash memory chip; Based on the register status information, complex verification is performed on the status of the existing bad blocks; Summarizing the test records to obtain the test data; The host computer module is provided with a real-time recording mechanism, and the host computer module will summarize the test results to form a traceable test report; The traceable test report can find out the test information of the bad blocks in the flash memory chip, and the test information includes the specific location and UID of the bad blocks; Based on the test instruction, the drive control module tests the flash memory module of the chip, which is a test content. When the number of test data reaches the preset number, the drive control module sends the test data in the first queue to the host computer module as a data frame. Otherwise, the test parameters are incremented to obtain the incremented test parameters, and the drive control module tests the flash memory module of the chip based on the incremented test parameters. The test parameter is incremented, including: if the number corresponding to the block position is equal to the number of tested blocks, the test parameter is no longer incremented, otherwise, the block position to be tested is determined; if the number corresponding to the page position is equal to the number of tested pages, the page position is incremented, otherwise, the page position to be tested is determined; The status of the existing bad blocks is verified, and the bad blocks of the flash memory chip are analyzed according to the status register information. In addition to analyzing new bad blocks, the causes of the bad blocks can also be analyzed.

2. The NAND Flash error analysis system for high-speed flexibility testing according to claim 1, characterized in that: Before the host computer module sends a test instruction to the drive module, it includes: The host computer module establishes a network connection with the drive control module; The host computer module performs initialization operations and obtains test parameters.

3. The NAND Flash error analysis system for high-speed flexibility testing according to claim 2, characterized in that: The test parameters include: offset, number of tests and programming code length.

4. The NAND Flash error analysis system for high-speed flexibility testing according to claim 1, characterized in that: The host computer module receives the test data, parses and processes the test data, and obtains the test results, including: The host computer module is provided with a timeout detection mechanism for detecting whether the test data from the drive control module is received within a preset time threshold; If the host computer module does not receive data within the preset time threshold, the host computer module issues a prompt, analyzes and processes the test data, and obtains the test result.

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