Power tube current detection circuit and method suitable for PMOS type LDO

Abstract

The invention discloses a power tube current detection circuit suitable for a PMOS type LDO, comprising a power tube MPN, a SENSE tube MPS, a PMOS tube PM5, a PMOS tube PM6, a PMOS tube PM7, an NMOS tube NM3, an NMOS tube NM4 and a current mirror comparison circuit, wherein the PMOS tube PM5, the PMOS tube PM6, the NMOS tube NM3 and the NMOS tube NM4 form a self-biased current mirror structure, and the PMOS tube PM7 is connected in series to the SENSE tube MPS branch and is controlled by the current mirror comparison circuit. The invention can not cause abnormal increase in circuit static power consumption under normal working conditions, and can accurately copy the power tube current at the same time.

Description

Technical Field

[0001] The present invention relates to a current detection circuit and method, in particular to a power tube current detection circuit and method suitable for a PMOS type LDO, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] As a universal linear power supply product, LDO has the characteristics of low cost, few peripheral devices, and high output voltage quality. It is widely used in various power supply scenarios. As a universal power supply product, its protection function is indispensable, such as overheating protection, overcurrent protection and other functions. For the overcurrent protection function, it is to detect the current of the power tube in real time to prevent the current of the power tube from exceeding a certain range, causing the chip to be damaged due to overheating. In order to realize the overcurrent protection function, the current of the power tube must be accurately detected first, so it is very meaningful to express the current of the power tube in real time with the lowest cost and the most reliable circuit.

[0003] Traditional test mode interface circuit such as Figure 2 As shown in the figure, the structure follows the drain of the SENSE MOS and the drain of the power tube through the error amplifier, so that the SENSE MOS can basically copy the working state of the power tube when working, thereby obtaining a relatively accurate copy current. After the current passes through the NMOS tube NM1, the voltage V_SENSE containing the current information of the power tube is obtained for use in the next stage. This structure will have the following problem:

[0004] When the power supply voltage is less than the set voltage of VOUT, the power tube will lose its voltage regulation function, and the GATE signal will become the voltage signal VDD, and VOUT will be infinitely close to the power supply voltage VDD. At this time, the power tube and the SENSE tube will work in the linear region. Assuming that the linear resistance of the power tube is Ronp, if the copy ratio of the power tube and the SENSE tube is N:1, then the linear impedance of the SENSE tube is N*Ronp. At this time, due to the offset voltage Vos of the error amplifier, it is difficult for VN to completely follow VOUT. When VN is less than VOUT, even if there is no current flowing through the power tube, the current flowing through the SENSE tube is:

[0005] Is=(VDD-VOUT-Vos) / (N*Ronp)

[0006] Since VOUT and VDD are very close, Is is basically determined by Vos / (N*Ronp). The larger the Vos, the larger the Is current, which causes the static power consumption of the chip to be abnormally large in this state. This problem is more fatal for low-power application scenarios. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a power tube current detection circuit and method suitable for PMOS type LDO, so as to solve the problem of abnormal increase of static power consumption of the power tube current detection circuit.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0009] A power tube current detection circuit suitable for a PMOS type LDO comprises a power tube MPN, a SENSE tube MPS, a PMOS tube PM5, a PMOS tube PM6, a PMOS tube PM7, an NMOS tube NM3, an NMOS tube NM4 and a current mirror comparison circuit, wherein the source of the power tube MPN and the source of the SENSE tube MPS are connected to a power supply VDD, the gate of the power tube MPN and the gate of the SENSE tube MPS are connected to a control signal GATE, the drain of the power tube MPN is connected to the source of the PMOS tube PM5 and the first input end of the current mirror comparison circuit to generate an output signal VOUT, and the second input end of the current mirror comparison circuit is connected to the power supply VDD. VDD, the drain of the SENSE tube MPS is connected to the source of the PMOS tube PM6, the gate of the PMOS tube PM5 is connected to the drain of the PMOS tube PM5, the drain of the NMOS tube NM3 and the gate of the PMOS tube PM6, the drain of the PMOS tube PM6 is connected to the source of the PMOS tube PM7, the gate of the PMOS tube PM7 is connected to the output end of the current mirror comparison circuit, the drain of the PMOS tube PM7 is connected to the drain of the NMOS tube NM4, the gate of the NMOS tube NM4 and the gate of the NMOS tube NM3 and connected to the detection voltage signal V_SENSE, and the source of the NMOS tube NM3 and the source of the NMOS tube NM4 are grounded.

[0010] Furthermore, the current mirror comparison circuit includes a PMOS tube PM3, a PMOS tube PM4, an NMOS tube NM1, an NMOS tube NM2 and a Schmitt trigger SMT1, the source of the PMOS tube PM3 serves as the first input end of the current mirror comparison circuit and is connected to the output signal VOUT, the source of the PMOS tube PM4 serves as the second input end of the current mirror comparison circuit and is connected to the power supply VDD, the gate of the PMOS tube PM3 is connected to the gate of the PMOS tube PM4, the drain of the PMOS tube PM3 is connected to the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 and the gate of the NMOS tube NM2, the drain of the PMOS tube PM4 is connected to the drain of the NMOS tube NM2 and the input end of the Schmitt trigger SMT1, the source of the NMOS tube NM1 and the source of the NMOS tube NM2 are grounded, and the output end of the Schmitt trigger SMT1 serves as the output end of the current mirror comparison circuit.

[0011] Furthermore, the PMOS transistor PM3 and the PMOS transistor PM4 match each other, and the size ratio of the PMOS transistor PM3 and the PMOS transistor PM4 is N:1, where N>1.

[0012] Furthermore, the NMOS tube NM1 and the NMOS tube NM2 match each other, and the size ratio of the NMOS tube NM1 and the NMOS tube NM2 is N:N.

[0013] Furthermore, a self-bias current mirror circuit is also included, and the output end of the self-bias current mirror circuit is connected to the drain of the NMOS tube NM3.

[0014] Furthermore, the self-biased current mirror circuit comprises a PMOS tube PM1, a PMOS tube PM2, a reference current source I0, an NMOS tube NM5 and an NMOS tube NM6, the source of the PMOS tube PM1 and the source of the PMOS tube PM2 are connected to the power supply VDD, the gate of the PMOS tube PM1 is connected to the drain of the PMOS tube PM1, one end of the reference current source I0, the gate of the PMOS tube PM2, the gate of the PMOS tube PM3 and the gate of the PMOS tube PM4, the other end of the reference current source I0 is grounded, the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM5, the gate of the NMOS tube NM5 and the gate of the NMOS tube NM6, the source of the NMOS tube NM5 and the source of the NMOS tube NM6 are grounded, and the drain of the NMOS tube NM6 serves as the output end of the self-biased current mirror circuit.

[0015] Furthermore, the PMOS tube PM5, PMOS tube PM6, NMOS tube NM3 and NMOS tube NM4 form a self-biased current mirror structure, the PMOS tube PM5 and the PMOS tube PM6 match each other and the size ratio is N:N, and the NMOS tube NM3 and the NMOS tube NM4 match each other and the size ratio is N:N.

[0016] A power tube current detection method based on a power tube current detection circuit suitable for a PMOS type LDO comprises the following steps:

[0017] The size ratio of the PMOS tube PM3 and the PMOS tube PM4 in the current mirror comparison circuit is N:1, that is, the size of the PMOS tube PM3 is larger than the size of the PMOS tube PM4;

[0018] Under normal working conditions, the voltage of the output signal VOUT is lower than the voltage of the power supply VDD. At this time, the current flowing through the PMOS tube PM3 is less than the current flowing through the PMOS tube PM4. The input power supply VN of the Schmitt trigger SMT1 is at a high level. The input power supply VN of the Schmitt trigger SMT1 controls the PMOS tube PM7 to turn on after passing through the Schmitt trigger SMT1. At this time, the current detection circuit works normally.

[0019] When the voltage of the power supply VDD is lower than the set voltage of the output signal VOUT, the voltage of the output signal VOUT will be infinitely close to the voltage of the power supply VDD. At this time, the current flowing through the PMOS tube PM3 is greater than the current flowing through the PMOS tube PM4. The input power supply VN of the Schmitt trigger SMT1 is at a low level. The input power supply VN of the Schmitt trigger SMT1 controls the PMOS tube PM7 to be turned off after passing through the Schmitt trigger SMT1. No abnormal current will flow through the branch where the SENSE tube MPS is located, so that the current detection circuit is in a normal state in this state.

[0020] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a power tube current detection circuit and method suitable for PMOS type LDO, the main structure of the circuit is simple, and under normal working conditions, the circuit static power consumption will not be abnormally increased, and the power tube current can be accurately copied. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The invention is a circuit principle diagram of a power tube current detection circuit applicable to a PMOS type LDO.

[0022] Figure 2 The invention is a circuit schematic diagram of a power tube current detection circuit of a PMOS type LDO in the prior art. DETAILED DESCRIPTION

[0023] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0024] like Figure 1As shown, a power tube current detection circuit suitable for a PMOS type LDO of the present invention comprises a power tube MPN, a SENSE tube MPS, a PMOS tube PM5, a PMOS tube PM6, a PMOS tube PM7, an NMOS tube NM3, an NMOS tube NM4 and a current mirror comparison circuit, wherein the source of the power tube MPN and the source of the SENSE tube MPS are connected to a power supply VDD, the gate of the power tube MPN and the gate of the SENSE tube MPS are connected to a control signal GATE, the drain of the power tube MPN is connected to the source of the PMOS tube PM5 and a first input terminal of the current mirror comparison circuit to generate an output signal VOUT, and the second input terminal of the current mirror comparison circuit is connected to the source of the PMOS tube PM5 and the first input terminal of the current mirror comparison circuit to generate an output signal VOUT. The power supply VDD is connected, the drain of the SENSE tube MPS is connected to the source of the PMOS tube PM6, the gate of the PMOS tube PM5 is connected to the drain of the PMOS tube PM5, the drain of the NMOS tube NM3 and the gate of the PMOS tube PM6, the drain of the PMOS tube PM6 is connected to the source of the PMOS tube PM7, the gate of the PMOS tube PM7 is connected to the output end of the current mirror comparison circuit, the drain of the PMOS tube PM7 is connected to the drain of the NMOS tube NM4, the gate of the NMOS tube NM4 and the gate of the NMOS tube NM3 and connected to the detection voltage signal V_SENSE, and the source of the NMOS tube NM3 and the source of the NMOS tube NM4 are grounded.

[0025] The current mirror comparison circuit comprises a PMOS tube PM3, a PMOS tube PM4, an NMOS tube NM1, an NMOS tube NM2 and a Schmitt trigger SMT1, the source of the PMOS tube PM3 serves as a first input end of the current mirror comparison circuit and is connected to an output signal VOUT, the source of the PMOS tube PM4 serves as a second input end of the current mirror comparison circuit and is connected to a power supply VDD, the gate of the PMOS tube PM3 is connected to the gate of the PMOS tube PM4, the drain of the PMOS tube PM3 is connected to the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 and the gate of the NMOS tube NM2, the drain of the PMOS tube PM4 is connected to the drain of the NMOS tube NM2 and the input end of the Schmitt trigger SMT1, the source of the NMOS tube NM1 and the source of the NMOS tube NM2 are grounded, and the output end of the Schmitt trigger SMT1 serves as the output end of the current mirror comparison circuit.

[0026] The PMOS transistor PM3 and the PMOS transistor PM4 match each other, and the size ratio of the PMOS transistor PM3 and the PMOS transistor PM4 is N:1, where N>1.

[0027] The NMOS tube NM1 and the NMOS tube NM2 match each other, and the size ratio of the NMOS tube NM1 and the NMOS tube NM2 is N:N.

[0028] A power tube current detection circuit suitable for a PMOS type LDO of the present invention further comprises a self-biased current mirror circuit, and the output end of the self-biased current mirror circuit is connected to the drain of the NMOS tube NM3.

[0029] The self-biased current mirror circuit comprises a PMOS tube PM1, a PMOS tube PM2, a reference current source I0, an NMOS tube NM5 and an NMOS tube NM6, the source of the PMOS tube PM1 and the source of the PMOS tube PM2 are connected to a power supply VDD, the gate of the PMOS tube PM1 is connected to the drain of the PMOS tube PM1, one end of the reference current source I0, the gate of the PMOS tube PM2, the gate of the PMOS tube PM3 and the gate of the PMOS tube PM4, the other end of the reference current source I0 is grounded, the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM5, the gate of the NMOS tube NM5 and the gate of the NMOS tube NM6, the source of the NMOS tube NM5 and the source of the NMOS tube NM6 are grounded, and the drain of the NMOS tube NM6 serves as the output end of the self-biased current mirror circuit.

[0030] The PMOS tube PM5, the PMOS tube PM6, the NMOS tube NM3 and the NMOS tube NM4 form a self-biased current mirror structure. The PMOS tube PM5 and the PMOS tube PM6 match each other and the size ratio is N:N. The NMOS tube NM3 and the NMOS tube NM4 match each other and the size ratio is N:N.

[0031] A power tube current detection method based on a power tube current detection circuit suitable for a PMOS type LDO comprises the following steps:

[0032] The size ratio of the PMOS tube PM3 and the PMOS tube PM4 in the current mirror comparison circuit is N:1, that is, the size of the PMOS tube PM3 is larger than that of the PMOS tube PM4. Assuming VOUT=VDD, if the current flowing through the PMOS tube PM3 is I, the current flowing through the PMOS tube PM4 is I / N, that is, if the voltage of the output signal VOUT is equal to the power supply VDD, the current flowing through the PMOS tube PM3 is larger than the current flowing through the PMOS tube PM4.

[0033] Under normal working conditions, the voltage of the output signal VOUT is lower than the voltage of the power supply VDD by more than tens of mV, that is, the voltage difference has a greater impact on the current flowing through the two PMOS tubes than the impact of the sizes of the two PMOS tubes on the current. At this time, the current flowing through the PMOS tube PM3 is smaller than the current flowing through the PMOS tube PM4, and the input power supply VN of the Schmitt trigger SMT1 is at a high level. The input power supply VN of the Schmitt trigger SMT1 controls the PMOS tube PM7 to open after passing through the Schmitt trigger SMT1. At this time, the current detection circuit works normally.

[0034] When the voltage of the power supply VDD is lower than the set voltage of the output signal VOUT, the voltage of the output signal VOUT will be infinitely close to the voltage of the power supply VDD. At this time, the current flowing through the PMOS tube PM3 is greater than the current flowing through the PMOS tube PM4. The input power supply VN of the Schmitt trigger SMT1 is at a low level. The input power supply VN of the Schmitt trigger SMT1 controls the PMOS tube PM7 to be turned off after passing through the Schmitt trigger SMT1. No abnormal current will flow through the branch where the SENSE tube MPS is located, so that the current detection circuit is in a normal state in this state.

[0035] The present invention provides a power tube current detection circuit and method suitable for a PMOS type LDO. The main structure of the circuit is simple, and abnormal increase in circuit static power consumption will not be caused under normal working conditions, while the power tube current can be accurately copied.

[0036] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A power tube current detection circuit suitable for a PMOS type LDO, characterized in that: The invention comprises a power tube MPN, a SENSE tube MPS, a PMOS tube PM5, a PMOS tube PM6, a PMOS tube PM7, an NMOS tube NM3, an NMOS tube NM4 and a current mirror comparison circuit, wherein the source of the power tube MPN and the source of the SENSE tube MPS are connected to a power supply VDD, the gate of the power tube MPN and the gate of the SENSE tube MPS are connected to a control signal GATE, the drain of the power tube MPN is connected to the source of the PMOS tube PM5 and the first input end of the current mirror comparison circuit to generate an output signal VOUT, the second input end of the current mirror comparison circuit is connected to the power supply VDD, the SENSE tube MPN The drain of S is connected to the source of the PMOS tube PM6, the gate of the PMOS tube PM5 is connected to the drain of the PMOS tube PM5, the drain of the NMOS tube NM3 and the gate of the PMOS tube PM6, the drain of the PMOS tube PM6 is connected to the source of the PMOS tube PM7, the gate of the PMOS tube PM7 is connected to the output end of the current mirror comparison circuit, the drain of the PMOS tube PM7 is connected to the drain of the NMOS tube NM4, the gate of the NMOS tube NM4 and the gate of the NMOS tube NM3 and connected to the detection voltage signal V_SENSE, and the source of the NMOS tube NM3 and the source of the NMOS tube NM4 are grounded; The current mirror comparison circuit comprises a PMOS tube PM3, a PMOS tube PM4, an NMOS tube NM1, an NMOS tube NM2 and a Schmitt trigger SMT1, the source of the PMOS tube PM3 serves as a first input end of the current mirror comparison circuit and is connected to an output signal VOUT, the source of the PMOS tube PM4 serves as a second input end of the current mirror comparison circuit and is connected to a power supply VDD, the gate of the PMOS tube PM3 is connected to the gate of the PMOS tube PM4, the drain of the PMOS tube PM3 is connected to the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 and the gate of the NMOS tube NM2, the drain of the PMOS tube PM4 is connected to the drain of the NMOS tube NM2 and the input end of the Schmitt trigger SMT1, the source of the NMOS tube NM1 and the source of the NMOS tube NM2 are grounded, and the output end of the Schmitt trigger SMT1 serves as the output end of the current mirror comparison circuit.

2. The power tube current detection circuit suitable for PMOS type LDO according to claim 1, characterized in that: The PMOS transistor PM3 and the PMOS transistor PM4 match each other, and the size ratio of the PMOS transistor PM3 and the PMOS transistor PM4 is N:1, where N>1.

3. The power tube current detection circuit suitable for PMOS type LDO according to claim 1, characterized in that: The NMOS tube NM1 and the NMOS tube NM2 match each other, and the size ratio of the NMOS tube NM1 and the NMOS tube NM2 is N:N.

4. The power tube current detection circuit suitable for PMOS type LDO according to claim 1, characterized in that: It also includes a self-bias current mirror circuit, the output end of which is connected to the drain of the NMOS tube NM3.

5. The power tube current detection circuit applicable to a PMOS type LDO according to claim 4, characterized in that: The self-biased current mirror circuit comprises a PMOS tube PM1, a PMOS tube PM2, a reference current source I0, an NMOS tube NM5 and an NMOS tube NM6, the source of the PMOS tube PM1 and the source of the PMOS tube PM2 are connected to a power supply VDD, the gate of the PMOS tube PM1 is connected to the drain of the PMOS tube PM1, one end of the reference current source I0, the gate of the PMOS tube PM2, the gate of the PMOS tube PM3 and the gate of the PMOS tube PM4, the other end of the reference current source I0 is grounded, the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM5, the gate of the NMOS tube NM5 and the gate of the NMOS tube NM6, the source of the NMOS tube NM5 and the source of the NMOS tube NM6 are grounded, and the drain of the NMOS tube NM6 serves as the output end of the self-biased current mirror circuit.

6. The power tube current detection circuit applicable to a PMOS type LDO according to claim 1, characterized in that: The PMOS tube PM5, PMOS tube PM6, NMOS tube NM3 and NMOS tube NM4 form a self-biased current mirror structure, the PMOS tube PM5 and the PMOS tube PM6 match each other and the size ratio is N:N, the NMOS tube NM3 and the NMOS tube NM4 match each other and the size ratio is N:N.

7. A power tube current detection method based on the power tube current detection circuit applicable to a PMOS type LDO according to any one of claims 1 to 6, characterized in that The following steps are involved: The size ratio of the PMOS tube PM3 and the PMOS tube PM4 in the current mirror comparison circuit is N:1, that is, the size of the PMOS tube PM3 is larger than the size of the PMOS tube PM4; Under normal working conditions, the voltage of the output signal VOUT is lower than the voltage of the power supply VDD. At this time, the current flowing through the PMOS tube PM3 is less than the current flowing through the PMOS tube PM4. The input power supply VN of the Schmitt trigger SMT1 is at a high level. The input power supply VN of the Schmitt trigger SMT1 controls the PMOS tube PM7 to turn on after passing through the Schmitt trigger SMT1. At this time, the current detection circuit works normally. When the voltage of the power supply VDD is lower than the set voltage of the output signal VOUT, the voltage of the output signal VOUT will be infinitely close to the voltage of the power supply VDD. At this time, the current flowing through the PMOS tube PM3 is greater than the current flowing through the PMOS tube PM4. The input power supply VN of the Schmitt trigger SMT1 is at a low level. The input power supply VN of the Schmitt trigger SMT1 controls the PMOS tube PM7 to be turned off after passing through the Schmitt trigger SMT1. No abnormal current will flow through the branch where the SENSE tube MPS is located, so that the current detection circuit is in a normal state in this state.

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