A CXL bias management method based on cache soft-hard coordination

Abstract

The present invention discloses a CXL bias management method based on cache software and hardware coordination, which is used to optimize memory access and cache consistency management in a computer system. It includes providing a CXL device, which includes a CXL.mem interface, a CXL.cache interface and a bias management component. The bias management component is composed of a request parsing module, a command queue, a bias cache, a device processor and a register module. The request parsing module is responsible for parsing the CXL.mem request, and the device processor dynamically adjusts the bias state according to the state of CXL.cache. The bias cache control module manages the cache through the least used strategy LRU, improves the cache hit rate, and reduces the response delay. Through a management method combining software and hardware. The present invention can significantly improve the system response speed, reduce power consumption, and optimize resource utilization under high load and complex scenarios, and further improve the performance and stability of the system.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer system interconnection, and specifically relates to a CXL bias management method based on cache software and hardware coordination, and in particular optimizes bias management by means of software and hardware coordination to improve cache consistency and memory management efficiency. Background Art

[0002] With the explosive growth of data volume and the increasing demand for high-performance computing, traditional interconnect technologies are gradually unable to meet the needs of modern computing environments for high throughput and low latency. As an emerging high-speed interconnect technology, CXL (Compute Express Link) allows the system to find a balance between efficient memory access and cache consistency management by providing CXL.cache and CXL.mem protocols.

[0003] Among the three main types of CXL technology, especially type 2 (CXLType2) technology, it emphasizes maintaining cache consistency between devices and hosts through bias management mechanisms. Current bias management mainly relies on the following two modes:

[0004] Software-assisted mode: The host actively manages the bias state through software and issues bias state modification requests when necessary.

[0005] Hardware autonomous mode: The device adjusts the bias state based on the current request and cache status without relying on host software.

[0006] However, these two modes have their own advantages and disadvantages. The software-assisted mode can manage the bias state more accurately, but it increases the computing burden of the host. The hardware-autonomous mode reduces the burden on the host, but may cause performance degradation in complex scenarios. Therefore, the existing technology has the following problems:

[0007] Lack of flexibility: It is not possible to flexibly switch the bias management mode in different scenarios.

[0008] Insufficient performance optimization: Lack of efficient management of bias cache affects the speed of bias state switching.

[0009] High resource consumption: When processing complex tasks, a single bias management mode may lead to excessive consumption of system resources and reduce overall efficiency. Summary of the invention

[0010] In order to solve the problems of insufficient flexibility, insufficient performance optimization and high resource consumption, the present invention provides a CXL bias management method based on cache software and hardware coordination. By introducing a bias management mechanism combining software and hardware, an optimized bias cache strategy and a dynamic mode switching method, the bias management efficiency of the system is effectively improved, power consumption is reduced, and flexible solutions are provided in different application scenarios.

[0011] In order to achieve the above object, the present invention is implemented by the following technical solutions:

[0012] A CXL bias management method based on cache soft-hard coordination, the method comprising the following steps:

[0013] A CXL device is provided, the device including a CXL.mem interface, a CXL.cache interface, and a bias management component;

[0014] The CXL.mem request is parsed by the request parsing module. When the received CXL.mem request meets the requirements for modifying the bias state, the information of the CXL.mem request is filled into the command queue;

[0015] The device processor determines whether the bias state needs to be adjusted based on the content of the CXL.mem request and the current state of CXL.cache. If adjustment is required, the bias conversion request is filled in the command queue;

[0016] The command parsing module parses the offset conversion request in the command queue and generates corresponding operation instructions;

[0017] The bias cache control module executes data access of the bias table according to the operation instructions generated by the command parsing module, manages the hits of the bias cache, and performs cache replacement through the least used strategy LRU;

[0018] When changing the bias state, determine whether the current bias cache hits. If it hits, directly update the bias table in the cache and return completion information; if it does not hit, perform cache replacement and write the new bias state to the internal data cache DRAM.

[0019] Further, the bias management component is implemented by the following steps:

[0020] The CXL.mem request is parsed by the request parsing module, and when the received CXL.mem request meets the requirements for modifying the bias state, the request information is written into the CXL.mem request queue;

[0021] In software-assisted mode, the device processor receives the bias conversion request sent by the host and writes it into the command queue; in hardware autonomous mode, the device processor determines whether the bias state needs to be adjusted based on the CXL.mem request parsed by the request parsing module and the current state of CXL.cache. If so, the bias conversion request is written into the command queue;

[0022] The command parsing module parses the bias conversion commands generated by the device processor and converts these commands into operation instructions for the bias state;

[0023] The data access operation of the biased table is executed through the biased cache control module, and the hit and replacement of the biased cache are managed through the least used strategy LRU;

[0024] When the bias cache hits, the bias state in the bias table is directly updated; when the bias cache misses, cache replacement is performed and the new bias state is written to the cache and internal data cache;

[0025] Through the register module, configure the hardware functions of the device and return the hardware status as needed;

[0026] Cache the request information filled in by the request parsing module in the CXL.mem request queue, and store the bias conversion request and bias state read and write request generated by the device processor;

[0027] The write command queue is used to cache the write command and related data issued by the device processor; the read command queue is used to cache the read command issued by the device processor;

[0028] The cache data returned by the biased cache control module is cached through the read data queue to complete the data read operation.

[0029] Furthermore, the bias state switching method in the software-assisted mode in the CXL.mem request processing includes the following operations:

[0030] The host sends a bias conversion request to the device processor through the OpenCL API;

[0031] After receiving the bias conversion request, the device processor fills it into the command queue and determines whether the bias state needs to be changed based on the current state of CXL.cache;

[0032] The device processor sends the bias state modification request to the command queue, and parses the command through the command parsing module to perform the bias state change operation;

[0033] After receiving the bias state modification command sent by the host through the OpenCL API, the device processor executes the update of the bias state.

[0034] Furthermore, the specific operations performed by the offset cache control module include:

[0035] Determine whether the bias cache is enabled;

[0036] If enabled, check whether the cache hits;

[0037] If the cache hits, the offset table in the cache is directly updated and the completion information is returned;

[0038] If the cache misses, a cache replacement is performed and a new bias state is written to the internal data cache DRAM;

[0039] If the bias cache is not enabled, the new bias state is written directly to the internal data cache DRAM.

[0040] Furthermore, the bias state switching method in the hardware autonomous mode in the CXL.mem request processing includes the following operations:

[0041] Parse the request from the CXL.mem interface to determine whether the request involves a change in the bias state;

[0042] If the CXL.mem request needs to change the bias state, the request information is filled into the CXL.mem request queue of the command queue;

[0043] The device processor checks the CXL.mem request queue and obtains the CXL.mem request that needs to be processed;

[0044] Determine whether the bias state needs to be changed based on the current CXL.cache state and the information in the CXL.mem request;

[0045] If the bias state needs to be changed, the write command is filled into the command queue, and the command parsing module executes the bias state change.

[0046] Furthermore, the bias cache of the CXL device includes 4 flag SRAMs and 4 bias state SRAMs, each flag SRAM accommodates 512 flags, and each bias state SRAM accommodates 512 bias state groups.

[0047] Furthermore, the biased cache adopts a cache replacement mechanism based on a least-used strategy (LRU) to retain frequently accessed data, so as to improve the hit rate of the biased cache.

[0048] Furthermore, the least used strategy LRU of the offset cache includes the following operations:

[0049] Use 4 access counters to monitor the hit status of 4 sets of caches;

[0050] If a hit occurs, the corresponding access counter is incremented by 1. At this time, the corresponding bias state exists in the cache and can be used directly;

[0051] If there is a miss, the sizes of the four access counters are compared, the bias state corresponding to the request is moved from the internal data cache DRAM to the corresponding cache, and the current access counter is cleared.

[0052] Furthermore, the device processor optimizes the performance in different application scenarios by dynamically adjusting the size of the offset table, specifically including:

[0053] Under high load conditions, the capacity of the bias table is increased; under low load conditions, the capacity of the bias table is reduced; the adjustment of the bias table size is completed autonomously by hardware.

[0054] Furthermore, after receiving the CXL.mem request, the device processor determines whether the bias state needs to be adjusted based on the current state of CXL.cache. If adjustment is required, the bias conversion request is filled into the command queue, and the bias state change is executed through the command parsing module to ensure the consistency of CXL.cache.

[0055] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention significantly improves the performance, resource utilization efficiency and flexibility of the system by adopting a CXL bias management method that combines software and hardware. Through the bias management mechanism that combines software and hardware, the system can intelligently select the optimal management mode according to different workloads, reduce the communication overhead between the host and the device processor, speed up the bias state switching speed, and improve the responsiveness of the system. At the same time, the introduction of bias cache and least used strategy significantly improves the cache hit rate and reduces the probability of cache misses, especially under high load conditions, and improves the overall processing efficiency. The present invention also effectively reduces system power consumption and optimizes resource utilization by dynamically switching between software-assisted mode and hardware autonomous mode, so that the system maintains low energy consumption under high load and multi-tasking scenarios, and significantly improves the energy efficiency ratio. In addition, the intelligent management method of the present invention enables the system to flexibly respond to complex application scenarios, avoids the performance bottleneck of a single mode, simplifies the host burden, optimizes resource allocation, and improves the operating efficiency of the system. Through the optimization of the bias cache control module, the present invention ensures efficient switching and consistency maintenance of the bias state, and enhances the stability and reliability of the system. It also includes using register configuration and processor to switch between software-assisted and hardware-autonomous modes, reasonably allocating hardware resources, saving hardware resources and improving system performance. In summary, the present invention has achieved significant improvements in system performance, power consumption optimization, resource utilization, system flexibility and stability, and has strong innovation and practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0057] Figure 1 A hardware implementation architecture diagram of an embodiment of the present invention;

[0058] Figure 2 This is a flowchart of autonomous hardware switching in an embodiment of the present invention;

[0059] Figure 3 This is a flow chart of software-assisted switching in an embodiment of the present invention;

[0060] Figure 4 This is a flow chart of biased cache control in an embodiment of the present invention;

[0061] Figure 5 This is a data flow diagram of autonomous switching of bias hardware in an embodiment of the present invention;

[0062] Figure 6 A data flow diagram of bias software assisted switching in an embodiment of the present invention;

[0063] Figure 7 The hardware implementation architecture diagram of an embodiment of the present invention shows the management and storage distribution of bias states;

[0064] Figure 8 The bias cache mapping diagram of the embodiment of the present invention shows the mapping process of the bias state from DRAM to SRAM;

[0065] Fig. 9 The flowchart of the bias hardware autonomous switching of the embodiment of the present invention describes the detailed steps of processing the bias state switching;

[0066] Fig.10 This is a flow chart of bias software-assisted switching according to an embodiment of the present invention, showing the process of the host controlling the bias state switching through software. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0068] Example 1

[0069] like Figure 1 As shown in FIG. 1 , an embodiment of the present invention is provided, which provides a CXL bias management method based on cache soft-hard coordination, including:

[0070] A CXL device is provided, the device including a CXL.mem interface, a CXL.cache interface, and a bias management component;

[0071] The bias management component is implemented by the following steps:

[0072] The CXL.mem request is parsed by the request parsing module, and when the received CXL.mem request meets the requirements for modifying the bias state, the request information is written into the CXL.mem request queue;

[0073] In software-assisted mode, the device processor receives the bias conversion request sent by the host and writes it into the command queue; in hardware autonomous mode, the device processor determines whether the bias state needs to be adjusted based on the CXL.mem request parsed by the request parsing module and the current state of CXL.cache. If so, the bias conversion request is written into the command queue;

[0074] The command parsing module parses the bias conversion commands generated by the device processor and converts these commands into operation instructions for the bias state;

[0075] The data access operation of the biased table is executed through the biased cache control module, and the hit and replacement of the biased cache are managed through the least used strategy LRU;

[0076] When the bias cache hits, the bias state in the bias table is directly updated; when the bias cache misses, cache replacement is performed and the new bias state is written to the cache and internal data cache;

[0077] Through the register module, configure the hardware functions of the device and return the hardware status as needed;

[0078] Cache the request information filled in by the request parsing module in the CXL.mem request queue, and store the bias conversion request and bias state read and write request generated by the device processor;

[0079] The write command queue is used to cache the write command and related data issued by the device processor; the read command queue is used to cache the read command issued by the device processor;

[0080] The cache data returned by the biased cache control module is cached through the read data queue to complete the data read operation.

[0081] Preferably, the CXL.mem request is parsed by the request parsing module, and when the CXL.mem request received by the request parsing module meets the requirement for modifying the bias state, the information of the CXL.mem request is filled into the command queue;

[0082] Among them, Figure 3 As shown, the software-assisted bias state switching method in CXL.mem request processing includes the following steps:

[0083] like Figure 6 As shown, the host sends a bias conversion request to the device processor through the OpenCL API;

[0084] After receiving the bias conversion request, the device processor fills it into the command queue and determines whether the bias state needs to be changed based on the current state of CXL.cache;

[0085] The device processor sends the bias state modification request to the command queue, and parses the command through the command parsing module to perform the bias state change operation;

[0086] After receiving the bias state modification command sent by the host through the OpenCL API, the device processor executes the update of the bias state.

[0087] like Figure 2 , Figure 5 As shown, the bias state switching method in the hardware autonomous mode in the CXL.mem request processing includes the following operations:

[0088] Parse the request from the CXL.mem interface to determine whether the request involves a change in the bias state;

[0089] If the CXL.mem request needs to change the bias state, the request information is filled into the CXL.mem request queue of the command queue;

[0090] The device processor checks the CXL.mem request queue and obtains the CXL.mem request that needs to be processed;

[0091] Determine whether the bias state needs to be changed based on the current CXL.cache state and the information in the CXL.mem request;

[0092] If the bias state needs to be changed, the write command is filled into the command queue, and the command parsing module executes the bias state change.

[0093] Preferably, the device processor determines whether the bias state needs to be adjusted according to the request received by the CXL.mem request interface and the current state of CXL.cache, and if adjustment is required, fills in the bias conversion request in the command queue;

[0094] The bias cache of the CXL device includes 4 flag SRAMs and 4 bias state SRAMs, each flag SRAM accommodates 512 flags, and each bias state SRAM accommodates 512 bias state groups.

[0095] Preferably, Figure 4 As shown, the bias cache control module controls the data access of the bias table and the hit management of the bias cache according to the command parsed by the command parsing module, and performs cache replacement through the least used strategy LRU;

[0096] The least used strategy LRU of the offset cache includes the following operations:

[0097] Use 4 access counters to monitor the hit status of 4 sets of caches;

[0098] If a hit occurs, the corresponding access counter is incremented by 1. At this time, the corresponding bias state exists in the cache and can be used directly;

[0099] If there is a miss, the sizes of the four access counters are compared, the bias state corresponding to the request is moved from the internal data cache DRAM to the corresponding cache, and the current access counter is cleared.

[0100] Preferably, when changing the bias state, the device determines whether the current bias cache hits, and if so, changes the bias table in the cache and returns completion information; if not, performs cache replacement and writes a new bias state to the internal data cache DRAM.

[0101] The biased cache adopts a cache replacement mechanism based on a least-used strategy, giving priority to retaining frequently accessed data, so as to improve the hit rate of the biased cache.

[0102] Furthermore, the least used strategy of the offset cache includes the following steps:

[0103] Four access counters are used to monitor the hits of the four cache groups;

[0104] If a hit occurs, the corresponding access counter is incremented by 1. At this time, the corresponding bias state exists in the cache and can be used directly;

[0105] If there is a miss, the sizes of the four access counters are compared, the bias state corresponding to the request is moved from the DRAM to the corresponding cache, and the current access counter is cleared.

[0106] Furthermore, the bias cache is managed using the least-recently-used strategy (LRU), and its specific implementation logic is as follows:

[0107] Cache storage structure: The bias cache consists of multiple groups of SRAM, each group of SRAM stores a part of the bias state data, and maintains an access record table to record the most recent access time of each bias state.

[0108] Hit and Replace: When a request is made to access the bias cache, first check whether the corresponding bias state exists in the access record table. If it hits, the bias state is moved to the top of the access record table, indicating that it is the most recently accessed state. If it misses, the least used bias state is replaced with the new bias state according to the access record table, and the access record table is updated.

[0109] Cache update: When a bias state change is made, if the new state is already in the cache, it is directly updated; otherwise, the least used bias state is replaced according to the LRU policy, and the new state is written to SRAM and placed at the top of the access record table.

[0110] Through this strategy, the system can maximize the cache hit rate and reduce the frequency of DRAM access in the case of frequent access and change of bias state, thereby improving the system's response speed and processing efficiency.

[0111] Furthermore, the device processor optimizes the performance in different application scenarios by dynamically adjusting the size of the offset table, specifically including:

[0112] Under high load conditions, the capacity of the bias table is increased; under low load conditions, the capacity of the bias table is reduced; the adjustment of the bias table size is completed autonomously by hardware.

[0113] Description of high-load situations: When the system is running complex computing tasks, especially scenarios involving large-scale data processing or high-concurrency access, such as high-performance computing (HPC) or artificial intelligence training, the system processor faces a large number of CXL.mem requests, which will cause a large number of memory read and write operations and cache consistency issues. In these cases, in order to ensure that the system can respond and process requests quickly, the capacity of the bias table needs to be dynamically increased, thereby speeding up the switching frequency of the bias state and improving the cache hit rate, reducing system latency and resource conflicts. At this time, after the hardware autonomously detects the high-load state, it will automatically adjust the size of the bias table to ensure that the system can run efficiently under high load.

[0114] Description of low load conditions: When the system is in a light task or idle state, such as executing low-priority tasks in the background or processing simple user requests, the CXL.mem request frequency drops significantly and the system's computational load is significantly reduced. At this time, maintaining a large bias table may lead to unnecessary resource occupation and energy consumption. Therefore, after the hardware autonomously detects the low load state, it will automatically reduce the capacity of the bias table, thereby releasing some system resources, reducing power consumption and improving resource utilization.

[0115] Furthermore, after receiving the CXL.mem request, the device processor dynamically adjusts the bias state in combination with the current state of CXL.cache, including the following steps:

[0116] Read the current state of CXL.cache;

[0117] Parse the bias state requirement in the CXL.mem request;

[0118] Dynamically adjust the bias state according to demand to ensure the consistency of CXL.cache.

[0119] like Figure 7 As shown, in this embodiment, the granularity of each bias state is 4KB, and the data size of the bias state is 16GB, so the bias table size required for the DRAM cache is 16GB / 4KB. The bias cache consists of 4 flag SRAMs and 4 bias state SRAMs, each flag SRAM holds 512 flags, each bias state SRAM holds 512 bias state groups, and each bias state group contains 32 bias states.

[0120] like Figure 8 As shown in the figure, the bias cache uses the least used strategy to replace the flag bit. The cache can accommodate a total of 8KB of bias state, realizing the mapping from 8Mb to 8KB. Each group of SRAM efficiently stores the bias state data in the corresponding SRAM through the mapping relationship. Specifically, the cache is selected according to the access frequency of the flag bit during replacement to ensure efficient use of the cache.

[0121] like Fig. 9 The figure shows the specific process of the device handling bias state switching in hardware autonomous mode. After receiving the CXL.mem request, the device first determines whether the bias state needs to be switched. If switching is required, the device processor fills the corresponding request information into the command queue, and then executes the bias state change operation through the command parsing module. The entire process is completed autonomously by the device without the intervention of the host, ensuring fast response under high load conditions.

[0122] like Fig.10 As shown in the figure, the host sends a bias state modification request to the device processor through the OpenCL API. After receiving the request, the device processor writes the bias state modification command to the command queue and executes the state change through the command parsing module. This process ensures accurate switching of the bias state when the host needs to participate, thereby maintaining the consistency and stability of the system.

[0123] Example 2

[0124] Detailed description of the embodiments

[0125] 1. CXL bias management mechanism with soft and hard coordination

[0126] The following functions are achieved through the cooperation of register configuration and device processor:

[0127] In software-assisted mode, the host sends bias state modification requests to the device through the OpenCL API.

[0128] In hardware autonomous mode, the device automatically determines and adjusts the bias state by requesting the parsing module and combining the current state of CXL.cache.

[0129] This combination of software and hardware can flexibly select the optimal bias management mode according to different scenarios, thereby improving the system's response speed and performance.

[0130] 2. Efficient management of bias cache

[0131] The bias cache is introduced, and the bias table data in the cache is managed through the least used strategy. The bias cache control module specifically includes the following functions:

[0132] The bias buffer consists of 4 flag SRAMs and 4 bias state SRAMs, each SRAM accommodating 512 flag or bias state groups respectively.

[0133] The biased cache control module can monitor the cache hits in real time and perform cache replacement according to the least used strategy to ensure efficient use of the cache.

[0134] This optimization solution can significantly reduce the delay when switching bias states, especially in high-concurrency access scenarios, and can maintain the high performance of the system.

[0135] 3. Dynamic mode switching

[0136] According to the current workload and system status, the device of the present invention can automatically select hardware autonomous mode or software assisted mode for bias management. The dynamic mode switching mechanism includes:

[0137] When the host detects that the bias state needs to be changed, the software-assisted mode is preferred for management.

[0138] When the host does not intervene in bias management, the device autonomously adjusts its status based on the CXL.mem request.

[0139] This intelligent switching capability enables the system to operate efficiently in different scenarios, avoiding the performance bottleneck caused by a single mode.

[0140] 4. Efficient request parsing and command processing

[0141] By optimizing the collaboration between the request parsing module and the command parsing module, the overall efficiency of bias management is improved. Its main functions include:

[0142] The request parsing module parses the CXL.mem request to determine whether the request involves a change in the bias state.

[0143] When the bias state needs to be changed, the device processor fills the request information into the command queue, and the command parsing module performs the specific bias state switching operation.

[0144] This design effectively reduces the burden on the processor and improves the system's processing speed and responsiveness.

[0145] Specific implementation of the software and hardware combined management mechanism:

[0146] The software-hard combination management mechanism of the present invention is intended to flexibly switch the bias management mode according to the current state and load of the system. Specifically, after receiving the CXL.mem request, the device processor first determines the current system load and the state of CXL.cache:

[0147] Under high load or multi-tasking conditions, the system automatically switches to hardware autonomous mode, where the device processor autonomously parses requests and adjusts bias states, thereby reducing host involvement and system latency.

[0148] Under low load or specific application requirements, the system switches to software-assisted mode. The host actively manages the bias state through the OpenCL API and sends specific bias state modification requests to the device processor to ensure precise control and efficient management.

[0149] The core of this dynamic switching mechanism is to automatically select the optimal bias management strategy based on real-time feedback from the system through close cooperation between the register module and the device processor, ensuring that the system can maintain optimal performance under different loads.

[0150] In summary, the present invention proposes a CXL bias management method based on cache software and hardware coordination, aiming to optimize cache consistency and memory management in computer systems. The technical solution realizes intelligent switching and dynamic adjustment of bias state by combining software-assisted and hardware-autonomous bias management mechanisms. Specifically, when parsing a CXL.mem request, the system can decide whether to adjust the bias state according to the current CXL.cache state, and use the bias cache control module and the minimum usage strategy to improve the cache hit rate and reduce response delay. In addition, through the management method of combining software and hardware, the system can significantly improve the response speed and efficiency under high load and complex scenarios, while reducing system power consumption and optimizing resource utilization.

[0151] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0152] Any process or method description in the flow chart or otherwise described herein can be understood to represent a module, fragment or portion of a code including one or more executable instructions for implementing the steps of a specific logical function or process. And the scope of the preferred embodiment of the present application includes other implementations, in which the functions may not be performed in the order shown or discussed, including in a substantially simultaneous manner or in a reverse order according to the functions involved.

[0153] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A CXL bias management method based on cache soft-hard coordination, characterized in that: The method comprises the following steps: Providing a CXL device, the device comprising a CXL.mem interface, a CXL.cache interface, and a bias management component; The CXL.mem request is parsed by the request parsing module. When the received CXL.mem request meets the requirements for modifying the bias state, the information of the CXL.mem request is filled into the command queue; The device processor determines whether the bias state needs to be adjusted based on the content of the CXL.mem request and the current state of CXL.cache. If adjustment is required, the bias conversion request is filled in the command queue; The command parsing module parses the offset conversion request in the command queue and generates corresponding operation instructions; The bias cache control module executes data access of the bias table according to the operation instructions generated by the command parsing module, manages the hits of the bias cache, and performs cache replacement through the least used strategy LRU; When changing the bias state, determine whether the current bias cache hits. If it hits, directly update the bias table in the cache and return completion information; if it does not hit, perform cache replacement and write the new bias state to the internal data cache DRAM.

2. The CXL bias management method based on cache soft-hard coordination according to claim 1, characterized in that: The bias management component is implemented by the following steps: The CXL.mem request is parsed by the request parsing module, and when the received CXL.mem request meets the requirements for modifying the bias state, the request information is written into the CXL.mem request queue; In software-assisted mode, the device processor receives the bias conversion request sent by the host and writes it into the command queue; in hardware autonomous mode, the device processor determines whether the bias state needs to be adjusted based on the CXL.mem request parsed by the request parsing module and the current state of CXL.cache. If so, the bias conversion request is written into the command queue; The command parsing module parses the bias conversion commands generated by the device processor and converts these commands into operation instructions for the bias state; The data access operation of the biased table is executed through the biased cache control module, and the hit and replacement of the biased cache are managed through the least used strategy LRU; When the bias cache hits, the bias status in the bias table is directly updated; When the bias cache misses, a cache replacement is performed and the new bias state is written to the cache and the internal data cache; Through the register module, configure the hardware functions of the device and return the hardware status as needed; Cache the request information filled in by the request parsing module in the CXL.mem request queue, and store the bias conversion request and bias state read and write request generated by the device processor; The write command queue is used to cache the write command and related data issued by the device processor; the read command queue is used to cache the read command issued by the device processor; The cache data returned by the biased cache control module is cached through the read data queue to complete the data read operation.

3. The CXL bias management method based on cache soft-hard coordination according to claim 1, characterized in that: The bias state switching method in software-assisted mode in CXL.mem request processing includes the following operations: The host sends a bias conversion request to the device processor through the OpenCL API; After receiving the bias conversion request, the device processor fills it into the command queue and determines whether the bias state needs to be changed based on the current state of CXL.cache; The device processor sends the bias state modification request to the command queue, and parses the command through the command parsing module to perform the bias state change operation; After receiving the bias state modification command sent by the host through the OpenCL API, the device processor executes the update of the bias state.

4. The CXL bias management method based on cache soft-hard coordination according to claim 1, characterized in that: The specific operations performed by the offset cache control module include: Determine whether the bias cache is enabled; If enabled, check whether the cache hits; If the cache hits, the offset table in the cache is directly updated and the completion information is returned; If the cache misses, a cache replacement is performed and a new bias state is written to the internal data cache DRAM; If the bias cache is not enabled, the new bias state is written directly to the internal data cache DRAM.

5. The CXL bias management method based on cache soft-hard coordination according to claim 1, characterized in that: The bias state switching method in hardware autonomous mode during CXL.mem request processing includes the following operations: Parse the request from the CXL.mem interface to determine whether the request involves a change in the bias state; If the CXL.mem request needs to change the bias state, the request information is filled into the CXL.mem request queue of the command queue; The device processor checks the CXL.mem request queue and obtains the CXL.mem request that needs to be processed; Determine whether the bias state needs to be changed based on the current CXL.cache state and the information in the CXL.mem request; If the bias state needs to be changed, the write command is filled into the command queue, and the command parsing module executes the bias state change.

6. The CXL bias management method based on cache soft-hard coordination according to claim 1, characterized in that: The bias buffer of the CXL device includes 4 flag SRAMs and 4 bias state SRAMs, each flag SRAM accommodates 512 flags, and each bias state SRAM accommodates 512 bias state groups.

7. The CXL bias management method based on cache soft-hard coordination according to claim 1, characterized in that: The biased cache adopts a cache replacement mechanism based on a least-used strategy (LRU) to retain frequently accessed data, so as to improve the hit rate of the biased cache.

8. The CXL bias management method based on cache soft-hard coordination according to claim 7, characterized in that: The least used strategy LRU of the biased cache includes the following operations: Use 4 access counters to monitor the hit status of 4 sets of caches; If a hit occurs, the corresponding access counter is incremented by 1. At this time, the corresponding bias state exists in the cache and can be used directly; If there is a miss, the sizes of the four access counters are compared, the bias state corresponding to the request is moved from the internal data cache DRAM to the corresponding cache, and the current access counter is cleared.

9. The CXL bias management method based on cache soft-hard coordination according to claim 1, characterized in that: The device processor optimizes performance in different application scenarios by dynamically adjusting the size of the offset table, including: Under high load conditions, the capacity of the bias table is increased; under low load conditions, the capacity of the bias table is reduced; the adjustment of the bias table size is completed autonomously by hardware.

10. The CXL bias management method based on cache soft-hard coordination according to claim 1, characterized in that: After receiving the CXL.mem request, the device processor determines whether the bias state needs to be adjusted based on the current state of CXL.cache. If adjustment is required, the bias conversion request is filled into the command queue, and the bias state change is executed through the command parsing module to ensure the consistency of CXL.mem.

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