Agile development method and system of software defined chip

Abstract

The invention discloses an agile development method and system for a software-defined chip, and the method comprises the steps: obtaining a predefined design space which comprises a predefined hardware design space and a predefined software design space, the hardware design space comprises a design space of a calculation unit, and the software design space comprises a design space of a calculation unit; all the computing units use an ordered data stream scheme and asynchronous data stream transmission, and the computing units comprise computing units specially used for supporting cyclic variable control and generation; obtaining a target application program, a software design requirement and a hardware design requirement of a target field input by a user; determining actual design space parameters corresponding to the target application program from a predefined design space through demand analysis; and performing design space exploration in the actual design space parameters to obtain optimal actual design space parameters, and generating software codes and hardware codes of the target application program. According to the invention, low power consumption and high energy efficiency can be realized, and various complex calculation modes can be flexibly supported.

Description

Technical Field

[0001] The present invention relates to the field of agile development technology, and in particular to an agile development method and system for software-defined chips. Background Art

[0002] This section is intended to provide a background or context to the embodiments of the invention recited in the claims. No admission is made that the description herein is prior art by inclusion in this section.

[0003] Today, the rapid development of artificial intelligence, robotics, digital signal processing, bioinformatics, and aerospace systems is constrained by the slowdown in technology scaling, and ultra-low power (ULP) processors with sufficient computing power are urgently needed. Software-defined chips (SDC), represented by coarse-grained reconfigurable architecture (CGRA), have solid competitive advantages in high energy efficiency, post-manufacturing flexibility, and low non-recurring engineering (NRE) costs. The SDC architecture is expected to achieve various ASIC-like functions while still maintaining high efficiency relative to general-purpose processors. In the above fields, the popularity of ULP sensing and edge devices will further amplify the competitive advantage of SDC.

[0004] In these fields, machine learning applications show significant parallelism; dynamic programming and mathematical optimization problems usually involve a large number of control statements such as branches; digital signal processing applications such as Cholesky decomposition and fast Fourier transform (FFT) show significant inductive data dependencies. In different scenarios, applications will show completely different computing and memory access patterns. Therefore, different fields usually require different domain-specific architectures to achieve high energy efficiency.

[0005] However, even the SDC architecture that can support a wide range of computing operations cannot meet the diverse needs of all fields. The computing array, memory interface, and interconnection topology of SDC are all changeable. When designing a customized SDC accelerator for each application field, domain expertise is often required. Manually designing the most ideal hardware structure consumes a lot of time and manpower. Manually designing all fields is unrealistic. Therefore, some researchers have proposed a design space exploration (DSE) framework to automatically search for the best software scheduling and circuit hardware structure design under different performance or area targets.

[0006] However, the existing DSE framework has room for improvement in terms of low power consumption and high energy efficiency, both in terms of architecture and software optimization. In addition, the efficiency and quality of the compiler are also bottlenecks that limit the exploration capabilities of the existing DSE framework. Therefore, there is currently a lack of an agile development solution for ultra-low power software-defined chips that pursues the goals of low power consumption and high energy efficiency, and allows SDC to flexibly support various complex computing modes. Summary of the invention

[0007] The embodiment of the present invention provides an agile development method for a software-defined chip, which can achieve low power consumption and high energy efficiency and can flexibly support various complex computing modes. The method includes:

[0008] Obtaining a predefined design space, the predefined design space comprising a predefined hardware design space and a predefined software design space, the hardware design space comprising a design space of computing units, all computing units using an ordered data flow scheme and asynchronous data flow emission, the computing units comprising computing units dedicated to supporting loop variable control and generation and general computing units;

[0009] Obtaining a target application in a target field input by a user, and software design requirements and hardware design requirements of the target application;

[0010] Analyzing the software design requirements and hardware design requirements of the target application, and determining actual design space parameters corresponding to the target application from a predefined design space;

[0011] Conduct design space exploration in the actual design space parameters to obtain the optimal actual design space parameters;

[0012] Generate software and hardware code for the target application based on the optimal actual design space parameters.

[0013] The embodiment of the present invention further provides an agile development system for software-defined chips, which can achieve low power consumption and high energy efficiency and can flexibly support various complex computing modes. The system includes:

[0014] A predefined design space is used to obtain a predefined design space, wherein the predefined design space includes a predefined hardware design space and a predefined software design space, wherein the hardware design space includes a design space of computing units, all of which use an ordered data flow scheme and asynchronous data flow emission, and wherein the computing units include computing units dedicated to supporting loop variable control and generation and general computing units;

[0015] A user input module, used to obtain a target application in a target field of user input, as well as software design requirements and hardware design requirements of the target application;

[0016] An actual design space determination module is used to analyze the software design requirements and hardware design requirements of the target application and determine actual design space parameters corresponding to the target application from a predefined design space;

[0017] A design space exploration module is used to perform design space exploration in actual design space parameters to obtain the optimal actual design space parameters;

[0018] The software and hardware code generation module is used to generate software code and hardware code of the target application based on the optimal actual design space parameters.

[0019] An embodiment of the present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the agile development method of the above-mentioned software-defined chip when executing the computer program.

[0020] An embodiment of the present invention also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the agile development method of the above-mentioned software-defined chip.

[0021] An embodiment of the present invention also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the agile development method of the above-mentioned software-defined chip.

[0022] In an embodiment of the present invention, a predefined design space is obtained, wherein the predefined design space includes a predefined hardware design space and a predefined software design space, wherein the hardware design space includes a design space of computing units, wherein all computing units use an ordered data flow scheme and asynchronous data flow transmission, and wherein the computing units include computing units dedicated to supporting loop variable control and generation and general computing units; a target application in a target domain input by a user, and software design requirements and hardware design requirements of the target application are obtained; the software design requirements and hardware design requirements of the target application are analyzed, and actual design space parameters corresponding to the target application are determined from the predefined design space; design space exploration is performed in the actual design space parameters to obtain optimal actual design space parameters; and software code and hardware code of the target application are generated based on the optimal actual design space parameters. In the above embodiment, all computing units use an ordered data flow scheme and asynchronous data flow transmission, so that each computing unit starts computing when data arrives, and the data does not have to rely on and wait for global clock transmission, thereby improving efficiency and reducing energy consumption; the computing units include computing units dedicated to supporting loop variable control and generation and general computing units, which makes it possible to map more parts of the target application to the software-defined chip architecture at the same time, reducing communication overhead with the host; and the concurrency of irregular loops can be improved through multiple computing units dedicated to supporting loop variable control and generation, so that the software code and hardware code of the target application can flexibly support various complex computing modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0024] Figure 1 Flow chart of an agile development method for software-defined chips in an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a control data flow for dense vector multiplication extraction in an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of a control data flow for sparse vector multiplication extraction in an embodiment of the present invention;

[0027] Figure 4 Schematic diagram of the mapping and exploration process when implementing two design space explorations in the present invention;

[0028] Figure 5 Schematic diagram of an agile development system for software-defined chips in an embodiment of the present invention;

[0029] Figure 6 Schematic diagram of a computer device in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0031] First, the terms involved in the embodiments of the present invention are explained.

[0032] CPU, central processing unit, central processing unit;

[0033] ASIC, application specific integrated circuit, application specific integrated circuit;

[0034] FPGA, field programmable gate array, field programmable logic gate array;

[0035] TPU, tensor processing unit, tensor processing unit;

[0036] DSP, digital signal processor, digital signal processor;

[0037] GPU, graphics processing unit, graphics processor;

[0038] SDC, software-defined chip, software-defined chip;

[0039] CGRA, coarse-grained reconfigurable architecture, coarse-grained reconfigurable processing architecture;

[0040] LLVM, low level virtual machine, low level virtual machine compilation framework;

[0041] PE, processing element, processing unit;

[0042] DFG, data flow graph, data flow graph;

[0043] GR, global register, global register;

[0044] ILP, integer linear programming, integer linear programming;

[0045] MCTS, monte-carlo tree search, Monte Carlo tree search;

[0046] NRE, non-recurring engineering, non-recurring engineering;

[0047] DSE, design space exploration, design space exploration;

[0048] ULP, ultra-low power, ultra-low power consumption;

[0049] MIMD, Multiple Instruction, Multiple Data, multiple instructions and multiple data;

[0050] SIMD, Single Instruction, Multiple Data, single instruction multiple data.

[0051] The inventors found that traditional hardware-software co-design methods usually start with extracting software features and then derive hardware parameters based on preconceived assumptions about best practices. DSAGEN and OverGen only support simple control flows with streaming memory access, and only accelerate regular loops, which weakens their effectiveness. AURORA and ASAP consider loop optimization at the software level (such as loop blocking, loop unrolling, etc.), but lack systematic code optimization solutions for irregular control flows. Overall, these frameworks do not target ultra-low power space architectures, nor do they have methods to effectively support program patterns with complex control flows and memory accesses.

[0052] To achieve this goal, the embodiment of the present invention defines a relatively complete software and hardware design space, and uses agile development, namely, a design space exploration (DSE) framework to generate a domain-specific ULP SDC for applications in any domain.

[0053] Figure 1 The flowchart of the agile development method of the software-defined chip in the embodiment of the present invention includes:

[0054] Step 101, obtaining a predefined design space, wherein the predefined design space includes a predefined hardware design space and a predefined software design space, wherein the hardware design space includes a design space of computing units, wherein all computing units use an ordered data flow scheme and asynchronous data flow emission, and wherein the computing units include computing units dedicated to supporting loop variable control and generation and general computing units;

[0055] Step 102, obtaining a target application in a target field input by a user, and software design requirements and hardware design requirements of the target application;

[0056] Step 103, analyzing the software design requirements and hardware design requirements of the target application, and determining actual design space parameters corresponding to the target application from the predefined design space;

[0057] Step 104, performing design space exploration in the actual design space parameters to obtain the optimal actual design space parameters;

[0058] Step 105 , generating software code and hardware code of the target application based on the optimal actual design space parameters.

[0059] In an embodiment of the present invention, all computing units use an ordered data flow scheme and asynchronous data flow transmission, so that each computing unit starts computing when data arrives, and the data does not have to rely on and wait for global clock transmission, thereby improving efficiency and reducing energy consumption; the computing units include computing units dedicated to supporting loop variable control and generation and general computing units, which makes it possible to simultaneously map more parts of the target application to the software-defined chip architecture, reducing communication overhead with the host; and the concurrency of irregular loops can be improved through multiple computing units dedicated to supporting loop variable control and generation, so that the software code and hardware code of the target application finally obtained can flexibly support various complex computing modes.

[0060] Different from the existing DSE framework, the method proposed in the embodiment of the present invention defines a comprehensive design space. The special point is that by integrating SIMD into the MIMD SDC architecture, the bandwidth required for instruction fetching and the cache space of instructions can be reduced, while reducing control overhead and providing overall energy efficiency. The limited interconnection between the PE units of SIMD reduces the overall number of interconnections and makes mapping easier. The nature of MIMD also ensures the flexibility of the entire SDC architecture. Facing possible irregular control, a dedicated control flow unit is introduced in agile development, that is, a computing unit dedicated to supporting loop variable control and generation. An ordered-dataflow scheme and asynchronous data flow emission are used to handle variable delays and reduce the power consumption overhead of clock trees and synchronous circuits. The compiler in the method automatically optimizes and maps so that various programs can be executed with optimal performance. Design space exploration (DSE) involves the above considerations, searches for PE functions, memory interfaces, and interconnection topologies (i.e., the design space defined above), explores the design space based on the computing and memory modes of the assembly to meet different requirements, and finally generates software code and hardware code corresponding to FPGA prototype or ASIC implementation.

[0061] Table 1 is an example of a predefined design space in an embodiment of the present invention.

[0062] Table 1

[0063]

[0064]

[0065] Table 1 is introduced in detail below.

[0066] In one embodiment, the design space of the computing unit includes precision parameters, supported computing function parameters, whether to support time domain extension mapping parameters, whether to support the number of functional units inside the SIMD computing unit, whether to support loop variable control and generation parameters, whether to support predicate parameters and input and output size parameters;

[0067] The precision parameter is used to indicate the precision that the computing unit can achieve;

[0068] The supported computing function parameter is used to indicate the computing functions supported by the computing unit;

[0069] The parameter "whether to support time domain extended mapping" is used to indicate whether the computing unit supports time domain extended mapping;

[0070] The parameters of whether SIMD is supported and the number of functional units in the computing unit are used to indicate whether the computing unit supports SIMD and the number of functional units when SIMD is supported;

[0071] The parameter whether loop variable control and generation is supported is used to indicate whether the computation unit is dedicated to handling loop variable control and generation;

[0072] The parameter whether to support predicates is used to indicate whether the computing unit supports predicates;

[0073] The input and output size parameters are used to indicate the input size and output size of the computational unit.

[0074] In the above embodiment, whether SIMD is supported and the number of functional units in the computing unit, if SIMD is supported, it means that SIMD is integrated into the MIMD SDC architecture: the original software-defined chip can generally be regarded as a MIMD architecture, that is, each PE performs different tasks autonomously; on this basis, the embodiment of the present invention adds SIMD inside some PEs, that is, there are multiple FUs (function units) inside the PE that are controlled by the same instruction to process different data. In this way, the bandwidth required for instruction fetching and the cache space for instructions can be reduced, while reducing control overhead and providing overall energy efficiency. The SIMD PE unit is equivalent to packing the original multiple PEs into one, which reduces the overall number of interconnections and makes mapping easier.

[0075] In the parameter "Whether to support loop variable control and generation", if the value is "support loop variable control and generation", the computing unit is a dedicated control flow unit: a special PE that processes loop statements. For example, loop statements / instructions such as for(i=0;i<10;i++) are executed in a single PE, and the PE outputs loop variables according to the instruction for other PEs to use in subsequent calculations. The advantage of this is that more parts of the application to be executed can be mapped to the SDC at the same time, reducing the communication overhead with the host; and the concurrency of irregular loops can be improved through multiple such units.

[0076] In the embodiment of the present invention, all PEs use ordered-dataflow and asynchronous data flow transmission. Ordered-dataflow means that each PE starts computing when data arrives. Asynchronous data flow transmission: Each PE is equipped with an output FIFO and supports handshake signals (ready-valid), so that data does not have to rely on and wait for global clock transmission, which improves efficiency and reduces energy consumption.

[0077] In one embodiment, the hardware design space also includes a design space of a memory access unit;

[0078] The design space of the memory access unit includes input and output size parameters, whether to support scatter and gather parameters;

[0079] The input and output size parameters are used to indicate the input size and output size of the memory access unit;

[0080] The parameter "whether to support scatter and gather" is used to indicate whether the memory access unit supports scatter and whether to support gather.

[0081] In one embodiment, the hardware design space also includes a design space for an on-chip storage scratchpad cache;

[0082] The design space of the on-chip storage note cache includes whether it is distributed, the number of ports, and the size.

[0083] The distributed parameter is used to indicate whether the on-chip storage note cache is a distributed structure;

[0084] The port number parameter is used to indicate the number of ports for on-chip storage of scratchpad cache;

[0085] The size parameter is used to indicate the size of the on-chip memory scratchpad cache.

[0086] In one embodiment, the hardware design space also includes a design space of an interconnect unit;

[0087] The design space of the interconnection unit includes whether it is a crossbar switch parameter, the number of ports parameter, the cache size parameter, whether it is point-to-point parameter, and the parameters of the computing units that can be connected;

[0088] The whether it is a cross switch parameter is used to indicate whether the interconnect unit is a cross switch;

[0089] The port number parameter is used to indicate the number of ports of the interconnection unit;

[0090] The cache size parameter is used to indicate the cache size of the interconnect unit;

[0091] The whether point-to-point parameter is used to indicate whether the interconnection unit is a point-to-point structure;

[0092] The connectable computing unit parameter is used to indicate the computing units that the interconnect unit can connect to.

[0093] In one embodiment, the software design space includes a design space for loops;

[0094] The design space of the loop includes expansion coefficient parameters, block coefficient parameters, whether to merge irregular loop parameters and vectorization coefficient parameters;

[0095] The expansion factor parameter is used to indicate the expansion factor of the loop;

[0096] The block coefficient parameter is used to indicate the block coefficient of the loop;

[0097] The parameter of whether to merge irregular cycles is used to indicate whether to merge irregular cycles;

[0098] The vectorization coefficient parameter is used to indicate the vectorization coefficient of the loop.

[0099] In one embodiment, analyzing the software design requirements and hardware design requirements of the target application to determine the actual design space parameters corresponding to the target application from the predefined design space includes:

[0100] According to software design requirements, loop parameter extraction and loop dependency analysis are performed on the target application program to determine actual software design space parameters for searching from a predefined software design space;

[0101] According to the hardware design requirements, actual hardware design space parameters for searching are determined from the predefined hardware design space.

[0102] In one embodiment, in the actual design space parameters, design space exploration is performed to obtain the optimal actual design space parameters, including:

[0103] Determine the software-defined chip architecture template based on the maximum number of operators of the target application and use it as a starting point for exploration;

[0104] Take the software-defined chip architecture template as the current software-defined chip architecture, start from the exploration starting point, and repeat the following steps until the new software-defined chip architecture converges, and take the current actual design space parameters as the optimal actual design space parameters:

[0105] A simulated annealing algorithm is used to search for actual hardware design space parameters, and the searched actual hardware design space parameters are applied to the current software-defined chip architecture to obtain a new software-defined chip architecture;

[0106] Optimize the actual software design space parameters through the compiler, apply the optimized actual software design space parameters to the target application to obtain the optimized target application, map the optimized target application to the new software-defined chip architecture to obtain the mapping result;

[0107] When the mapping is successful, an evaluation model is used to evaluate the evaluation indicator value of the new software-defined chip architecture;

[0108] Recording the current actual hardware design space parameters and the actual software design space parameters as the current actual design space parameters;

[0109] Determine whether the evaluation index values ​​of the new software-defined chip architecture converge. If not, use the new software-defined chip architecture as the current software-defined chip architecture.

[0110] In the above embodiment, according to the maximum number of operators N of the target application, the software-defined chip architecture template is determined as Architecture, and then add PE and interconnection according to application mapping.

[0111] If the evaluation index values ​​of the new software-defined chip architecture do not converge, when using the simulated annealing algorithm to search the actual hardware design space parameters, priority is given to changing the actual hardware design space parameters that cause the bottleneck, where the bottleneck refers to the poorer value in the evaluation index values ​​of the new software-defined chip architecture. The evaluation index values ​​include power consumption, performance, and area. The power consumption and area are directly estimated by adding the basic units, and the performance uses the mapping results to estimate the total number of cycles.

[0112] For example, if the area gap is large, then the actual hardware design space parameters that increase the area are changed first. For example, if the performance does not meet the requirements, the number of FUs in the PE is increased, or the capacity of the on-chip memory is increased. Each time a search point is selected, a mapping is performed. If the mapping fails, the PE and interconnection are increased accordingly.

[0113] The design goals for target applications in different fields are different, such as performance priority in high-performance computing and energy efficiency priority in embedded fields. The search target value can be pre-defined before design.

[0114] In the above embodiment, when mapping fails, the design space exploration needs to be performed again.

[0115] When judging whether convergence has occurred, if the priority evaluation indicator value among all evaluation indicator values ​​has converged, then it is determined that the evaluation indicator value of the new software-defined chip architecture has converged.

[0116] In one embodiment, generating software code and hardware code of a target application based on optimal actual design space parameters includes:

[0117] Parameterized implementation of hardware programming language for each hardware module of the software-defined chip architecture after design space exploration;

[0118] Generate hardware code based on the optimal actual design space parameters and parameterized implementation of hardware programming language;

[0119] According to the loop parameters and mapping results in the optimal actual design space parameters, a binary file corresponding to the software code that can be run in the hardware code implementation is output.

[0120] A specific example is given below to illustrate the application of the agile development method of software-defined chips.

[0121] For example, the target applications include dense vector multiplication and sparse vector multiplication, and the corresponding extracted control data flows are as follows: Figure 2 As shown and Figure 3 shown.

[0122] The above target application is a single-layer loop. If it is a multi-layer loop, each for statement can be abstracted as a for operator separately, added to the CDFG, and mapped to a PE that supports loop variable generation in subsequent mapping.

[0123] When exploring the design space, the starting point is an empty 3×3 structure. Figure 4 Schematic diagram of the mapping and exploration process when implementing two design space explorations in the present invention, see Figure 4 , using point-to-point interconnection, first try to map target application 1, and then add PE and interconnection in sequence. Then try to map target application 2, and further add PE and interconnection. At the same time, determine the parameters of the on-chip storage scratchpad according to the memory access operator. When the design space exploration is completed, the optimal actual design space parameters can be obtained, and finally the software code and hardware code of the target application are generated.

[0124] An embodiment of the present invention also proposes an agile development system for software-defined chips, the principle of which is similar to the agile development method for software-defined chips, and will not be repeated here.

[0125] Figure 5The schematic diagram of the agile development system of the software-defined chip in the embodiment of the present invention includes:

[0126] Predefined design space 501, used to obtain a predefined design space, the predefined design space includes a predefined hardware design space and a predefined software design space, the hardware design space includes a design space of computing units, all computing units use an ordered data flow scheme and asynchronous data flow emission, the computing units include computing units dedicated to supporting loop variable control and generation and general computing units;

[0127] A user input module 502, used to obtain a target application in a target field input by a user, and software design requirements and hardware design requirements of the target application;

[0128] An actual design space determination module 503 is used to analyze the software design requirements and hardware design requirements of the target application and determine actual design space parameters corresponding to the target application from a predefined design space;

[0129] A design space exploration module 504 is used to perform design space exploration in actual design space parameters to obtain optimal actual design space parameters;

[0130] The software and hardware code generation module 505 is used to generate software code and hardware code of the target application based on the optimal actual design space parameters.

[0131] In one embodiment, the actual design space determination module 503 is used to: perform loop parameter extraction and loop dependency analysis on the target application according to software design requirements, and determine actual software design space parameters for searching from the predefined software design space;

[0132] According to the hardware design requirements, actual hardware design space parameters for searching are determined from the predefined hardware design space.

[0133] In one embodiment, the design space exploration module 504 is used to: determine a software-defined chip architecture template based on the maximum number of operators of the target application and use it as a starting point for exploration;

[0134] Take the software-defined chip architecture template as the current software-defined chip architecture, start from the exploration starting point, and repeat the following steps until the new software-defined chip architecture converges, and take the current actual design space parameters as the optimal actual design space parameters:

[0135] A simulated annealing algorithm is used to search for actual hardware design space parameters, and the searched actual hardware design space parameters are applied to the current software-defined chip architecture to obtain a new software-defined chip architecture;

[0136] Optimize the actual software design space parameters through the compiler, apply the optimized actual software design space parameters to the target application to obtain the optimized target application, map the optimized target application to the new software-defined chip architecture to obtain the mapping result;

[0137] When the mapping is successful, an evaluation model is used to evaluate the evaluation indicator value of the new software-defined chip architecture;

[0138] Recording the current actual hardware design space parameters and the actual software design space parameters as the current actual design space parameters;

[0139] Determine whether the evaluation index values ​​of the new software-defined chip architecture converge. If not, use the new software-defined chip architecture as the current software-defined chip architecture.

[0140] In one embodiment, the software and hardware code generation module 505 is used to: perform parameterized implementation of the hardware programming language of each hardware module of the software-defined chip architecture after the design space exploration is completed;

[0141] Generate hardware code based on the optimal actual design space parameters and parameterized implementation of hardware programming language;

[0142] According to the loop parameters and mapping results in the optimal actual design space parameters, a binary file corresponding to the software code that can be run in the hardware code implementation is output.

[0143] In summary, in the method and system proposed in the embodiments of the present invention, a predefined design space is obtained, wherein the predefined design space includes a predefined hardware design space and a predefined software design space, wherein the hardware design space includes a design space of computing units, all computing units use an ordered data flow scheme and asynchronous data flow transmission, and the computing units include computing units dedicated to supporting loop variable control and generation and general computing units; a target application in a target field input by a user, as well as software design requirements and hardware design requirements of the target application are obtained; the software design requirements and hardware design requirements of the target application are analyzed, and actual design space parameters corresponding to the target application are determined from the predefined design space; design space exploration is performed in the actual design space parameters to obtain optimal actual design space parameters; and software code and hardware code of the target application are generated based on the optimal actual design space parameters. In the above embodiment, all computing units use an ordered data flow scheme and asynchronous data flow transmission, so that each computing unit starts computing when data arrives, and the data does not have to rely on and wait for global clock transmission, thereby improving efficiency and reducing energy consumption; the computing units include computing units dedicated to supporting loop variable control and generation and general computing units, which makes it possible to map more parts of the target application to the software-defined chip architecture at the same time, reducing communication overhead with the host; and the concurrency of irregular loops can be improved through multiple computing units dedicated to supporting loop variable control and generation, so that the software code and hardware code of the target application can flexibly support various complex computing modes.

[0144] An embodiment of the present invention further provides a computer device, Figure 6 This is a schematic diagram of a computer device in an embodiment of the present invention. The computer device 600 includes a memory 610, a processor 620, and a computer program 630 stored in the memory 610 and executable on the processor 620. When the processor 620 executes the computer program 630, the agile development method of the software-defined chip is implemented.

[0145] An embodiment of the present invention also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the agile development method of the above-mentioned software-defined chip.

[0146] An embodiment of the present invention also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the agile development method of the above-mentioned software-defined chip.

[0147] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0148] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0149] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0150] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0151] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An agile development method for software-defined chips, characterized in that: include: Obtaining a predefined design space, the predefined design space comprising a predefined hardware design space and a predefined software design space, the hardware design space comprising a design space of computing units, all computing units using an ordered data flow scheme and asynchronous data flow emission, the computing units comprising computing units dedicated to supporting loop variable control and generation and general computing units; Obtaining a target application in a target field input by a user, and software design requirements and hardware design requirements of the target application; Analyzing the software design requirements and hardware design requirements of the target application, and determining actual design space parameters corresponding to the target application from a predefined design space; Conduct design space exploration in the actual design space parameters to obtain the optimal actual design space parameters; Generate software and hardware code for the target application based on the optimal actual design space parameters.

2. The method according to claim 1, characterized in that The design space of the computing unit includes precision parameters, supported computing function parameters, whether to support time domain extension mapping parameters, whether to support SIMD and the number of functional units inside the computing unit parameters, whether to support loop variable control and generation parameters, whether to support predicate parameters and input and output size parameters; The precision parameter is used to indicate the precision that the computing unit can achieve; The supported computing function parameter is used to indicate the computing functions supported by the computing unit; The parameter "whether to support time domain extended mapping" is used to indicate whether the computing unit supports time domain extended mapping; The parameters of whether SIMD is supported and the number of functional units in the computing unit are used to indicate whether the computing unit supports SIMD and the number of functional units when SIMD is supported; The parameter whether loop variable control and generation is supported is used to indicate whether the computation unit is dedicated to handling loop variable control and generation; The parameter whether to support predicates is used to indicate whether the computing unit supports predicates; The input and output size parameters are used to indicate the input size and output size of the computational unit.

3. The method according to claim 1, characterized in that The hardware design space also includes a design space for a memory access unit; The design space of the memory access unit includes input and output size parameters, whether to support scatter and gather parameters; The input and output size parameters are used to indicate the input size and output size of the memory access unit; The parameter "whether to support scatter and gather" is used to indicate whether the memory access unit supports scatter and whether to support gather.

4. The method according to claim 1, characterized in that The hardware design space also includes a design space for an on-chip storage scratchpad cache; The design space of the on-chip storage note cache includes whether it is distributed, the number of ports, and the size. The distributed parameter is used to indicate whether the on-chip storage note cache is a distributed structure; The port number parameter is used to indicate the number of ports for on-chip storage of scratchpad cache; The size parameter is used to indicate the size of the on-chip memory scratchpad cache.

5. The method according to claim 1, characterized in that The hardware design space also includes a design space for interconnection units; The design space of the interconnection unit includes whether it is a crossbar switch parameter, the number of ports parameter, the cache size parameter, whether it is point-to-point parameter, and the parameters of the computing units that can be connected; The whether it is a cross switch parameter is used to indicate whether the interconnect unit is a cross switch; The port number parameter is used to indicate the number of ports of the interconnection unit; The cache size parameter is used to indicate the cache size of the interconnect unit; The whether point-to-point parameter is used to indicate whether the interconnection unit is a point-to-point structure; The connectable computing unit parameter is used to indicate the computing units that the interconnect unit can connect to.

6. The method according to claim 1, characterized in that The software design space includes the design space of loops; The design space of the loop includes expansion coefficient parameters, block coefficient parameters, whether to merge irregular loop parameters and vectorization coefficient parameters; The expansion factor parameter is used to indicate the expansion factor of the loop; The block coefficient parameter is used to indicate the block coefficient of the loop; The parameter of whether to merge irregular cycles is used to indicate whether to merge irregular cycles; The vectorization coefficient parameter is used to indicate the vectorization coefficient of the loop.

7. The method according to claim 1, characterized in that Analyze the software design requirements and hardware design requirements of the target application, and determine the actual design space parameters corresponding to the target application from the predefined design space, including: According to software design requirements, loop parameter extraction and loop dependency analysis are performed on the target application program to determine actual software design space parameters for searching from a predefined software design space; According to the hardware design requirements, actual hardware design space parameters for searching are determined from the predefined hardware design space.

8. The method according to claim 7, characterized in that In the actual design space parameters, design space exploration is performed to obtain the optimal actual design space parameters, including: Determine the software-defined chip architecture template based on the maximum number of operators of the target application and use it as a starting point for exploration; Take the software-defined chip architecture template as the current software-defined chip architecture, start from the exploration starting point, and repeat the following steps until the new software-defined chip architecture converges, and take the current actual design space parameters as the optimal actual design space parameters: A simulated annealing algorithm is used to search for actual hardware design space parameters, and the searched actual hardware design space parameters are applied to the current software-defined chip architecture to obtain a new software-defined chip architecture; Optimize the actual software design space parameters through the compiler, apply the optimized actual software design space parameters to the target application to obtain the optimized target application, map the optimized target application to the new software-defined chip architecture to obtain the mapping result; When the mapping is successful, an evaluation model is used to evaluate the evaluation indicator value of the new software-defined chip architecture; Recording the current actual hardware design space parameters and the actual software design space parameters as the current actual design space parameters; Determine whether the evaluation index values ​​of the new software-defined chip architecture converge. If not, use the new software-defined chip architecture as the current software-defined chip architecture.

9. The method according to claim 8, characterized in that Generate software and hardware code for the target application based on the optimal actual design space parameters, including: Parameterized implementation of hardware programming language for each hardware module of the software-defined chip architecture after design space exploration; Generate hardware code based on the optimal actual design space parameters and parameterized implementation of hardware programming language; According to the loop parameters and mapping results in the optimal actual design space parameters, a binary file corresponding to the software code that can be run in the hardware code implementation is output.

10. An agile development system for software-defined chips, characterized in that: include: A predefined design space is used to obtain a predefined design space, wherein the predefined design space includes a predefined hardware design space and a predefined software design space, wherein the hardware design space includes a design space of computing units, all of which use an ordered data flow scheme and asynchronous data flow emission, and wherein the computing units include computing units dedicated to supporting loop variable control and generation and general computing units; A user input module, used to obtain a target application in a target field of user input, as well as software design requirements and hardware design requirements of the target application; An actual design space determination module is used to analyze the software design requirements and hardware design requirements of the target application and determine actual design space parameters corresponding to the target application from a predefined design space; A design space exploration module is used to perform design space exploration in actual design space parameters to obtain the optimal actual design space parameters; The software and hardware code generation module is used to generate software code and hardware code of the target application based on the optimal actual design space parameters.

11. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 9 is implemented.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

13. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

Images