Data processing method, device, electronic device and computer readable storage medium

Abstract

The embodiment of the present invention provides a data processing method, device, electronic device and computer-readable storage medium, which relate to the technical field of solid-state hard disks. The method uses an address cache table that only records physical addresses to realize the mapping relationship between logical addresses and physical addresses. Compared with the prior art that uses an L2P table to record the mapping relationship between logical addresses and physical addresses, the method effectively reduces space occupancy and reduces write amplification, thereby reducing the impact on host services.

Description

Technical Field

[0001] The present invention relates to the technical field of solid-state hard disks, and in particular to a data processing method, device, electronic device and computer-readable storage medium. Background Art

[0002] Solid State Drives (SSDs) usually use NAND flash memory as the storage medium. Since NAND flash memory cannot be overwritten, it needs to be erased before writing again. Therefore, there is a serious write amplification problem in the data storage process of SSDs. Summary of the invention

[0003] In view of this, an object of the present invention is to provide a data processing method, device, electronic device and computer-readable storage medium, which can reduce space occupation and reduce write amplification.

[0004] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0005] In a first aspect, the present invention provides a data processing method, the method comprising:

[0006] Get the logical address of the data to be processed;

[0007] Allocating a physical address for the data to be processed, and writing the data to be processed into a NAND flash memory according to the physical address;

[0008] The offset position of the physical address in the address cache table is determined according to the logical address, and the physical address is saved in the offset position; the logical address and the offset position correspond one to one.

[0009] In an optional embodiment, the method further comprises:

[0010] An incremental log is updated according to the logical address and the physical address; the incremental log is used to record the corresponding relationship between the logical address and the physical address;

[0011] When the data volume of the incremental log reaches a preset value, the partition index to be written is determined according to the partition index written last time; each of the partition indexes corresponds to address data of a preset size in the address cache table;

[0012] Determine target address data from the address cache table according to the partition index to be written;

[0013] Generate the partition data to be written according to the target address data and the partition index to be written;

[0014] The incremental log and the partition data to be written are written into the NAND flash memory.

[0015] In an optional implementation manner, generating the partition data to be written according to the target address data and the partition index to be written includes:

[0016] The partition index to be written is written into the metadata area corresponding to the first physical address in the target address data to obtain the partition data to be written.

[0017] In an optional implementation manner, writing the incremental log and the partition data to be written into a NAND flash memory includes:

[0018] Determine a target block from the NAND flash memory according to a partition index corresponding to the partition data to be written;

[0019] Determine the data offset and log offset according to the partition index corresponding to the partition data to be written; the data offset represents the starting address of the target block where the partition data to be written is stored; the log offset represents the starting address of the target block where the incremental log is stored;

[0020] The partition data to be written is written into the target block according to the data offset, and the incremental log is written into the target block according to the log offset.

[0021] In an optional embodiment, the method further comprises:

[0022] When power is restored, read the data of each partition and the corresponding incremental log in the NAND flash memory;

[0023] Restoring the address cache table according to all the partition data;

[0024] The address cache table is updated using the incremental log.

[0025] In an optional implementation manner, the restoring the address cache table according to all the partition data includes:

[0026] Determine the location of the partition data in the address cache table according to the partition index corresponding to the partition data;

[0027] The physical addresses in the partition data are restored to the address cache table according to the positions.

[0028] In an optional implementation manner, the updating the address cache table using the incremental log includes:

[0029] Reading the correspondence between each logical address and physical address in each incremental log in sequence according to the order in which the incremental logs are created;

[0030] According to the logical address in the corresponding relationship, obtaining the corresponding physical address in the address cache table;

[0031] When the physical address in the corresponding relationship is different from the corresponding physical address in the address cache table, the corresponding physical address in the address cache table is updated to the physical address in the corresponding relationship.

[0032] In a second aspect, the present invention provides a data processing device, the device comprising:

[0033] A processing module, used to obtain the logical address of the data to be processed;

[0034] A storage module, used for allocating a physical address for the data to be processed, and writing the data to be processed into a NAND flash memory according to the physical address;

[0035] An update module is used to determine the offset position of the physical address in the address cache table according to the logical address, and save the physical address to the offset position; the logical address corresponds to the offset position one by one.

[0036] In a third aspect, the present invention provides an electronic device, comprising a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the data processing method described in any of the aforementioned embodiments.

[0037] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements a data processing method as described in any one of the aforementioned embodiments.

[0038] Compared with the prior art, the data processing method, device, electronic device and computer-readable storage medium provided in the embodiments of the present invention use an address cache table that only records physical addresses to implement the mapping relationship between logical addresses and physical addresses. Compared with the prior art that uses an L2P table to record the mapping relationship between logical addresses and physical addresses, it effectively reduces space occupancy and write amplification, thereby reducing the impact on host services.

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 A schematic flow chart of a data processing method provided by an embodiment of the present invention is shown.

[0042] Figure 2 A schematic diagram of an address cache table provided by an embodiment of the present invention is shown.

[0043] Figure 3 Another flow chart of the data processing method provided by the embodiment of the present invention is shown.

[0044] Figure 4 A schematic diagram of partition data provided by an embodiment of the present invention is shown.

[0045] Figure 5 A schematic diagram of storing partition data and incremental logs in a NAND flash memory provided by an embodiment of the present invention is shown.

[0046] Figure 6 Another flow chart of the data processing method provided by the embodiment of the present invention is shown.

[0047] Figure 7 A block diagram of a data processing device provided by an embodiment of the present invention is shown.

[0048] Figure 8 A block diagram of an electronic device provided by an embodiment of the present invention is shown.

[0049] Icon: 100 - electronic device; 110 - memory; 120 - processor; 130 - communication module; 200 - data processing device; 201 - processing module; 202 - storage module; 203 - update module. DETAILED DESCRIPTION

[0050] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0051] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0052] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0053] The NAND flash memory of the SSD does not support overwriting. When writing again, it needs to be erased before writing. When the host sends a read or write request to the SSD, it needs to obtain the corresponding physical address according to the logical address carried in the read or write request, and read or store user data by accessing the physical address.

[0054] The inventors have found that the current existing technology uses a logical address to physical address (L2P) table to record the mapping relationship between the logical address of user data and the physical address in the NAND flash memory. The L2P table records the logical address and physical address corresponding to each 4K data. As the capacity increases, the space requirement of the L2P table also increases, which will further aggravate the power-on recovery time and write amplification problems.

[0055] Among them, write amplification is a property associated with flash memory and solid-state drives, which means that when performing a write operation, the amount of data written to the solid-state drive is much greater than the actual amount of data written. Due to the continuous update of the L2P table, the number of bad blocks caused by erasing the NAND flash memory will increase, reducing the service life of the SSD.

[0056] Based on this, the data processing method and device provided in the embodiments of the present invention use an address cache table that only records physical addresses to implement the mapping relationship between logical addresses and physical addresses. Compared with the prior art that uses the L2P table to record the mapping relationship between logical addresses and physical addresses, it effectively reduces space occupancy and write amplification, thereby reducing the impact on host services.

[0057] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0058] See also Figure 1 , Figure 1 A flow chart of a data processing method provided by an embodiment of the present invention is shown. The method should include the following steps:

[0059] Step S10, obtaining the logical address of the data to be processed.

[0060] In a solid-state drive, data is usually stored in blocks of fixed size. Each block is assigned a logical address, which is continuous. The host can access the data through the logical address. When the host sends a write request, the write request carries the data to be processed and the logical address. The write request is parsed to obtain the data to be processed and the logical address.

[0061] Step S20, allocating a physical address for the data to be processed, and writing the data to be processed into the NAND flash memory according to the physical address.

[0062] In an embodiment of the present invention, the physical address is the location where data is actually stored on the NAND flash memory, and each physical address corresponds to a storage unit of a fixed size. When a write request is received, an idle physical address is allocated to the data to be processed, triggering the operation of writing the data to be processed to the storage unit corresponding to the physical address. Usually, each data to be processed is not written to the storage unit immediately, but the data to be processed is accumulated, and when a certain amount of data is reached, it is written together to the storage unit corresponding to the physical address in the NAND flash memory. For example, when the amount of data sent by the host reaches a program unit (Program Unit, abbreviated as: PU), each data to be processed is written to the NAND flash memory together.

[0063] Step S30, determine the offset position of the physical address in the address cache table according to the logical address, and save the physical address to the offset position; the logical address and the offset position correspond one to one. In the embodiment of the present invention, the address cache table is used to manage the mapping relationship between the logical address and the physical address, and the logical address is used as the subscript index of the address cache table to uniquely identify the offset position of each physical address in the address cache table. It can be understood that the address cache table is equivalent to an array, the logical address is equivalent to the array subscript, and the physical address is equivalent to the array element.

[0064] As a possible implementation, Figure 2For example, assume that the address cache table is used to record the physical addresses corresponding to 1000 logical addresses. The logical addresses are continuous and numbered from 0 to 999. For example, the logical address of the address to be processed is 1, and the newly allocated physical address is a. Then, according to the logical address 1, the second offset position storing the physical address is found in the address cache table, and the physical address a is saved to the offset position.

[0065] In summary, the data processing method provided by the embodiment of the present invention obtains the logical address of the data to be processed; allocates a physical address to the data to be processed, and writes the data to be processed into the NAND flash memory according to the physical address; determines the offset position of the physical address in the address cache table according to the logical address, and saves the physical address to the offset position; the logical address corresponds to the offset position one by one. The embodiment of the present invention uses an address cache table that only records physical addresses to realize the mapping relationship between logical addresses and physical addresses. Compared with the prior art that uses the L2P table to record the mapping relationship between logical addresses and physical addresses, it effectively reduces space occupancy and reduces write amplification, thereby reducing the impact on host services.

[0066] Optionally, a possible implementation method is provided below for how to write the address cache table into NAND flash memory. Figure 3 , the data processing method further comprises the following steps:

[0067] Step S40, updating the incremental log according to the logical address and the physical address; the incremental log is used to record the corresponding relationship between the logical address and the physical address.

[0068] In the embodiment of the present invention, the latest update of the cache information table is recorded by using the incremental log. When the host sends a write request, the logical address and physical address corresponding to the write request are saved as a record in the incremental log to ensure that the incremental log can record the complete update process of the cache information table.

[0069] It should be noted that the size of the logical address and the physical address are usually the same. For example, if it is set to 4 bytes, the physical address in the address cache table is 4 bytes, and the corresponding relationship in the incremental log is 8 bytes. For each additional correspondence between the logical address and the physical address in the incremental log, the amount of data in the incremental log will increase by 8 bytes. As the host continues to send write requests, the amount of data in the incremental log will increase accordingly.

[0070] Step S50, when the data volume of the incremental log reaches a preset value, the partition index to be written is determined according to the partition index written last time; each partition index corresponds to address data of a preset size in the address cache table.

[0071] In the embodiment of the present invention, a reasonable preset value can be set according to the difference of the solid state drive. If the preset value is too large, the incremental log will be too large, and it will take a long time to write it into the NAND flash memory when the power is off, and it may not be written completely, resulting in data loss. If the preset value is too large, it will cause the address data in the incremental log and address cache table to be written frequently, affecting the read and write performance of the solid state drive.

[0072] As a possible implementation, for example, the preset value can be set to 96K bytes. When the amount of data in the incremental log reaches the preset value of 96K, a new incremental log is created, and the new incremental log is used to record the subsequent updates of the address cache table. The incremental log in the cache that reaches the preset value of 96K is written to the NAND flash memory. At the same time, the physical address in the address cache table is divided into multiple address data according to the preset value, and an address data is obtained as the incremental log is written to the NAND flash memory.

[0073] In order to ensure that the address data in the address cache table can be written into the NAND flash memory in sequence, it is necessary to record the partition index corresponding to the address data last written into the NAND flash memory, that is, the partition index last written. The partition index to be written is obtained by taking the sum of the partition index last written and 1 modulo the total number of partition indexes.

[0074] For example, if the partition index corresponding to the address data written to the NAND flash memory last time is 0, then when the incremental log reaches the preset value, the partition index to be written is 1. Therefore, when the incremental log reaches the preset value next time, the partition index written last time is 1, and so on, until the partition index written last time is the largest partition index, and the partition index to be written starts from 0 again.

[0075] It is worth mentioning that, assuming a 4T SSD, the size of the physical address is 4 bytes, the size of the address cache table is 4G, and the ratio between the size of the address cache table and the size of the SSD is 1:1000. Assuming that 96K of address data corresponds to one partition, a 4G address cache table corresponds to 43 partitions.

[0076] Step S60, determining target address data from the address cache table according to the partition index to be written.

[0077] In the embodiment of the present invention, in order to facilitate the segmentation of the address cache table to disk (ie, writing to NAND flash memory), the address cache table may be divided into multiple address data according to a preset size, each address data including multiple physical addresses. The preset size may be a preset value.

[0078] As a possible implementation, assuming that the preset value is 96K and the address cache table is 960K, the 240,000 physical addresses in the address cache table are divided into 10 address data according to the preset value, and each address data contains 24,000 physical addresses. The partition index is used to uniquely identify the address data, and the partition index is globally uniformly encoded, and the partition index can be from 0 to 9. For example, if the partition index to be written is 1, it is necessary to obtain the second address data from the address cache table as the target address data, that is, the physical address corresponding to the logical address 24,000 to 47,999.

[0079] Step S70, generating the partition data to be written according to the target address data and the partition index to be written.

[0080] Step S80, writing the incremental log and the partition data to be written into the NAND flash memory.

[0081] In an embodiment of the present invention, in order to restore the address data stored in the NAND flash memory to the corresponding position in the address cache table during power-on recovery, the target address data and the partition index to be written are written into the NAND flash memory together in the form of partition data to be written.

[0082] It can be seen that in the embodiment of the present invention, when the host sends a write request to the solid-state hard disk, the address cache table will be updated in real time, while the partition data in the NAND flash memory is not updated in real time. Only when the data volume of the incremental log reaches the preset value, the partition data is generated according to the partition index and address data, and the incremental log and partition data are written to the NAND flash memory. By adding a partition index to the partition data to mark the position of each partition data in the address cache table, the partition index can be used to quickly and accurately restore the address cache table when power is restored, and the impact on the host business is reduced by partitioning the disk.

[0083] It should be noted that when the host sends a read request to the SSD, the physical address is quickly obtained by searching the address cache table, and the data is read through the physical address, which effectively reduces write amplification while ensuring data access efficiency.

[0084] Optionally, a possible implementation method is provided below for how to generate partition data to be written. Figure 3 The sub-steps of step S70 may include:

[0085] The partition index to be written is written into the metadata area corresponding to the first physical address in the target address data to obtain the partition data to be written.

[0086] In an embodiment of the present invention, the target address data is divided according to a preset division threshold to obtain a plurality of regional data, each of which corresponds to a storage unit, and the storage unit includes a data area and a metadata area, the data area is used to store the regional data, and the metadata area is used to store the metadata corresponding to the regional data. The metadata corresponding to the regional data where the first physical address in the target address data is located is generated according to the partition index to be written, and the generated metadata is written into the corresponding metadata area, the metadata corresponding to other regional data is set to an initial value, and the partition data to be written is generated according to each regional data and the corresponding metadata.

[0087] As a possible implementation, assume that the target address data of 96K is divided according to the preset division threshold of 4K, and 24 4K regional data are obtained. The metadata corresponding to each regional data is set to the initial value, the metadata corresponding to the first physical address in the target address data is determined as the target metadata, and the partition index to be written is written into the target metadata. In the order of writing the regional data first and then writing the corresponding metadata, all the regional data and all the metadata are used to generate the partition data to be written, such as Figure 4 shown.

[0088] That is, the storage unit includes a data area and a metadata area, the data area is used to store target address data, metadata is generated according to the partition index to be written, and the metadata is stored in the metadata area. The partition data to be written includes the target address data and the corresponding metadata.

[0089] Optionally, a possible implementation method is provided below for how to write the incremental log and the partition data to be written into the NAND flash memory. Figure 3 The sub-steps of step S80 may include:

[0090] The target block is determined from the NAND flash memory according to the partition index corresponding to the partition data to be written; the data offset and the log offset are determined according to the partition index corresponding to the partition data to be written; the data offset represents the starting address of the target block where the partition data to be written is stored; the log offset represents the starting address of the target block where the incremental log is stored; the partition data to be written is written into the target block according to the data offset, and the incremental log is written into the target block according to the log offset.

[0091] In the embodiment of the present invention, since NAND flash memory does not support overwriting, it can only be written again after erasing. Therefore, in order to fully store the address data in the address cache table, at least 1.5 times the storage blocks of the address data need to be applied to store all the address data, that is, all the physical addresses in the address cache table.

[0092] As a possible implementation, assume that the address cache table is divided into 10 address data when it is written to the NAND flash memory, and the address data corresponds to the partition data one by one. In order to facilitate erasure, the partition data and incremental log written to the NAND flash memory are stored in the same storage block. Assume that each storage block can store 5 partition data and 5 incremental logs, and 10 partition data and corresponding 10 incremental logs have been written to storage block 1 and storage block 2 in sequence, as shown in FIG. Figure 5 shown.

[0093] Assuming that the partition index corresponding to the partition data to be written this time is 0, since both storage block 1 and storage block 2 are valid and have been written, storage block 3 is determined as the target block. In an embodiment of the present invention, the partition data is stored in the first half of the storage block, and the incremental log is stored in the second half of the storage block. The starting address of the target block is determined as the data offset according to the partition index 0, and the position of the target block starting address offset by 5 partition data sizes is determined as the log offset. The partition data is written to the target block starting from the data offset, and the incremental log is written to the target block starting from the log offset, and the partition data 0 and incremental log 10 in storage block 3 are set to be valid, and the partition data 0 and incremental log 0 in storage block 1 are set to be invalid.

[0094] It is worth mentioning that when storage block 3 is full, the 5 partition data and 5 incremental logs in storage block 3 are all set to valid, while the 5 partition data and 5 incremental logs in storage block 1 are all set to invalid. When all partition data and incremental logs in storage block 1 are invalid, storage block 1 can be erased, and storage block 1 can be used to cyclically store newly written partition data and incremental logs. Compared with storing partition data and incremental logs in different storage blocks, using the same storage block to store partition data and corresponding incremental logs can effectively save one storage block.

[0095] It should be noted that when power is off abnormally, all physical addresses in the address cache table cannot be written into the NAND flash memory. The power-off protection strategy is used to write the incremental log in the cache into the NAND flash memory so that the address cache table can be restored using the incremental log when power is restored.

[0096] Optionally, the following provides a possible implementation method for restoring the address cache table when power is turned on. Figure 6 , the data processing method further comprises the following steps:

[0097] Step S90, when power is restored, read the data of each partition and the corresponding incremental log in the NAND flash memory.

[0098] Step S100, restoring the address cache table according to all partition data.

[0099] Step S110: update the address cache table using the incremental log.

[0100] In the embodiment of the present invention, during the power-on recovery process, the incremental log corresponding to the valid partition data in the NAND flash memory is read. Figure 5 , read partition data 1 to partition data 4 and corresponding incremental logs 1 to incremental log 4 in storage block 1, read partition data 5 to partition data 9 and corresponding incremental logs 5 to incremental log 9 in storage block 2, and read partition data 0 and corresponding incremental log 10 in storage block 3. Use 10 partition data to build an address cache table, and then use each incremental log to verify the physical address in the address cache table to update the address cache table, thereby ensuring the accuracy of the address cache table.

[0101] It can be seen that the embodiment of the present invention quickly restores the address cache table based on the partition data corresponding to the partition index, avoids restoring the address cache table in sequence according to the correspondence between the logical address and the physical address, and effectively improves the recovery efficiency of the address cache table, thereby ensuring the rapid provision of host services.

[0102] Optionally, a possible implementation method is provided below on how to use partition data to restore the address cache table. Figure 6 The sub-steps of step S100 may include:

[0103] The location of the partition data in the address cache table is determined according to the partition index corresponding to the partition data; and the physical address in the partition data is restored to the address cache table according to the location.

[0104] In the embodiment of the present invention, continue with Figure 4 For example, according to the order of regional data and metadata, the partition index corresponding to the partition data is obtained, the position of the partition data in the address cache table is found according to the partition index, and the 24 regional data in the partition data are read in sequence. Starting from the position, the 24 regional data are copied to the address cache table in sequence, so as to use all physical addresses recorded in the NAND flash memory to restore the address cache table in the cache.

[0105] Optionally, a possible implementation method is provided below on how to update the address cache table using the incremental log. Figure 6 The sub-steps of step S110 may include:

[0106] In accordance with the order in which the incremental logs are created, the correspondence between each logical address and physical address in each incremental log is read in turn; according to the logical address in the correspondence, the corresponding physical address in the address cache table is obtained; when the physical address in the correspondence is different from the corresponding physical address in the address cache table, the corresponding physical address in the address cache table is updated to the physical address in the correspondence.

[0107] In an embodiment of the present invention, each incremental log records the latest update status of the address cache table corresponding to each disk cycle. The incremental logs are read in order from the creation time of the incremental logs, and the correspondence between each logical address and physical address in the incremental logs is read one by one. The offset position in the address cache table is determined according to the logical address in the correspondence. If the physical address in the correspondence is the same as the physical address in the offset position, the next correspondence is read to continue the comparison. If the physical address in the correspondence is not the same as the physical address in the offset position, the physical address in the correspondence is used to update the corresponding physical address in the address cache table.

[0108] Based on the same inventive concept, the embodiment of the present invention further provides a data processing device, the basic principle and technical effects of which are the same as those of the above embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the above embodiment.

[0109] See also Figure 7 , Figure 7 A block diagram of a data processing device 200 provided by an embodiment of the present invention is shown. The data processing device 200 includes a processing module 201 , a storage module 202 and an updating module 203 .

[0110] Processing module 201, used to obtain the logical address of the data to be processed;

[0111] The storage module 202 is used to allocate physical addresses to the data to be processed and write the data to be processed into the NAND flash memory according to the physical addresses;

[0112] The updating module 203 is used to determine the offset position of the physical address in the address cache table according to the logical address, and save the physical address to the offset position; the logical address and the offset position correspond one to one.

[0113] To sum up, the data processing device provided in an embodiment of the present invention uses an address cache table that only records physical addresses to implement the mapping relationship between logical addresses and physical addresses. Compared with the prior art that uses an L2P table to record the mapping relationship between logical addresses and physical addresses, it effectively reduces space occupancy and reduces write amplification, thereby reducing the impact on host services.

[0114] Optionally, the update module 203 is further used to update the incremental log according to the logical address and the physical address; the incremental log is used to record the corresponding relationship between the logical address and the physical address.

[0115] The storage module 202 is also used to determine the partition index to be written according to the partition index written last time when the data volume of the incremental log reaches a preset value; each partition index corresponds to address data of a preset size in the address cache table; determine the target address data from the address cache table according to the partition index to be written; generate the partition data to be written according to the target address data and the partition index to be written; and write the incremental log and the partition data to be written into the NAND flash memory.

[0116] Optionally, the storage module 202 is specifically configured to write the partition index to be written into a metadata area corresponding to the first physical address in the target address data to obtain the partition data to be written.

[0117] Optionally, the storage module 202 is specifically used to determine the target block from the NAND flash memory according to the partition index corresponding to the partition data to be written; determine the data offset and the log offset according to the partition index corresponding to the partition data to be written; the data offset represents that the partition data to be written is stored at the starting address of the target block; the log offset represents that the incremental log is stored at the starting address of the target block; the partition data to be written is written into the target block according to the data offset, and the incremental log is written into the target block according to the log offset.

[0118] Optionally, the update module 203 is further used to read each partition data and the corresponding incremental log in the NAND flash memory when power is restored; restore the address cache table according to all partition data; and update the address cache table using the incremental log.

[0119] Optionally, the update module 203 is specifically configured to determine the position of the partition data in the address cache table according to the partition index corresponding to the partition data; and restore the physical address in the partition data to the address cache table according to the position.

[0120] Optionally, the update module 203 is specifically used to read the correspondence between each logical address and physical address in each incremental log in sequence according to the order in which the incremental logs are created; obtain the corresponding physical address in the address cache table according to the logical address in the correspondence; when the physical address in the correspondence is different from the corresponding physical address in the address cache table, update the corresponding physical address in the address cache table to the physical address in the correspondence.

[0121] See also Figure 8 , Figure 8A block diagram of an electronic device 100 provided in an embodiment of the present invention. The electronic device 100 may be any device having a data processing function, such as a personal computer, a laptop computer, a server, etc. The electronic device 100 includes a memory 110, a processor 120, and a communication module 130. The memory 110, the processor 120, and the communication module 130 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components may be electrically connected to each other via one or more communication buses or signal lines.

[0122] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0123] The processor 120 is used to read / write data or programs stored in the memory 110 and execute corresponding functions. For example, when the computer program stored in the memory 110 is executed by the processor 120, the data processing method disclosed in the above embodiments can be implemented.

[0124] The communication module 130 is used to establish a communication connection between the electronic device 100 and other communication terminals through a network, and to send and receive data through the network.

[0125] It should be understood that Figure 8 The structure shown is only a schematic diagram of the structure of the electronic device 100. The electronic device 100 may also include Figure 8 More or fewer components as shown, or with Figure 8 Different configurations are shown. Figure 8 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0126] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by the processor 120, the data processing method disclosed in the above embodiments is implemented.

[0127] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0128] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0129] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program codes.

[0130] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A data processing method, characterized in that: The method comprises: Get the logical address of the data to be processed; Allocating a physical address for the data to be processed, and writing the data to be processed into a NAND flash memory according to the physical address; Determine the offset position of the physical address in the address cache table according to the logical address, and save the physical address to the offset position; the logical address and the offset position correspond one to one; An incremental log is updated according to the logical address and the physical address; the incremental log is used to record the corresponding relationship between the logical address and the physical address; When the data volume of the incremental log reaches a preset value, the partition index to be written is determined according to the partition index written last time; each of the partition indexes corresponds to address data of a preset size in the address cache table; Determine target address data from the address cache table according to the partition index to be written; Generate the partition data to be written according to the target address data and the partition index to be written; The incremental log and the partition data to be written are written into the NAND flash memory.

2. The data processing method according to claim 1, characterized in that: The generating the partition data to be written according to the target address data and the partition index to be written comprises: The partition index to be written is written into the metadata area corresponding to the first physical address in the target address data to obtain the partition data to be written.

3. The data processing method according to claim 1, characterized in that: Writing the incremental log and the partition data to be written into the NAND flash memory includes: Determine a target block from the NAND flash memory according to a partition index corresponding to the partition data to be written; Determine the data offset and log offset according to the partition index corresponding to the partition data to be written; the data offset represents the starting address of the target block where the partition data to be written is stored; the log offset represents the starting address of the target block where the incremental log is stored; The partition data to be written is written into the target block according to the data offset, and the incremental log is written into the target block according to the log offset.

4. The data processing method according to claim 1, characterized in that: The method further comprises: When power is restored, read the data of each partition and the corresponding incremental log in the NAND flash memory; Restoring the address cache table according to all the partition data; The address cache table is updated using the incremental log.

5. The data processing method according to claim 4, characterized in that: The restoring the address cache table according to all the partition data includes: Determine the location of the partition data in the address cache table according to the partition index corresponding to the partition data; The physical addresses in the partition data are restored to the address cache table according to the positions.

6. The data processing method according to claim 4, characterized in that: The updating of the address cache table by using the incremental log includes: Reading the correspondence between each logical address and physical address in each incremental log in sequence according to the order in which the incremental logs are created; According to the logical address in the corresponding relationship, obtaining the corresponding physical address in the address cache table; When the physical address in the corresponding relationship is different from the corresponding physical address in the address cache table, the corresponding physical address in the address cache table is updated to the physical address in the corresponding relationship.

7. A data processing device, characterized in that: The device comprises: A processing module, used to obtain the logical address of the data to be processed; A storage module, used for allocating a physical address for the data to be processed, and writing the data to be processed into a NAND flash memory according to the physical address; An updating module, used for determining an offset position of the physical address in the address cache table according to the logical address, and saving the physical address to the offset position; the logical address corresponds to the offset position one by one; The update module is further used to update the incremental log according to the logical address and the physical address; the incremental log is used to record the corresponding relationship between the logical address and the physical address; The storage module is also used to determine the partition index to be written according to the partition index written last time when the data volume of the incremental log reaches a preset value; each partition index corresponds to address data of a preset size in the address cache table; determine the target address data from the address cache table according to the partition index to be written; generate the partition data to be written according to the target address data and the partition index to be written; and write the incremental log and the partition data to be written into a NAND flash memory.

8. An electronic device, characterized in that: It comprises a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the data processing method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data processing method according to any one of claims 1 to 6 is implemented.

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