System and method for testing memory

Abstract

This application provides a testing system and method for a memory. The testing system includes a testing device and a processor. The testing device uses a second voltage detection module to detect a second test voltage, thereby monitoring the time taken for the second memory cell to be interfered with by the first memory cell, and thus obtaining the operation time of the first memory cell. The first voltage detection module also detects a first test voltage at one end of a first address line, allowing the processor to calculate the interference energy generated by the first memory cell on the second memory cell during operation based on the voltages of the first and third address lines, the first test voltage, the resistance of the differential voltage generator, and the operation time of the first memory cell.

Description

Technical Field

[0001] This application generally relates to the field of electronic devices, and more specifically, to a test system and test method for memory. Background Technology

[0002] Various types of memory devices exist in the industry, including magnetic hard disks, random access memory, read-only memory, dynamic random access memory, synchronous dynamic random access memory, ferroelectric random access memory, magnetic random access memory, resistive random access memory, flash memory, phase change memory, and other memory devices.

[0003] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by logic "1" or logic "0". In other systems, more than two states can be stored. To access the stored information, components of the electronic device can read or sense the stored states in the memory device. To store information, components of the electronic device can write or program states into the memory device.

[0004] Different threshold voltage states of a memory can represent different logic states (e.g., "0" and "1"). For phase-change memory, when operating on a memory cell (including writing "0" and writing "1"), the large surge current and high reset current will cause significant thermal interference to the adjacent memory cells in the reset state. How to measure the interference energy generated by a memory cell on its adjacent memory cells is a major issue. Summary of the Invention

[0005] The purpose of this application is to provide a testing system and method for a memory, which aims to test the interference energy generated by a first memory cell on a second memory cell during operation.

[0006] In a first aspect, this application provides a testing system for a memory, the memory including a first memory cell and a second memory cell arranged adjacent to each other, a first address line connected to one end of the first memory cell, a second address line connected to one end of the second memory cell, and a third address line connected to the other ends of the first memory cell and the second memory cell; the testing system includes a testing device and a processor, the testing device including:

[0007] The voltage output interface includes a first voltage output interface, a second voltage output interface and a third voltage output interface. The first voltage output interface is used to connect to the first address line, one end of the second voltage output interface is used to connect to the second address line, and the third voltage output interface is used to connect to the third address line.

[0008] A differential pressure generator is connected to the first voltage output interface;

[0009] The voltage detection module includes a first voltage detection module and a second voltage detection module. The first voltage detection module is used to detect a first test voltage between the first voltage output interface and the differential voltage generator. The second voltage detection module is used to detect a second test voltage at the other end of the second voltage output interface.

[0010] The controller is configured to apply voltage to the first address line, the second address line, and the third address line through the voltage output interface until the second test voltage changes and the application of the voltage is stopped.

[0011] The processor is used to calculate the energy generated by the first memory cell based on the voltage of the first address line and the third address line, the first test voltage, the resistance of the differential voltage generator, and the operating time of the first memory cell.

[0012] In some embodiments, the testing apparatus further includes:

[0013] The first input terminal is connected to the differential pressure generator and is used to receive the write operation voltage applied by the controller;

[0014] The second input terminal is connected to the second voltage output interface and is used to receive the read operation voltage applied by the controller;

[0015] The third input terminal, connected to the third voltage output interface, is used to receive the turn-on voltage applied by the controller.

[0016] In some embodiments, the testing apparatus further includes:

[0017] A first selector switch is connected between the first input terminal and the differential pressure generator. When the first control terminal of the first selector switch receives a first voltage signal applied by the controller, the first selector switch is switched to the open state; when the first control terminal receives a second voltage signal applied by the controller, the first selector switch is switched to the closed state.

[0018] A second selector switch is connected between the second input terminal and the second voltage detection module. When the second control terminal of the second selector switch receives a third voltage signal applied by the controller, the second selector switch is switched to the open state; when the second control terminal receives a fourth voltage signal applied by the controller, the second selector switch is switched to the closed state.

[0019] Specifically, when the first selection switch is in the open state, the second selection switch is in the closed state, causing the first storage unit to perform a write operation; when the first selection switch is in the closed state, the second selection switch is in the open state, causing the second storage unit to perform a read operation.

[0020] In some embodiments, the testing apparatus further includes:

[0021] An oscilloscope, connected to the first voltage detection module and the second voltage detection module, is used to display the waveforms of the first test voltage and the second test voltage as a function of time.

[0022] In some embodiments, the differential pressure generator is connected between the first selection switch and the first voltage detection module.

[0023] In some embodiments, the processor includes:

[0024] The statistics module is used to count the number of times the first storage unit performs the write operation and the time of a single write operation when the second test voltage changes.

[0025] The first calculation module is used to calculate the voltage difference across the first storage unit based on the first test voltage and the voltage at the third input terminal.

[0026] The second calculation module is used to calculate the current value generated by the differential pressure generator;

[0027] The third calculation module is used to calculate the energy generated by the first storage unit based on the voltage difference, the current value, the time, and the number of times.

[0028] In some embodiments, the second computing module includes:

[0029] The first calculation unit is used to calculate the voltage difference between the voltage at the first input terminal and the first test voltage.

[0030] The second calculation unit is used to calculate the current value based on the voltage difference and the resistance value of the voltage difference generator.

[0031] In some embodiments, the memory further includes a third memory cell disposed adjacent to the second memory cell, a fourth address line connected to one end of the third memory cell, and the other end of the third memory cell connected to the third address line; the testing apparatus further includes:

[0032] A fourth voltage output interface, one end of which is connected to the fourth address line, and the other end of which is connected to the first input terminal;

[0033] A fourth selection switch is connected between the first input terminal and the fourth voltage output interface, and is connected in parallel with the first selection switch. The fourth control terminal of the fourth selection switch is connected to the first control terminal of the first selection switch.

[0034] One end of the differential pressure generator is connected to the first input terminal, and the other end of the differential pressure generator is connected to the first selection switch and the fourth selection switch, respectively.

[0035] Secondly, this application provides a method for testing a memory, applied to the testing system in any of the above embodiments, the testing method comprising:

[0036] Apply voltage to the first address line, the second address line, and the third address line until the second test voltage changes and then stop applying the voltage.

[0037] The energy generated by the first memory cell is calculated based on the voltages of the first address line and the third address line, the first test voltage, the resistance of the differential voltage generator, and the operating time of the first memory cell.

[0038] In some embodiments, the step of calculating the energy generated by the first memory cell based on the voltages of the first address line and the third address line, the first test voltage, the resistance of the differential voltage generator, and the operating time of the first memory cell includes:

[0039] The number of times the first storage unit performs the write operation and the time of each write operation are recorded when the second test voltage changes.

[0040] The voltage difference across the first memory cell is calculated based on the first test voltage and the voltage at the third input terminal.

[0041] Calculate the current value generated by the differential pressure generator;

[0042] The energy generated by the first storage unit is calculated based on the voltage difference, the current value, the time, and the number of times.

[0043] This application provides a testing system and method for a memory. The testing system includes a testing device and a processor. The testing device uses a second voltage detection module to detect a second test voltage, thereby monitoring the time taken for the second memory cell to be interfered with by the first memory cell, and thus obtaining the operation time of the first memory cell. The first voltage detection module also detects a first test voltage at one end of a first address line, allowing the processor to calculate the interference energy generated by the first memory cell on the second memory cell during operation based on the voltages of the first and third address lines, the first test voltage, the resistance of the differential voltage generator, and the operation time of the first memory cell. Attached Figure Description

[0044] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0045] Figure 1 This is a schematic diagram of the structure of a memory testing system provided in some embodiments of this application;

[0046] Figure 2 This is a schematic diagram of the structure of a memory testing apparatus provided in some embodiments of this application;

[0047] Figure 3 This is a waveform diagram showing the voltage change of the first and second input terminals over time, provided in some embodiments of this application.

[0048] Figure 4 This is a waveform diagram of the voltage at the third input terminal changing over time, provided in some embodiments of this application;

[0049] Figure 5 This is a waveform diagram of the voltage change of the first control terminal over time provided in some embodiments of this application;

[0050] Figure 6 This is a waveform diagram of the voltage change over time at the second control terminal provided in some embodiments of this application;

[0051] Figure 7 This is a waveform diagram of the voltage change of the third control terminal over time provided in some embodiments of this application;

[0052] Figure 8 This is a waveform diagram of the first test voltage changing over time provided in some embodiments of this application;

[0053] Figure 9 This is a waveform diagram of the second test voltage changing over time provided in some embodiments of this application;

[0054] Figure 10 This is a schematic diagram of the structure of a memory testing apparatus provided in some embodiments of this application;

[0055] Figure 11 This is a flowchart illustrating a memory testing method provided in some embodiments of this application;

[0056] Figure 12 This is a flowchart illustrating a memory testing method provided in some embodiments of this application;

[0057] Figure 13 This is a schematic flowchart illustrating the energy calculation process provided in some embodiments of this application. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0059] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.

[0060] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a range smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers, as well as one or more dielectric layers.

[0061] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation, the form, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0062] Please see Figure 1 and Figure 2 , Figure 1This is a schematic diagram of the structure of a memory testing system provided in some embodiments of this application. Figure 2 This is a schematic diagram of the structure of a memory testing apparatus provided in some embodiments of this application.

[0063] The memory 100 in this application may include at least one of phase-change memory and select-only memory. An important direction for optimizing this memory 100 is to increase the read windows for reset and set operations. The read windows for reset and set operations refer to the difference between the high threshold voltage of the reset state and the low threshold voltage of the set state. To increase the read windows for set and reset, it is necessary to increase the reset current of the memory cell during operation. However, high reset current and large inrush current can cause significant thermal interference to adjacent memory cells, thereby changing the threshold voltage or state of adjacent memory cells and directly affecting the size of the memory's read window. Therefore, measuring the energy generated when a memory cell operates and causes thermal interference to adjacent memory cells is extremely important. This interference energy can then be used to improve the memory structure or the operating voltage of the memory cells to reduce the impact on the read window.

[0064] The memory 100 in this application includes a first memory cell C1 and a second memory cell C2 arranged adjacent to each other, a first address line L1 connected to one end of the first memory cell C1, a second address line L2 connected to one end of the second memory cell C2, and a third address line L3 connected to the other end of the first memory cell C1 and the other end of the second memory cell C2.

[0065] In some embodiments, the third address line L3 can be a word line, and the first address line L1 and the second address line L2 can be bit lines; or the third address line L3 can be a bit line, and the first address line L1 and the second address line L2 can be word lines. The word lines and bit lines can be perpendicular and non-linear, with multiple memory cells connected between the word lines and bit lines, located at their intersections. Specifically, the first memory cell C1 is connected between the first address line L1 and the third address line L3, and the second memory cell C2 is connected between the second address line L2 and the third address line L3. Therefore, the first address line L1 and the third address line L3 are used to operate on the first memory cell C1, and the second address line L2 and the third address line L3 are used to operate on the second memory cell C2.

[0066] In some embodiments, the memory 100 is a select-only memory, and each memory cell may include a first electrode, a second electrode, and a select switch layer located between the first electrode and the second electrode.

[0067] like Figure 1 As shown, the test system 200 provided in this application includes a test device 20 and a processor 30. (As indicated...) Figure 2 As shown, the testing device 20 includes a voltage output interface 21, a differential pressure generator 22, a voltage detection module 23, and a controller 24.

[0068] The voltage output interface 21 includes a first voltage output interface 211, a second voltage output interface 212, and a third voltage output interface 213. The first voltage output interface 211 is used to connect to the first address line L1, one end of the second voltage output interface 212 is used to connect to the second address line L2, and the third voltage output interface 213 is used to connect to the third address line L3. Therefore, the first voltage output interface 211 transmits the operating voltage to the first address line L1, the second voltage output interface 212 transmits the operating voltage to the second address line L2, and the third voltage output interface 213 transmits the operating voltage to the third address line L3.

[0069] The differential voltage generator 22 is connected to the first voltage output interface 211 and is used to generate a voltage difference before the first voltage output interface 211. In some embodiments, the differential voltage generator 22 may include a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). The resistance value of the differential voltage generator 22 can be set according to actual needs. In some embodiments, the resistance value of the differential voltage generator 22 is 1 kOhm to 10 kOhm, for example, 5 kOhm.

[0070] The voltage detection module 23 includes a first voltage detection module 231 and a second voltage detection module 232. The first voltage detection module 231 is used to detect a first test voltage between the first voltage output interface 211 and the differential voltage generator 22; that is, the first voltage detection module 231 is connected between the first voltage output interface 211 and the differential voltage generator 22. The second voltage detection module 232 is used to detect a second test voltage at the other end of the second voltage output interface 212; that is, when the second voltage output interface 212 is connected to the second address line L2, the second voltage detection module 232 and the second address line L2 are located at opposite ends of the second voltage output interface 212.

[0071] The controller 24 applies voltage to the first address line L1, the second address line L2, and the third address line L3 through the voltage output interface 21 until the second test voltage changes, at which point the application of voltage stops. A change in the second test voltage indicates a change in the state of the second memory cell C2, for example, from a reset state to a set state. At this point, the detected second test voltage suddenly increases, forming a peak. After the controller 24 stops applying voltage, the voltages of the first address line L1, the second address line L2, and the third address line L3 are all 0, therefore the second test voltage also becomes 0.

[0072] The processor 30 is used to calculate the energy generated by the first storage unit C1 based on the voltages of the first address line L1 and the third address line L3, the first test voltage, the resistance value of the differential voltage generator 22, and the operating time of the first storage unit C1. The processor 30 can be connected to the testing device 20. When connected, the processor 30 can receive these parameters (including voltage, resistance, and time) from the testing device 20 and calculate the energy generated by the first storage unit C1. Alternatively, these parameters can be manually recorded and then input into the processor 30 for calculation.

[0073] In some embodiments, the test device 20 further includes a first input terminal 251 and a second input terminal 252. The first input terminal 251 is connected to the differential pressure generator 22 and is used to receive the write operation voltage applied by the controller 24. The second input terminal 252 is connected to the second voltage output interface 212 and is used to receive the read operation voltage applied by the controller 24.

[0074] In some embodiments, the test device 20 further includes a third input terminal 253, which is connected to a third voltage output interface 213 for receiving the turn-on voltage applied by the controller 24.

[0075] Please see Figure 3 and Figure 4 , Figure 3 This is a waveform diagram showing the voltage change over time at the first input terminal 251 and the second input terminal 252 provided in some embodiments of this application. Figure 4 This is a waveform diagram showing the voltage of the third input terminal 253 changing over time, provided in some embodiments of this application.

[0076] Specifically, controller 24 applies a write operation voltage V2 to the first input terminal 251, a read operation voltage V1 to the second input terminal 252, and a conduction voltage V3 to the third input terminal 253, thereby realizing a write operation on the first memory cell C1 and a read operation on the second memory cell C2. For example, the write operation voltage V2 is -3.6V, the read operation voltage V1 is -2.5V, and the conduction voltage V3 is 4-5V.

[0077] In some embodiments, the testing device 20 further includes a first selection switch 261, a second selection switch 262, and a third selection switch 263.

[0078] The first selection switch 261 is connected between the first input terminal 251 and the differential pressure generator 22. When the first control terminal 2611 of the first selection switch 261 receives the first voltage signal applied by the controller 24, the first selection switch 261 is switched to the open state; when the first control terminal 2611 receives the second voltage signal applied by the controller 24, the first selection switch 261 is switched to the closed state.

[0079] The second selection switch 262 is connected between the second input terminal 252 and the second voltage detection module 232. When the second control terminal 2621 of the second selection switch 262 receives a third voltage signal applied by the controller 24, the second selection switch 262 is switched to the open state; when the second control terminal 2621 receives a fourth voltage signal applied by the controller 24, the second selection switch 262 is switched to the closed state. Specifically, when the first selection switch 261 is in the open state, the second selection switch 262 is in the closed state, causing the first storage unit C1 to perform a write operation; when the first selection switch 261 is in the closed state, the second selection switch 262 is in the open state, causing the second storage unit C2 to perform a read operation.

[0080] The third selection switch 263 is connected between the third voltage output interface 213 and the third input terminal 253. When the third control terminal 2631 of the third selection switch 263 receives the fifth voltage signal applied by the controller 24, the third selection switch 263 is switched to the open state.

[0081] In some embodiments, the first selection switch 261, the second selection switch 262, and the third selection switch 263 can all be transistors, and the first control terminal 2611, the second control terminal 2621, and the third control terminal 2631 can all be gate terminals. Specifically, the voltage value of the first voltage signal is greater than the threshold voltage of the first selection switch 261, the voltage value of the second voltage signal is less than the threshold voltage of the first selection switch 261, the voltage value of the third voltage signal is greater than the threshold voltage of the second selection switch 262, the voltage value of the fourth voltage signal is less than the threshold voltage of the second selection switch 262, and the voltage value of the fifth voltage signal is greater than the threshold voltage of the third selection switch 263.

[0082] Please combine Figure 5-7 , Figure 5 This is a waveform diagram showing the voltage change over time at the first control terminal provided in some embodiments of this application. Figure 6 This is a waveform diagram showing the voltage change over time at the second control terminal provided in some embodiments of this application. Figure 7 This is a waveform diagram showing the voltage change over time of the third control terminal provided in some embodiments of this application.

[0083] like Figure 7 As shown, the fifth voltage signal V6 received by the third control terminal 2631 is 5.2V, and the third selection switch 263 is switched to the open state. Figure 5 As shown, the first control terminal 2611 receives a first voltage signal V4 of 5.2V and a second voltage signal V4 of 0V. When the third selection switch 263 is in the open state, the first control terminal 2611 receives the first voltage signal N times, indicating that the first memory cell C1 has performed N write operations. Figure 6 As shown, the second control terminal 2621 receives a third voltage signal V5 of 5.2V and a fourth voltage signal V5 of 0V. When the third selection switch 263 is in the open state, the second control terminal 2621 receives the third voltage signal N times, indicating that the second storage unit C2 has performed N read operations.

[0084] In this process, after the first storage unit C1 performs a write operation, the second storage unit C2 performs a read operation, and so on in a loop. During this process, the first voltage detection module 231 and the second voltage detection module 232 continuously detect the voltage at their respective locations until the second test voltage changes, at which point they stop applying voltage to the first address line L1, the second address line L2, and the third address line L3. The controller 24 can also stop applying voltage to the first control terminal 2611, the second control terminal 2621, and the third control terminal 2631.

[0085] In some embodiments, the testing device 20 further includes an oscilloscope (not shown), which is connected to the first voltage detection module 231 and the second voltage detection module 232, for displaying the waveforms of the first test voltage and the second test voltage changing over time.

[0086] Please see Figure 8 and Figure 9 , Figure 8 This is a waveform diagram showing the change of the first test voltage over time provided in some embodiments of this application. Figure 9 This is a waveform diagram of the second test voltage changing over time provided in some embodiments of this application.

[0087] like Figure 8 As shown, each time the first memory cell C1 performs a write operation, the first test voltage V7 will generate a peak. Figure 9 As shown, when the first storage cell C1 performs a write operation, the second storage cell C2 performs a read operation, and the second test voltage V8 does not change. When the first storage cell C1 performs the Nth write operation, the second storage cell C2 performs the Nth read operation, and the second test voltage V8 changes, producing a peak. This indicates that after the first storage cell C1 writes N times, the energy generated is sufficient to change the state of the second storage cell C2. Therefore, the processor 30 can calculate the energy generated by the first storage cell C1 performing N write operations, and this energy is the interference energy generated by the first storage cell C1 on the second storage cell C2.

[0088] In some embodiments, such as Figure 2 As shown, the differential pressure generator 22 is connected between the first selection switch 261 and the first voltage detection module 231. The resistance of the first selection switch 261 is negligible, and the current value of the differential pressure generator 22 can represent the current value of the first memory cell C1 during the write operation.

[0089] Please see Figure 10 , Figure 10 This is a schematic diagram of the processor structure provided in some embodiments of this application.

[0090] In some embodiments, the processor 30 includes a statistics module 31, a first calculation module 32, a second calculation module 33, and a third calculation module 34.

[0091] The statistics module 31 is used to count the number of write operations performed by the first storage unit C1 and the time of each write operation when the second test voltage V8 changes. Figure 8As shown, for example, the second test voltage V8 changes at time T1. At this time, the number of write operations N performed by the first memory cell C1 within time T1 and the time T0 of a single write operation can be counted, that is... Figure 5 The number of medium wave crests.

[0092] The first calculation module 32 is used to calculate the voltage difference across the first storage cell C1 based on the first test voltage and the voltage at the third input terminal 253. Specifically, the voltage V3 at the third input terminal 253 (e.g., ...) is used as an example. Figure 3 By subtracting the first test voltage V7 from the 4-5V in the first test voltage, the voltage difference (V3-V7) across the first memory cell C1 can be obtained.

[0093] The second calculation module 33 is used to calculate the current value generated by the differential pressure generator 22.

[0094] In some embodiments, the second calculation module 33 includes a first calculation unit 331 and a second calculation unit 332. The first calculation unit 331 is used to calculate the voltage of the first input terminal 251 (e.g., Figure 2 V2) and the first test voltage (e.g. Figure 8 The voltage difference (V7) is used to calculate the current value based on the voltage difference and the resistance R of the voltage difference generator 22, for example, by dividing (V7-V2) by R.

[0095] The third calculation module 34 is used to calculate the energy generated by the first storage unit C1 based on the voltage difference, the current value, the time, and the number of times. In some embodiments, the energy can be calculated according to the following formula (1).

[0096]

[0097] It should be noted that formula (1) represents an ideal situation, where the first test voltage V7 is constant. In actual practice, Figure 8 The first test voltage V7 fluctuates, meaning that the first test voltage V7 has a functional relationship with time T. Therefore, the energy P needs to be calculated using the following integral formula (2).

[0098]

[0099] Please see Figure 11 , Figure 11 This is a schematic diagram of the structure of a memory testing apparatus provided in some embodiments of this application. For ease of understanding and brief explanation, the same structures as those in the above embodiments will continue to use the same reference numerals, and the same structures will not be described in detail. This embodiment will only describe the different structures in detail.

[0100] This embodiment and Figure 2 The difference in the embodiment is that the memory 100a further includes a third memory cell C3 disposed adjacent to the second memory cell C2, a fourth address line L4 connected to one end of the third memory cell C3, and the other end of the third memory cell C3 connected to the third address line L3. Therefore, the third address line L3 and the fourth address line L4 together realize the operation of the third memory cell C3.

[0101] like Figure 11 As shown, the test device 20a also includes a fourth voltage output interface 214 and a fourth selection switch 264. One end of the fourth voltage output interface 214 is used to connect to the fourth address line L4, and the other end of the fourth voltage output interface 214 is connected to the first input terminal 251. Therefore, the voltage signal can also be transmitted from the first input terminal 251 to the fourth voltage output interface 214.

[0102] A fourth selection switch 264 is connected between the first input terminal 251 and the fourth voltage output interface 214, and is connected in parallel with the first selection switch 261. The fourth control terminal 2641 of the fourth selection switch 264 is connected to the first control terminal 2611 of the first selection switch 261. Therefore, the open and closed states of the fourth selection switch 264 and the first selection switch 261 are synchronized. That is, when the first selection switch 261 and the fourth selection switch 264 receive the first voltage signal applied by the controller 24, both the first selection switch 261 and the fourth selection switch 264 switch to the open state. Thus, when the first input terminal 251 receives the write operation voltage applied by the controller 24, both the first memory cell C1 and the third memory cell C3 perform a write operation. Figure 1 Compared to the previous embodiment, adding a third storage cell C3 adjacent to the second storage cell C2 allows for the measurement of the energy generated by the two adjacent storage cells. This results in faster energy accumulation, which in turn causes the state of the second storage cell C2 to change more quickly. Consequently, the number of write operations required is reduced, and the testing time is also reduced accordingly.

[0103] Since the first storage unit C1 and the third storage unit C3 are connected in parallel, the voltage difference across the first storage unit C1 is equal to the voltage difference across the third storage unit C3. That is, the first test voltage at one end of the first storage unit C1 can also be expressed as the voltage at the corresponding end of the third storage unit C3. This is why a voltage detection module 23 does not need to be set near the fourth voltage output interface 214.

[0104] In some embodiments, such as Figure 11As shown, one end of the differential pressure generator 22 is connected to the first input terminal 251, and the other end of the differential pressure generator 22 is connected to the first selection switch 261 and the fourth selection switch 264 respectively. In this way, the total current of the branch where the first storage unit C1 is located and the branch where the third storage unit C3 is located can be calculated based on the resistance value of the differential pressure generator 22. Thus, the total energy generated by the first storage unit C1 and the third storage unit C3 can be calculated. The interference energy generated by an adjacent storage unit can be obtained by averaging the total energy. The interference energy generated by an adjacent storage unit can be calculated using the following formula (3).

[0105]

[0106] Please see Figure 12 , Figure 12 This is a schematic flowchart of a memory testing method provided in some embodiments of this application. The testing method is applied to the aforementioned memory testing apparatus and includes the following steps S1-S2.

[0107] Step S1: Apply voltage to the first address line L1, the second address line L2 and the third address line L3 until the second test voltage changes and then stop applying the voltage.

[0108] In a specific example, controller 24 is configured to refer to Figures 3-7 The waveform diagram is used to apply voltage until... Figure 8 The location of the second test voltage V8 changes.

[0109] Step S2: Calculate the energy generated by the first memory cell C1 based on the voltage of the first address line L1 and the third address line L3, the first test voltage, the resistance of the differential voltage generator 22, and the operating time of the first memory cell.

[0110] Please see Figure 13 , Figure 13 This is a schematic flowchart of energy calculation provided in some embodiments of this application. In some embodiments, step S2 may include the following steps S21-S24.

[0111] Step S21: Count the number of times the first storage unit C1 performs the write operation and the time of a single write operation when the second test voltage changes.

[0112] See Figure 9 For example, the time it takes for the second test voltage V8 to change is T1, and within T1, the first memory cell C1 performs N write operations, with the time for each write operation being T0 (e.g., Figure 5 As shown in the figure, N multiplied by T0 is the operation time of the first storage unit.

[0113] Step S22: Calculate the voltage difference across the first storage cell C1 based on the first test voltage and the voltage at the third input terminal 253.

[0114] In some embodiments, see Figure 8 If the first test voltage is V7 and the voltage at the third input terminal 253 is V3, then the voltage difference is V3-V7.

[0115] Step S23: Calculate the current value generated by the differential pressure generator 22.

[0116] For a specific example, the voltage at the first input terminal 251 is first calculated by the first calculation unit 331 (e.g., ...). Figure 3 The voltage V2 in the test voltage (e.g.) and the first test voltage (e.g.) Figure 8 The second calculation unit 332 calculates the current value based on the voltage difference (V7) and the resistance value of the voltage difference generator.

[0117] Step S24: Calculate the energy generated by the first storage unit C1 based on the voltage difference, the current value, the time, and the number of times.

[0118] exist Figure 2 In the embodiments, energy can be calculated according to the above formula (1) or (2). Figure 10 In the embodiment, energy can be calculated according to the above formula (3).

[0119] The memory 100 / 100a test system 200 provided in this application embodiment includes a test device 20 / 20a and a processor 30. The test device 20 / 20a detects a second test voltage by setting a second voltage detection module 232, thereby monitoring the time taken for the second memory cell C2 to be interfered with by the first memory cell C1, and thus obtaining the operation time of the first memory cell C1. The first voltage detection module 231 detects a first test voltage at one end of the first address line L1, so the processor 30 can calculate the interference energy generated by the first memory cell C1 on the second memory cell C2 during operation based on the voltages of the first address line L1 and the third address line L3, the first test voltage, the resistance value of the differential voltage generator 22, and the operation time of the first memory cell C1.

[0120] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A testing system for a memory, characterized in that, The memory includes a first memory cell and a second memory cell arranged adjacent to each other, a first address line connected to one end of the first memory cell, a second address line connected to one end of the second memory cell, and a third address line connected to the other ends of the first memory cell and the second memory cell. Both the first memory cell and the second memory cell include a first electrode, a second electrode, and a selection switch layer located between the first electrode and the second electrode. The first memory cell and the second memory cell are independent of each other. The testing system includes a testing device and a processor. The testing device includes: The voltage output interface includes a first voltage output interface, a second voltage output interface and a third voltage output interface. The first voltage output interface is used to connect to the first address line, one end of the second voltage output interface is used to connect to the second address line, and the third voltage output interface is used to connect to the third address line. A differential pressure generator is connected to the first voltage output interface; The voltage detection module includes a first voltage detection module and a second voltage detection module. The first voltage detection module is used to detect a first test voltage between the first voltage output interface and the differential voltage generator. The second voltage detection module is used to detect a second test voltage at the other end of the second voltage output interface. The controller is configured to apply voltage to the first address line, the second address line, and the third address line through the voltage output interface to perform multiple write operations on the first memory cell and multiple read operations on the second memory cell until the second test voltage changes and the application of the voltage is stopped. The processor is used to calculate the energy generated by the first memory cell based on the voltage of the first address line and the third address line, the first test voltage, the resistance of the differential voltage generator, and the operating time of the first memory cell.

2. The memory testing system according to claim 1, characterized in that, The testing apparatus also includes: The first input terminal is connected to the differential pressure generator and is used to receive the write operation voltage applied by the controller; The second input terminal is connected to the second voltage output interface and is used to receive the read operation voltage applied by the controller; The third input terminal, connected to the third voltage output interface, is used to receive the turn-on voltage applied by the controller.

3. The memory testing system according to claim 2, characterized in that, The testing apparatus also includes: A first selector switch is connected between the first input terminal and the differential pressure generator. When the first control terminal of the first selector switch receives a first voltage signal applied by the controller, the first selector switch is switched to the open state; when the first control terminal receives a second voltage signal applied by the controller, the first selector switch is switched to the closed state. A second selector switch is connected between the second input terminal and the second voltage detection module. When the second control terminal of the second selector switch receives a third voltage signal applied by the controller, the second selector switch is switched to the open state; when the second control terminal receives a fourth voltage signal applied by the controller, the second selector switch is switched to the closed state. Specifically, when the first selection switch is in the open state, the second selection switch is in the closed state, causing the first storage unit to perform a write operation; when the first selection switch is in the closed state, the second selection switch is in the open state, causing the second storage unit to perform a read operation.

4. The memory testing system according to claim 1, characterized in that, The testing apparatus also includes: An oscilloscope, connected to the first voltage detection module and the second voltage detection module, is used to display the waveforms of the first test voltage and the second test voltage as a function of time.

5. The memory testing system according to claim 3, characterized in that, The differential pressure generator is connected between the first selector switch and the first voltage detection module.

6. The memory testing system according to claim 5, characterized in that, The processor includes: The statistics module is used to count the number of times the first storage unit performs the write operation and the time of a single write operation when the second test voltage changes. The first calculation module is used to calculate the voltage difference across the first storage unit based on the first test voltage and the voltage at the third input terminal. The second calculation module is used to calculate the current value generated by the differential pressure generator; The third calculation module is used to calculate the energy generated by the first storage unit based on the voltage difference, the current value, the time, and the number of times.

7. The memory testing system according to claim 6, characterized in that, The second calculation module includes: The first calculation unit is used to calculate the voltage difference between the voltage at the first input terminal and the first test voltage. The second calculation unit is used to calculate the current value based on the voltage difference and the resistance value of the voltage difference generator.

8. The memory testing system according to claim 3, characterized in that, The memory further includes a third memory unit disposed adjacent to the second memory unit, a fourth address line connected to one end of the third memory unit, and the other end of the third memory unit connected to the third address line; the testing device further includes: A fourth voltage output interface, one end of which is connected to the fourth address line, and the other end of which is connected to the first input terminal; A fourth selection switch is connected between the first input terminal and the fourth voltage output interface, and is connected in parallel with the first selection switch. The fourth control terminal of the fourth selection switch is connected to the first control terminal of the first selection switch. One end of the differential pressure generator is connected to the first input terminal, and the other end of the differential pressure generator is connected to the first selection switch and the fourth selection switch, respectively.

9. A method for testing a memory, characterized in that, The test method, applied to the test system according to any one of claims 1-8, comprises: Apply voltage to the first address line, the second address line, and the third address line until the second test voltage changes and then stop applying the voltage. The energy generated by the first memory cell is calculated based on the voltages of the first address line and the third address line, the first test voltage, the resistance of the differential voltage generator, and the operating time of the first memory cell.

10. The testing method for a memory according to claim 9, characterized in that, The testing device further includes: a third input terminal, connected to the third voltage output interface, for receiving the conduction voltage applied by the controller; and a step of calculating the energy generated by the first storage unit based on the voltages of the first address line and the third address line, the first test voltage, the resistance value of the differential voltage generator, and the operating time of the first storage unit, including: The number of times the first storage unit performs the write operation and the time of each write operation are recorded when the second test voltage changes. The voltage difference across the first memory cell is calculated based on the first test voltage and the voltage at the third input terminal. Calculate the current value generated by the differential pressure generator; The energy generated by the first storage unit is calculated based on the voltage difference, the current value, the time, and the number of times.

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