A design of power supply and enable timing control logic circuit

Abstract

The present invention relates to a power supply and enable timing control logic circuit design, the power supply and enable timing control logic circuit comprises: an LDO circuit, a bandgap reference source circuit, a post-stage module enable circuit and a DC-DC converter; wherein the LDO circuit receives an input voltage VIN, and under the control of an external enable signal EN, supplies power to the DC-DC converter through the bandgap reference source circuit and the post-stage module enable circuit. The beneficial effects of the present invention are: the time-sharing control operation of each component in the power supply and enable timing control logic circuit optimizes the power-on timing process, avoids the working error of the DC-DC converter main loop caused by the timing competition between modules, and at the same time, since the input VIN has a wide load range, the delay control between the modules also reserves a certain controllable range to ensure that the power-on timing can start the circuit normally under all input conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuit design, and more specifically, to a power supply and enable timing control logic circuit design. Background Art

[0002] With the popularity of mobile devices, the demand for efficient power management has increased significantly. Smartphones, tablets, and laptops require long battery life and stable power supply. PMIC (power management chip) regulates battery voltage, manages the charging process, and provides the required voltage rails in these devices to optimize power usage, reduce power consumption, and improve battery life. For example, the PMIC in modern smartphones can effectively manage battery consumption in different working modes, ensuring good performance under high performance requirements and low power standby state. The intelligence of home appliances and smart home devices has also raised new power management challenges. Home appliances with integrated smart functions (such as refrigerators, washing machines, air conditioners) and smart home devices (such as smart bulbs and sockets) require PMIC to provide stable power, support intelligent control systems, and ensure reliable operation. PMIC is also needed in the automotive electronics field, especially electric vehicles and hybrid vehicles, which need to efficiently manage the charging and discharging of battery packs to achieve optimal energy utilization and long driving range. The rise of Internet of Things (IoT) devices has further promoted the application of PMIC. These devices need to maintain low power consumption during long-term operation. PMIC is responsible for regulating power to support sensors, communication modules, and processors, and maintaining extremely low power consumption in standby, thereby extending device battery life and reducing maintenance costs.

[0003] A general power management chip consists of a DC-DC converter and a low dropout regulator (LDO). LDO is a linear regulator used in electronic circuits. Its main function is to convert the input voltage into a stable DC voltage to ensure that the circuit components operate at a stable voltage. Compared with traditional linear regulators, LDO has a lower voltage difference requirement, that is, the difference between the input voltage and the output voltage is relatively small. This feature makes LDO widely used in many applications that require precise voltage supply. However, since LDO achieves voltage regulation by reducing the input voltage to the output voltage, the unused energy is dissipated in the form of heat. Therefore, when the input voltage is much higher than the output voltage, the efficiency of LDO is significantly reduced. Due to the low efficiency, LDO will cause large power loss in high-power applications, and then generate excessive heat, which requires additional heat dissipation measures to maintain the stability of the circuit. In addition, the input voltage of LDO must be higher than the output voltage, and the gap between the input voltage and the output voltage (dropout voltage) should be as small as possible. In applications where the input voltage is close to the output voltage, the use of LDO will be limited. Compared with switching regulators, LDOs have limited load capacity. Especially in applications that require high current, LDO power consumption and heat dissipation issues will be more prominent.

[0004] Traditional DC switching power supplies include buck converters, boost converters, and buck-boost converters, etc., and their efficiency can exceed 90%, which is due to their ability to control output power by quickly switching switching elements, thereby reducing energy loss. In contrast, although the linear regulator has a simple structure, it will result in higher power loss when the input voltage and output voltage are far apart. The switching converter uses high-frequency switching technology to significantly reduce the size of the transformer and filter, making it superior to the linear regulator in performance and more suitable for space-constrained application scenarios. In addition, DC power converters can provide output voltages ranging from a few volts to hundreds of volts to meet the needs of different electronic devices, and many modern converters are equipped with over-current, over-voltage, short-circuit and other protection functions to ensure the safe operation of the equipment under abnormal conditions, improving reliability and service life. They can also adapt to a variety of input voltage sources, including renewable energy sources such as solar panels, and operate stably over a wide range of operating temperatures.

[0005] Modern electronic devices, such as smartphones, tablets, laptops, and industrial control systems, have increasingly complex power requirements. These devices typically require multiple power rails to support the operation of different components, including processors, memory, displays, and wireless communication modules. This requires power management chips to not only be able to handle a wide range of input voltages, but also output a wide range of regulated voltages and carry a large load capacity to adapt to the power requirements of different devices and ensure stable operation of the devices. Traditional PMIC structures such as Figure 1 As shown in the figure, the output stage is mainly LDO, which makes the chip unable to adapt to the requirements of a wide load range, and the current carrying capacity and dynamic response speed cannot meet the system requirements. Therefore, most PMICs that adapt to the development of today's electronic technology use Figure 2 In the PMIC structure shown, the output stage is mainly generated by the DC-DC converter to improve conversion efficiency, increase the load bearing range, and increase the converter response speed; the DC-DC converter is powered by LDO to reduce power supply noise and ripple, improve conversion accuracy, and inherit overcurrent protection and overheating protection functions to increase system reliability and safety and prevent system damage caused by excessive current or high temperature. At the same time, since the control circuit of the DC-DC converter requires multiple reference currents and reference voltages, this part is generally generated by a bandgap reference source BANDGAP.

[0006] However, when using LDO to provide power and reference voltage and current to the DC-DC converter, some timing problems may occur. On the one hand, there is the matching between the response speed of the LDO and the switching frequency and load change speed of the DC-DC converter. If the adjustment response of the LDO is too slow, it may not be able to handle the voltage fluctuation at the output of the Buck chip in time, resulting in unstable output voltage. On the other hand, there is the matching problem between the response speed of the BANDGAP and the operation of the DC-DC converter. If the phase response speed of the BANDGAP is too slow, it may not be able to provide accurate reference voltage and reference current (Reference), which will cause converter operation errors. To avoid this problem, the traditional solution is to carefully select the performance parameters of the LDO and BANDGAP during design, and perform sufficient timing analysis to ensure that they can respond quickly and effectively to the voltage changes of the DC-DC Converter. However, due to the influence of working environments such as temperature and noise, this timing problem has not been completely solved. In some cases, system operation disorders caused by power-on timing problems will still occur. Summary of the invention

[0007] The purpose of the present invention is to address the deficiencies of the prior art and to propose a power supply and enable timing control logic circuit design.

[0008] In a first aspect, a power supply and enable timing control logic circuit is provided, comprising: an LDO circuit, a bandgap reference source circuit, a post-stage module enable circuit and a DC-DC converter;

[0009] The LDO circuit receives an input voltage VIN and, under the control of an external enable signal EN, supplies power to the DC-DC converter through the bandgap reference source circuit and the subsequent module enable circuit.

[0010] Preferably, the LDO circuit comprises an operational amplifier circuit, a pre-start circuit and a feedback resistor network;

[0011] Among them, when the external enable signal EN is at a low level, the pre-start circuit is started, and a pre-start voltage VCC_P is generated to power the bandgap reference source circuit and the subsequent module enable circuit, the output of the operational amplifier is shielded, and the feedback resistor network generates a feedback voltage to the operational amplifier circuit and the pre-start circuit; when the external enable signal EN is at a high level, the pre-start circuit is turned off, and the output of the operational amplifier is released.

[0012] Preferably, the LDO circuit also includes an ESR resistor of an external capacitor and a feedforward capacitor CF; a zero point is introduced inside the operational amplifier circuit; and the LDO circuit performs frequency compensation through the ESR resistor of the external capacitor, the feedforward capacitor CF and the zero point inside the operational amplifier circuit.

[0013] Preferably, the subsequent module enabling circuit generates a corresponding subsequent circuit enabling signal CTRL according to an external enabling signal EN; and the DC-DC converter is in a standby state or starts working according to the subsequent circuit enabling signal CTRL.

[0014] Preferably, the post-stage module enabling circuit is composed of a PMOS tube MP, a capacitor CE, a hysteresis inverter INV3, an inverter INV4 and an inverter INV5; wherein, the gate of the PMOS tube MP is connected to an external enable signal EN, the source is connected to the output voltage of the LDO circuit; the drain is connected to the reference current IREF output by the bandgap reference source circuit; the positive terminal of CE is connected to the output voltage of the LDO circuit, and the negative terminal is connected to the drain of MP and the input of the hysteresis inverter NV3; the hysteresis inverter INV3, the inverter INV4 and the inverter INV5 are connected in series in sequence, and output a post-stage circuit enabling signal CTRL.

[0015] Preferably, the input voltage VIN has a wide load range, and the wide load range is 3V-36V.

[0016] In a second aspect, a method for operating a power supply and enable timing control logic circuit as described in any one of the first aspects is provided, comprising:

[0017] Step 1, input voltage VIN and external enable signal EN to the LDO circuit;

[0018] Step 2, control the external enable signal EN to be low level, the LDO circuit generates a stable pre-start voltage VCC_P, and supplies power to the bandgap reference source circuit and the subsequent module enable circuit at the same time; the bandgap reference source circuit starts to work and generates a VBG voltage and a corresponding reference current IREF and a reference voltage VREF; the subsequent module enable circuit receives the pre-start voltage VCC_P and the reference current IREF, generates a low level subsequent circuit enable signal CTRL, and puts the DC-DC converter in a standby state;

[0019] Step 3: Control the external enable signal EN to be high level, the LDO circuit generates a stable operating voltage VCC, and the subsequent circuit enable signal CTRL generated by the subsequent module enable circuit is increased to a high level, so that the DC-DC converter starts to work.

[0020] In a third aspect, a power management chip is provided, comprising any power supply and enable timing control logic circuit as described in the first aspect.

[0021] The beneficial effects of the present invention are as follows: when the present invention uses an LDO circuit to provide power to a DC-DC converter, the LDO circuit can effectively filter out high-frequency noise from the input power supply, thereby reducing the noise level at the input power supply end of the DC-DC converter, helping to maintain the stability of the output voltage, and reducing EMI interference to surrounding circuits, thereby improving the reliability and stability of the entire power supply system. The time-sharing control operation of each component in the power supply and enable timing control logic circuit optimizes the power-on timing process of the designed buck converter, avoiding the working error of the main loop of the DC-DC converter caused by the timing competition between modules. At the same time, since the input VIN has a wide load range, the delay control between each module also reserves a certain controllable range to ensure that the power-on timing can start the circuit normally under all input conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the traditional PMIC structure;

[0023] Figure 2 Schematic diagram of PMIC structure to adapt to wide input and wide load range;

[0024] Figure 3 It is a structural diagram of the LDO circuit;

[0025] Figure 4 It is a structural schematic diagram of the enabling circuit of the subsequent module;

[0026] Figure 5 A schematic diagram of the structure of a power supply and enable timing control logic circuit provided by an embodiment of the present invention;

[0027] Figure 6a A timing simulation diagram of a power supply and an enabling module provided in an embodiment of the present invention;

[0028] Figure 6b A timing simulation diagram of another power supply and enabling module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention is further described below in conjunction with embodiments. The description of the following embodiments is only used to help understand the present invention. It should be noted that for ordinary persons in the art, without departing from the principle of the present invention, the present invention can also be modified in some ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0030] Embodiment 1:

[0031] like Figure 5 As shown, Example 1 of the present application provides a power supply and enable timing control logic circuit, which controls the working timing of the LDO circuit and the DC-DC converter through an external enable signal EN, that is, by giving EN a high or low level to control the working state of the LDO circuit, thereby determining whether the subsequent DC-DC converter starts to work normally, including: an LDO circuit, a bandgap reference source circuit, a subsequent module enable circuit and a DC-DC converter.

[0032] The LDO circuit receives an input voltage VIN and, under the control of an external enable signal EN, supplies power to the DC-DC converter through the bandgap reference source circuit and the post-stage module enable circuit. The input voltage VIN has a wide load range of 3V-36V. For example, the input voltage VIN can be as low as 3V, which has the characteristics of low power consumption.

[0033] Specifically, Figure 3 As shown, the LDO circuit includes an operational amplifier circuit, a pre-start circuit and a feedback resistor network. The operational amplifier circuit is composed of a comparator AMP1, NMOS tubes M0 and M5, NMOS power tubes MN1, PMOS power tube MP1, resistors R4 and RC, capacitor CC, and inverter INV1; the pre-start circuit is composed of NMOS tubes M1, M2, M3, M4, M11, M12, M13, M14, M21, M22, M23, M24, NMOS power tubes MN2 and MN3, PMOS power tube MP1, resistors R1, R2, R3, and inverter INV2; the feedback resistor network is composed of resistors RF1, RF2, RF3, and RF4.

[0034] The source of the PMOS power tube MP1 in the LDO circuit and one end of the resistors R1 and R4 are connected to the input voltage VIN; the sources of the NMOS tubes M0, M5, M1, M14, M3, and M24 are grounded GND; one end of the resistor RF4 and the negative end of the capacitor CC are grounded GND.

[0035] In the operational amplifier circuit, the positive input of the operational amplifier AMP1 is connected to a reference voltage, the negative input is connected to a voltage divider in the feedback resistor network, the output of AMP1 is connected to the gate of M0 and the drain of M5; the gate of M5 is connected to the input of the inverter INV1; one end of RC is connected to the output of AMP1, and the other end is connected to the positive end of the capacitor CC; the source of MN1 is connected to the drain of M0, the gate is connected to the output of INV1, and the drain is connected to one end of R4 and the gate of MP1. In the pre-start circuit of the LDO, the gate of M1 is connected to the external enable signal EN, the drain is connected to the gate of MN2 and the input of INV1, one end of R1 is connected to VIN, the other end is connected to the drain of MN2 and one end of R2, and the other end of R2 is connected to the drain of M11; the gate and drain of M11 are connected, and the source is connected to the drain of M12; the gate and drain of M12 are connected, and the source is connected to the drain of M13; the gate and drain of M13 are connected, and the source is connected to the drain of M14; the gate and drain of M14 are connected, and the source is grounded GND; the source of MN2 is connected to one end of R3, and the other end of R3 is connected to the drain of M2; the gate of M2 is connected to the output end of INV2 , the source is connected to the drain of M3; the gate of M3 is connected to the voltage divider between the feedback resistor network RF2 and RF3, and the source is grounded; the gate and drain of M11 are connected, and are connected to one end of R3 and the gate of MN3, and the source is connected to the drain of M12; the gate and drain of M21 are connected, and the source is connected to the drain of M22; the gate and drain of M22 are connected, and the source is connected to the drain of M23; the gate and drain of M23 are connected, and the source is connected to the drain of M24; the gate and drain of M24 are connected, and the source is grounded; the gate of M4 is connected to the voltage divider between the feedback resistor network RF1 and RF2, the drain is connected to the gate of MN3, and the source is grounded; the drain of MN3 is connected to the gate of MP1. The four resistors of the feedback resistor network are connected in series in the order of RF1, RF2, RF3, and RF4, and the other end of RF1 is connected to the drain of MP1 and the output signal VCC.

[0036] like Figure 4As shown, the post-stage module enabling circuit is composed of a PMOS tube MP, a capacitor CE, a hysteresis inverter INV3, an inverter INV4 and an inverter INV5; wherein, the gate of the PMOS tube MP is connected to an external enabling signal EN, the source is connected to the output voltage of the LDO circuit; the drain is connected to the reference current IREF output by the bandgap reference source circuit; the positive terminal of CE is connected to the output voltage of the LDO circuit, and the negative terminal is connected to the drain of MP and the input of the hysteresis inverter NV3; the hysteresis inverter INV3, the inverter INV4 and the inverter INV5 are connected in series in sequence, and output a post-stage circuit enabling signal CTRL.

[0037] Embodiment 2:

[0038] Based on Example 1, Example 2 of the present application provides a more specific power supply and enable timing control logic circuit, including: an LDO circuit, a bandgap reference source circuit, a post-stage module enable circuit and a DC-DC converter.

[0039] The LDO circuit includes an operational amplifier circuit, a pre-start circuit, a feedback resistor network, an equivalent series resistance (ESR) of an external capacitor, and a feedforward capacitor CF. The operational amplifier's non-inverting input is connected to a reference voltage, and the inverting input is connected to a feedback voltage derived from the resistor divider network RF1 and RF2. The high-voltage PMOS tube MP1 is selected as the power tube of the LDO, which can adapt to a wide range of input voltage changes. When the input voltage is as high as 36V, the drain-source end of the power tube can withstand a higher conduction voltage drop, and when the input voltage is as low as 3V, it only brings a small conduction voltage drop, so that the LDO can provide sufficient voltage.

[0040] The LDO circuit works in two stages and is controlled by an external enable EN. In the first stage, when EN=0, after VIN is powered on, the LDO pre-start circuit starts working, and the voltage at point A is clamped by the MOS connected by four diodes M11, M12, M13 and M14 ( Figure 3The two A points marked in the figure are connected together), M5 is turned on, the output of the first stage of the operational amplifier is pulled down to GND, and MN1 is turned off, the output of the operational amplifier is shielded, and the output of the LDO is determined by the outputs VB and VC of the startup circuit. VCC generates a preset voltage to power the subsequent circuit, and the feedback resistor network generates a feedback voltage to the operational amplifier and the pre-startup circuit to prepare for the next stage of work. In the second stage, after VIN is powered on and stabilized, the VCC voltage temporarily stabilizes at the preset value. At this time, the external enable EN is high, point A is pulled down to GND, and the pre-startup circuit is turned off. At this time, M5 is turned off, MN1 is turned on, and the two-stage output of the operational amplifier are released. At the same time, the reference voltage VREF1 generated by the bandgap reference source circuit has stabilized, and the LDO quickly enters the normal operation stage of the main loop. In the feedback resistor network, VRF4=VREF1, so:

[0041]

[0042] The first stage of the LDO operational amplifier is composed of a differential amplifier AMP1, which increases the input linear range. The second stage is composed of an input tube M1, a high-voltage NMOS tube MN1, and a resistor R4. Since the LDO input voltage is up to 36V, and the first-stage power supply voltage VCC of the amplifier is up to 5V, the amplifier output needs to be shifted to the high voltage domain through the high-voltage NMOS tube MN1 in the second stage.

[0043] In addition, the stability of the LDO has an important impact on the performance of the system. When disturbances occur in the circuit, if the loop stability is not enough, oscillations will occur, causing output abnormalities. At the same time, it is also necessary to ensure that the LDO output has sufficient transient response speed to avoid large voltage overshoots when the output load changes. In order to ensure the stability of the loop, it is necessary to ensure that the loop has a certain phase margin, so it is necessary to achieve the loop stability of the LDO through frequency compensation. This design uses three methods to compensate the frequency of the circuit. First, since an external capacitor is used, the ESR resistor of the external capacitor can usually be used to generate an external zero point for frequency compensation; in addition, a zero point is introduced inside the error amplifier of the LDO to compensate the phase of the LDO loop. Such as Figure 3 As shown in FIG, a resistor RC and a capacitor CC are connected in series at the output point of AMP1 for internal zero-point compensation. In addition to adding zero-point compensation inside the amplifier, this design also connects a feedforward capacitor CF across the LDO output and the feedback signal to compensate for the transfer function of the feedback circuit.

[0044] The subsequent module enabling circuit is as follows Figure 4As shown in the figure, when the external enable EN=0, the PMOS tube MP is turned on, and the reference current IREF generated by the bandgap reference source circuit reversely charges the negative electrode of the capacitor CE, so that the voltage at point M increases. After being shaped by the inverter, the output of the subsequent circuit enable signal CTRL is low level. At this time, the subsequent circuit module is turned off and the system does not work. When the external enable EN is high level, the PMOS tube MP is turned off, the negative electrode of the capacitor CE is discharged, and the voltage at point M drops to a low level. After being shaped by the inverter, the output of the subsequent circuit enable signal CTRL is high level, the subsequent circuit module is turned on, and the system starts to work normally.

[0045] After the LDO circuit and the bandgap reference source circuit work stably, with the effectiveness of the external enable signal EN, an enable signal CTRL is generated for the subsequent circuit, so that the relevant modules of the subsequent circuit start working, ensuring that the system starts working normally after the power supply and reference voltage are stable, ensuring the correctness and stability of the power-on timing and system operation. The design uses a hysteresis inverter INV1 as the first-level shaping to avoid the influence of noise generated by point M and signal fluctuations on the output CTRL, thereby ensuring a more stable output of the control enable signal.

[0046] It should be noted that the parts in this embodiment that are the same or similar to those in Embodiment 1 can be referenced to each other and will not be described in detail in this application.

[0047] Embodiment 3:

[0048] On the basis of Embodiments 1 and 2, Embodiment 3 of the present application provides a working method of a power supply and enable timing control logic circuit, including:

[0049] Step 1: Input voltage VIN and external enable signal EN to the LDO circuit.

[0050] Step 2, control the external enable signal EN to be low level, the LDO circuit generates a stable pre-start voltage VCC_P, and supplies power to the bandgap reference source circuit and the subsequent module enable circuit at the same time; the bandgap reference source circuit starts to work and generates a stable VBG voltage, which, after shunting and voltage division, generates a stable reference current IREF and a reference voltage VREF to provide to the subsequent circuit; the subsequent module enable circuit receives the pre-start voltage VCC_P and the reference current IREF, generates a low-level subsequent circuit enable signal CTRL, and puts the DC-DC converter in standby state.

[0051] In step 2, the LDO circuit works in the pre-startup stage. The bandgap reference source circuit generates the VBG voltage and the corresponding IREF and VREF to prepare for the control circuit. At the same time, VREF is fed back to the error amplifier of the LDO circuit to prepare for the main loop working stage of the LDO. At the same time, the generation of VCC_P and the reference current IREF allows the capacitor of the subsequent module enabling circuit to complete the charging process, ensuring that the CTRL signal is low at this time, and the DC-DC converter is in standby mode at this moment. The signal transmission process in step 2 can be referred to Figure 5 Purple lines in the.

[0052] Step 3: Control the external enable signal EN to be high level, the LDO circuit generates a stable operating voltage VCC, and the subsequent circuit enable signal CTRL generated by the subsequent module enable circuit is increased to a high level, so that the DC-DC converter starts to work.

[0053] Specifically, when the reference voltage is stable, the control system loop is ready to work normally, and the external EN enable signal is high, the LDO circuit enters the main loop working state, and generates a stable VCC for normal operation. At this time, VBG, IREF and VREF remain stable, and the capacitor of the subsequent module enable circuit enters the discharge process. The subsequent circuit enable signal CTRL rises to a high level, so that the DC-DC converter starts to work normally, and then the designed PMIC starts to work stably. The signal transmission process in step 3 can be referred to Figure 5 The red line in.

[0054] The time-sharing control operation of each component in the power supply and enable timing control logic circuit optimizes the power-on timing process of the designed buck converter, avoiding the working errors of the DC-DC converter main loop caused by timing competition between modules. At the same time, since the input VIN has a wide load range, in order to ensure that the power-on timing can start the control circuit normally under all input conditions, the delay control between its modules also needs to reserve a certain controllable range.

[0055] For example, FIG6 shows a timing simulation diagram of the power supply and enable module, where Figure 6a In the case of input VIN=8V, VCC_P=3.9V, VCC=5V, after EN is powered on, CTRL delays 578us to increase, the subsequent circuit is enabled and starts to work normally; Figure 6b In the case of input VIN=3V, VCC_P=3V, VCC=3V, after EN is powered on, CTRL delays 268us to increase, the subsequent circuit is enabled and starts to work normally.

[0056] Specifically, the method provided in this embodiment is a working method corresponding to the circuits provided in Embodiments 1 and 2. Therefore, the parts in this embodiment that are the same or similar to Embodiments 1 and 2 can be referenced to each other and will not be repeated in this application.

Claims

1. A power supply and enable timing control logic circuit, characterized in that: include: LDO circuit, bandgap reference source circuit, post-module enabling circuit and DC-DC converter; The LDO circuit receives an input voltage VIN and, under the control of an external enable signal EN, supplies power to a DC-DC converter through the bandgap reference source circuit and the subsequent module enable circuit; the LDO circuit includes an operational amplifier circuit, a pre-start circuit and a feedback resistor network; when the external enable signal EN is at a low level, the pre-start circuit is started to generate a pre-start voltage VCC_P to supply power to the bandgap reference source circuit and the subsequent module enable circuit, the output of the operational amplifier is shielded, and the feedback resistor network generates a feedback voltage to the operational amplifier circuit and the pre-start circuit; when the external enable signal EN is at a high level, the pre-start circuit is turned off, the output of the operational amplifier is released, and a stable operating voltage VCC is generated.

2. The power supply and enable timing control logic circuit according to claim 1, characterized in that: The LDO circuit also includes an ESR resistor of an external capacitor and a feedforward capacitor CF; a zero point is introduced inside the operational amplifier circuit; and the LDO circuit performs frequency compensation through the ESR resistor of the external capacitor, the feedforward capacitor CF and the zero point inside the operational amplifier circuit.

3. The power supply and enable timing control logic circuit according to claim 2, characterized in that: The post-stage module enabling circuit generates a corresponding post-stage circuit enabling signal CTRL according to an external enabling signal EN; the DC-DC converter is in a standby state or starts working according to the post-stage circuit enabling signal CTRL.

4. The power supply and enable timing control logic circuit according to claim 3, characterized in that: The post-stage module enabling circuit is composed of a PMOS tube MP, a capacitor CE, a hysteresis inverter INV3, an inverter INV4 and an inverter INV5; wherein the gate of the PMOS tube MP is connected to an external enabling signal EN, the source is connected to the output voltage of the LDO circuit; the drain is connected to the reference current IREF output by the bandgap reference source circuit; the positive terminal of CE is connected to the output voltage of the LDO circuit, and the negative terminal is connected to the drain of MP and the input of the hysteresis inverter NV3; the hysteresis inverter INV3, the inverter INV4 and the inverter INV5 are connected in series in sequence, and output a post-stage circuit enabling signal CTRL.

5. The power supply and enable timing control logic circuit according to claim 4, characterized in that: The input voltage VIN has a wide load range, and the wide load range is 3V-36V.

6. A method for operating a power supply and enable timing control logic circuit according to any one of claims 1 to 5, characterized in that: include: Step 1, input voltage VIN and external enable signal EN to the LDO circuit; Step 2, control the external enable signal EN to be low level, the LDO circuit generates a stable pre-start voltage VCC_P, and supplies power to the bandgap reference source circuit and the subsequent module enable circuit at the same time; the bandgap reference source circuit starts to work and generates a VBG voltage and a corresponding reference current IREF and a reference voltage VREF; the subsequent module enable circuit receives the pre-start voltage VCC_P and the reference current IREF, generates a low level subsequent circuit enable signal CTRL, and puts the DC-DC converter in a standby state; Step 3: Control the external enable signal EN to be high level, the LDO circuit generates a stable operating voltage VCC, and the subsequent circuit enable signal CTRL generated by the subsequent module enable circuit is increased to a high level, so that the DC-DC converter starts to work.

7. A power management chip comprising the power supply and enable timing control logic circuit according to any one of claims 1 to 5.

Images