A frequency conversion and state monitoring control device

Abstract

The present invention relates to a high-speed frequency conversion and status monitoring control device, belonging to the technical field of information equipment manufacturing. The device comprises an FPGA main control circuit, a clock circuit, a serial port conversion circuit, a high-speed frequency conversion circuit, a power regulation circuit, a status monitoring circuit, a power supply circuit, and an external interface circuit. Rapid frequency conversion is achieved by changing the parameter configuration of the fractional-frequency phase-locked loop register within the integrated phase-locked circuit BR9177. Different attenuation values ​​are configured for the registers within the serial-parallel digital controlled attenuator BR9153S to adjust the power. The analog-to-digital conversion circuit JAD7998 performs cyclic detection of the analog input status of the 8-channel self-test monitoring, achieving real-time reporting of the 8-channel self-test monitoring status and self-closed-loop protection for power amplifier failures. The reference clock output frequency is modified through debugging control commands to change the output frequency error of the high-speed frequency conversion circuit. The device is a fully domestically produced design with fast frequency conversion speed, adjustable output frequency error accuracy, and output power. The device also features high channel transmission efficiency during rapid frequency conversion, meeting the application requirements of specific scenarios.

Description

Technical Field

[0001] The invention relates to a high-speed frequency conversion and state monitoring control device, belonging to the technical field of information equipment manufacturing. Background Art

[0002] The widespread use of wireless communication equipment has promoted and driven the rapid development of the electronic information industry. Domestic wireless communication equipment is the ballast for ensuring national stability and the security of the national defense industry. In certain specific environments and application scenarios, wireless communication equipment is required not only to have ultra-fast frequency conversion speeds and efficient channel transmission rates, but also to have self-monitoring of operating status, real-time reporting, closed-loop control, and alarm protection capabilities. While ensuring operating performance standards remain unchanged, how can we prevent high-power information transmission equipment from burning out due to excessive reflected power from antenna failures or load mismatches? How can we quickly and stably activate self-protection functions in the event of temperature anomalies? How can we quickly and accurately self-check, monitor, scan, and locate faults when they occur? How can we effectively improve the safety, reliability, maintainability, and environmental adaptability of domestic wireless communication equipment, and meet the real-time application requirements of special scenarios? This has become a crucial and challenging task for researchers who are constantly striving to overcome difficulties. Summary of the Invention

[0003] The present invention aims to address the aforementioned high standards for wireless communication equipment, address specific application scenarios of wireless communication equipment, and address the shortcomings of existing wireless communication equipment technology by providing a high-speed frequency conversion and status monitoring control device. The device utilizes a domestically produced FPGA as the primary control component, features independently controlled key hardware circuits and software design, and features adjustable output power and output frequency accuracy. This device achieves rapid frequency conversion, self-monitoring of device status, and automatic closed-loop protection of the power amplifier standing wave. The device features fast frequency conversion, extended effective transmission time for steady-state channel information during frequency changes, strong real-time status monitoring, and accurate and efficient fault location. This device addresses the problems of existing similar devices, such as low domestic production rates, inability to self-control key control components, large and unadjustable output frequency offsets, slow frequency conversion speeds, short effective information transmission time during rapid frequency changes, low channel transmission efficiency, high reflected power due to antenna short-circuit faults or load adaptation, and the potential for device burnout, single output power, long internal board status self-monitoring and fault location time, weak self-repair and protection capabilities, and poor adaptability to application scenarios and environments, as well as poor maintainability.

[0004] The present invention achieves the above-mentioned purpose through the following technical solutions:

[0005] A high-speed frequency conversion and status monitoring control device, comprising a control device body, an FPGA main control circuit, a clock circuit, a serial port conversion circuit, a high-speed frequency conversion circuit, a power regulation circuit, a status monitoring circuit, a power supply circuit, and an external interface circuit; its characteristics are as follows: the control device body is composed of the above-mentioned module circuits placed on the same printed circuit board; the FPGA main control circuit is composed of an FPGA control circuit, a JTAG simulation download circuit, a data storage circuit, and a Flash program loading circuit; the clock circuit is mainly composed of a 28.8MHz crystal oscillator device JTM1907 and its peripheral devices, which can be fine-tuned by inputting debugging control commands from a serial port. components; the serial port conversion circuit consists of the SM3232EEUE signal transceiver and its peripheral components; the high-speed frequency conversion circuit consists of the BR9177 integrated phase-locked circuit, the third-order loop filter, and the RF transformer conversion circuit; the power regulation circuit consists of the serial-parallel digital controlled attenuator BR9153S and peripheral circuits; the status monitoring circuit consists of the analog-to-digital conversion circuit JAD7998 and peripheral resistor-capacitor components; the power supply circuit consists of two ultra-low voltage difference linear JS74401 regulators generating two DC voltage stabilization circuits; the external interface circuit consists of the connector DS-SFM-125-02-LDA and multiple sensor components.

[0006] The FPGA master control circuit cyclically scans and detects the master control commands sent in by the three data signal lines FPGA_CLK clock, FPGA_DATA data, and FPGA_LE enable in the external interface circuit. When high-speed frequency parameter conversion is required, the FPGA_LE port receives the falling trigger edge sent from the outside. Whenever the rising edge of the clock FPGA_CLK signal comes, the current value of FPGA_DATA is sent to the FPGA master control circuit for shift storage. After receiving 48 bits of data and receiving the rising edge of the FPGA_LE signal at the same time, the reception of the master control command is completed; the master control command is sent to the FPGA master control circuit one bit at a time through the high-speed data port FPGA_DATA. The received 48 bits of data include the current frequency conversion parameters, power adjustment attenuation value, channel transceiver control value, working mode control, status monitoring reporting and control processing information; after the master control command is received, the received 48 bits of data are unpacked and extracted to extract the current frequency parameters, power attenuation parameters, channel status monitoring parameters, and perform related control processing; the extracted The frequency value is mapped into the corresponding bit configuration value of the 6 configuration registers of the BR9177 integrated phase-locked circuit through frequency conversion calculation processing. If the current frequency value is different from the previous frequency value, the 6 configuration register configuration driver of the BR9177 integrated phase-locked circuit is immediately started. The BR9177 integrated phase-locked circuit achieves stable frequency lock through the PLL phase-locked loop composed of an internal integrated VCO oscillator, PFD phase detector comparator, frequency divider and external loop filter; by selecting the fractional frequency division mode, widening the loop filter bandwidth and increasing the reference comparison frequency parameter, it achieves rapid frequency conversion and locking; at the same time, the power attenuation conversion parameter mapping processing is performed according to the extracted power attenuation value; through the ATT_EN, ATT_DATA, and ATT_CLK three-wire interfaces of the FPGA main control circuit, the power attenuation control word is sent to the BR9153S serial-parallel digital controlled attenuator of the power regulation circuit in a certain timing, realizing the synchronous change of link channel gain attenuation while frequency conversion; by extracting the status monitoring command, multi-channel status monitoring identification processing is performed, and the I 2 The JAD7998 analog-to-digital conversion circuit channel selection register of the configuration status monitoring circuit is configured through the C serial interface F_JAD_SDA and F_JAD_SCL. The self-test monitoring status analog input signal of the currently configured channel is read and the analog-to-digital sampling value is also read through the I 2The C serial interface F_JAD_SDA and F_JAD_SCL are sent to the FPGA main control circuit, and after the internal data calculation and processing of the FPGA main control circuit, they are sent out by the sending serial port F_TXD. After the level conversion of the signal transceiver interface of the serial port conversion circuit SM3232EEUE, the monitoring status data is sent out by the RXD232 pin; similarly, the external data and debugging commands received by TXD232 are converted to LVCMOS3.3V level by the serial port conversion circuit RS232 and then sent to the FPGA main control circuit by the F_RXD port. The FPGA main circuit unpacks the received debugging command data, converts it, and performs the corresponding control operation; when the 8-way self-test monitoring status When the input power amplifier standing wave forward Vin1 and reverse analog voltage Vin2 are monitored abnormally, the FPGA main control circuit sends an F_PTT signal to start the power amplifier standing wave closed-loop protection; the 8-channel status monitoring sampling data is sent through the serial port RXD232 after calculation and conversion processing. When any status abnormality is detected, the corresponding alarm protection function is activated; the software debugging command is sent through the JTM_RX_232 serial port, and then sent to the JTM_RX input port of the clock circuit after passing through the level conversion circuit. By fine-tuning the software command parameters, the clock output frequency 28.8MHz frequency accuracy is changed, and then the reference input clock of the high-speed frequency conversion circuit phase-locked loop is changed, so as to achieve the purpose of fine-tuning the output frequency of the frequency conversion circuit.

[0007] The FPGA master control circuit is mainly composed of an FPGA control circuit, a JTAG simulation download circuit, a data storage circuit, and a Flash program loading circuit. The FPGA master control circuit mainly realizes the functions of master control command detection and reception, frequency conversion calculation processing, BR9177 register configuration, power attenuation parameter conversion, BR9153S attenuator parameter configuration, JAD7988 channel selection register configuration, reading of configuration channel analog-to-digital conversion sampling values, state monitoring and identification processing, serial port transceiver processing, and amplifier standing wave closed-loop protection. At the same time, it realizes the functions of JTAG online program simulation, program execution power-on loading, program download, and storage and reading of various required data parameters.

[0008] The clock circuit is mainly composed of a 28.8MHz crystal oscillator device JTM1907 and its peripheral devices, which can be fine-tuned by serial port input control commands, and provides a reference clock for the FPGA main control circuit and the BR9177 integrated phase-locked circuit.

[0009] The serial port conversion circuit is mainly composed of SM3232EEUE signal transceiver and its peripheral devices. Through the mutual conversion of two sets of RS232 levels and LVCMOS3.3V levels, it realizes 8-way self-test monitoring status and alarm information reporting, and receives data interaction of debugging control commands.

[0010] The high-speed frequency conversion circuit is composed of a BR9177 integrated phase-locked circuit, a third-order loop filter, and a radio frequency transformer conversion circuit. By changing the parameter configuration of the six registers inside the BR9177 integrated phase-locked circuit, rapid frequency locking and conversion can be achieved.

[0011] The power regulation circuit consists of a 6-bit serial-parallel digitally controlled attenuator (BR9153S) and peripheral resistors and capacitors. The attenuation value of the register within the 6-bit serial-parallel digitally controlled attenuator (BR9153S) is controlled via a three-wire serial interface to adjust the RF channel gain. The status monitoring circuit primarily consists of an 8-channel analog-to-digital converter (JAD7998) and peripheral components to digitally convert and process 8-channel analog signals.

[0012] The power supply circuit is composed of two ultra-low voltage difference linear JS74401 regulators and peripheral circuits to provide the required DC power to the circuit module.

[0013] The external interface circuit is composed of a connector DS-SFM-125-02-LDA and a plurality of sensing components, and is used for connection, interaction, joint debugging, control and status monitoring with external interface signals.

[0014] The high-speed frequency conversion and status monitoring control device uses the domestic chip GW1N-LV9PG256C6 / I5 as the main controller. It converts the received main control command frequency parameters through calculation, and changes the configuration of the six register parameters inside the BR9177 integrated phase-locked chip of the high-speed frequency conversion circuit through a three-wire interface. The frequency is quickly converted through the fractional frequency phase-locked loop circuit. At the same time, different attenuation values ​​are configured for the registers inside the serial-parallel digital controlled attenuator BR9153S of the power regulation circuit. The purpose of adjusting the RF output power is achieved by changing the RF channel attenuation value. The 8-bit fixed interval cyclic sampling is used to adjust the RF output power. The system monitors the status of the analog input signal of the power amplifier self-test, compares and calculates the forward and reverse analog voltage sampling values ​​of the power amplifier standing wave, and determines whether to enable the closed-loop protection function of the power amplifier. For the status monitoring of the other six analog voltages, the two-wire serial interface sends the sampling data to the FPGA main control circuit for analysis, calculation and closed-loop control processing. The status monitoring data is sent through the asynchronous serial port to realize status monitoring and alarm reporting. Software debugging commands are sent through the serial port to modify the circuit parameters of the JTM1907 crystal oscillator in the clock circuit, fine-tune the 28.8MHz output frequency of the reference clock, and then change the output frequency error of the high-speed frequency conversion circuit to meet the application requirements of specific scenarios.

[0015] The beneficial effects of the present invention compared with the prior art are:

[0016] This high-speed frequency conversion and status monitoring control device uses the domestic chip GW1N-LV9PG256C6 / I5 as the main controller and is designed and manufactured using domestically produced devices with independent and controllable technology. The BR9177's integrated phase-locked loop (PLL) features fractional frequency division, wide loop bandwidth, and high phase-detection reference comparison frequency, enabling fast locking during high-speed frequency conversion. The RF signal output frequency and power parameters are adjustable, extending the effective transmission time of channel steady-state information during rapid frequency conversion and achieving high channel information transmission efficiency. This makes it suitable as a test platform for exploring and researching key technologies for various high-speed frequency conversion communication equipment, mitigating key technology design risks and facilitating rapid application portability. The JAD7998 state monitoring circuit digitizes eight analog input signals, enabling closed-loop self-protection for high-power communication equipment power amplifiers, preventing damage caused by excessive reflected power due to antenna open-circuit faults or load mismatch. Temperature monitoring and sampling of analog channel voltage values ​​enable environmental adaptability and self-protection, while also enabling multi-channel status monitoring and alarm reporting. Power is adjusted synchronously during frequency parameter conversion, leveraging the overlap between the unstable phase-locked loop lock period and the channel link instability caused by power adjustment. This increases the effective transmission time of channel steady-state information during rapid frequency conversion, improving channel transmission efficiency and ensuring wide-band output power fluctuation indicators. By sending debug control commands through the serial port, the reference crystal oscillator clock output frequency error accuracy is modified, achieving fast frequency conversion speed, adjustable output frequency error accuracy and output power, real-time monitoring and reporting of equipment link status, and self-closed-loop protection of power amplifier faults. This solves the problems of low localization rate of existing technologies, slow frequency conversion speed, difficulty in fault location of status monitoring, and low channel transmission rate during rapid frequency conversion. It avoids the key technical design risks of broadband wireless high-power communication equipment such as high reflected power burning equipment due to power amplifier load mismatch and poor output power flatness, increases the effective duration of steady-state information transmission in the channel during high-speed frequency conversion, and effectively improves the reliability, maintainability, safety, self-testing and environmental adaptability of the device in combination with software control. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a block diagram of the working principle of the present invention;

[0018] Figure 2 This is a signal flow chart of the control software of the present invention;

[0019] FIG3 is a diagram of an FPGA master control circuit of the present invention;

[0020] Figure 3-1 It is a configuration diagram of the FPGA master control circuit of the present invention;

[0021] Figure 3-2 This is a control diagram of the FPGA master control circuit of the present invention;

[0022] Figure 3-3 This is a serial port control diagram of the FPGA master control circuit of the present invention;

[0023] Figure 3-4 This is a power supply configuration diagram of the FPGA master control circuit of the present invention;

[0024] Figure 3-5 It is a program loading diagram of the FPGA main control circuit of the present invention;

[0025] Figure 4 A clock circuit diagram of the present invention;

[0026] Figure 5 Serial port conversion circuit diagram of the present invention;

[0027] Figure 6 A high-speed frequency conversion circuit diagram of the present invention;

[0028] Figure 7 is a power regulation circuit diagram of the present invention;

[0029] Figure 8 is a state monitoring circuit diagram of the present invention;

[0030] Figure 9 is a power supply circuit diagram of the present invention;

[0031] Figure 10 This is the external interface circuit diagram of the present invention;

[0032] Figure 11 This is a timing diagram of reading the analog-to-digital conversion value of JAD7998 of the present invention;

[0033] Figure 12 This is the JAD7998 software driver code flow chart of the present invention;

[0034] Figure 13 This is a connection verification test diagram for the control device of the present invention;

[0035] Figure 14 This is a frequency parameter conversion online simulation data diagram of the present invention;

[0036] Figure 15 It is the analog channel sampling data and the power amplifier standing wave online simulation waveform diagram of the present invention;

[0037] Figure 16 This is a graph of measured data from the 8-channel status monitoring sampling serial port monitoring of the present invention;

[0038] Figure 17 This is a timing diagram of the attenuation waveform of the BR9153S attenuator of the present invention.

[0039] In the figure, 1. control device body, 2. FPGA main control circuit, 3. clock circuit, 4. serial port conversion circuit, 5. high-speed frequency conversion circuit, 6. power regulation circuit, 7. status monitoring circuit, 8. power supply circuit, 9. external interface circuit. DETAILED DESCRIPTION

[0040] The following is a further detailed description of the implementation of the high-speed frequency conversion and state monitoring control device with reference to the accompanying drawings (see Figures 1 to 17 ):

[0041] (See Figure 1 ), a high-speed frequency conversion and status monitoring control device, which includes a control device body 1, FPGA main control circuit 2, clock circuit 3, serial port conversion circuit 4, high-speed frequency conversion circuit 5, power regulation circuit 6, status monitoring circuit 7, power supply circuit 8 and external interface circuit 9. The corresponding module circuits are placed on the same printed circuit board. The circuit principle diagram corresponding to each part of the module circuit (see Figure 3~ Figure 10 ), FPGA main control circuit 2 control software signal flow chart (see Figure 2 ).

[0042] When the control device body 1 requires high-speed frequency conversion, the master control command containing the frequency parameters is sent to the FPGA master control circuit 2 through the three-way external master control command input interface. After the master control command is received, the extracted frequency parameters are processed by frequency conversion calculation and sent to the high-speed frequency conversion circuit 5. By changing the configuration bits of the integrated phase-locked circuit BR9177 register, the fractional-frequency phase-locked loop is quickly locked to output a stable radio frequency RF_IN signal. After the signal is attenuated by the digitally controlled gain attenuator of the serial-parallel digitally controlled attenuator BR9153S of the power regulation circuit 6, the required radio frequency power signal is output from the RF_OUT port. The frequency accuracy of the RF_OUT output signal is fine-tuned by sending control commands through the JTM_RX_232 serial port.

[0043] When the self-test monitoring device status is in progress, the 8-channel self-test monitoring analog input voltage is sent to the status monitoring circuit 7, which performs analog-to-digital conversion on the analog voltage of the current self-test channel, and the converted sampled data is sent to the FPGA main control circuit 2 for calculation and processing through the two-wire serial port; the sampled values ​​of the positive detection input voltage Vin1 and the reverse input voltage Vin2 of the power amplifier standing wave are compared and calculated. When the calculated and processed values ​​are abnormal, the FPGA main control circuit 2 controls the power amplifier standing wave protection function through the power amplifier standing wave protection output signal F_PTT; when the analog input voltage sampling value of the power amplifier temperature detection Vin3 channel exceeds the comparison threshold, the serial port F_TXD sends a temperature alarm status information. Similarly, when the analog input voltage sampling values ​​of other detection and monitoring channels Vin4 to Vin8 are abnormal, the abnormal status information is also sent out immediately through the serial port F_TXD to start the closed-loop protection or alarm display function of the corresponding channel, and the closed-loop protection or alarm display function of the corresponding channel is turned on.

[0044] The FPGA master control circuit 2 (see Figure 3-1 to Figure 3-3 ) of U1C, U1D, and U1E: F_JAD_SDA and F_JAD_SCL signals are respectively connected to the status monitoring circuit 7 (see Figure 8 )'s R204 and R203 resistors are connected;

[0045] Among them, F_TXD, F_RXD, JTM_RX, JTM_TX signals are respectively connected to the serial port conversion circuit 4 (see Figure 5 ) in which the resistors R138, R141, R142, and R145 are connected;

[0046] Among them, ATT_EN, ATT_DATA, ATT_CLK signals are respectively connected to the power regulation circuit 6 (see Figure 7 ) in which the resistors R193, R190, and R187 are connected;

[0047] Among them, F_CLK, F_DATA, F_LE, F_LD signals are respectively connected to the high-speed frequency conversion circuit 5 (see Figure 6 ) in which the resistors R186, R188, R191, and R185 are connected;

[0048] The JTM_TX and F_CLK signals are respectively connected to the clock circuit 3 (see Figure 4 ) in which the resistor R158 and the inductor L8 are connected;

[0049] FPGA_LE, FPGA_DATA, FPGA_CLK, and F_PTT are connected to the external interface circuit 9 (see Figure 10 ) are connected to pins 13, 12, 10, and 40 of the XP1 socket.

[0050] For the external interface properties of the external interface circuit 9, the signal definitions of the pins, and where the pins are connected, please refer to the external interface signal table 1.

[0051] Table 1 External interface signal table

[0052]

[0053] FPGA main control circuit 2 (see Figure 3-1 to Figure 3-5 ) consists of FPGA control circuit, JTAG simulation download circuit, data storage circuit, and Flash program loading circuit; the FPGA control circuit U1 uses Guangdong Gaoyun's GW1N-LV9PG256C6 / I5 programmable logic gate array as the core key component, and its working principle block diagram and control software signal flow chart (see Figures 1 and 2 ).

[0054] Gowin_V1.9.9 (64-bit) integrates development and compilation environment, functional simulation, and execution program download. It is powerful and convenient for software program download and simulation. It is self-controlled. The JTAG simulation download circuit is used to download the execution code to the Flash program loading circuit (see Figure 3-5 U2 is the program memory for the FPGA master circuit. It's a 64Mb Flash memory provided by GigaDevice. Download the executable program to U2 using the GOWIN USB Cable. After powering on, the executable program is loaded from U2 into FPGA master circuit 2 and begins running. The internal BRAM resources of FPGA master circuit 2 are used during online simulation or debugging, and the U2 program memory is inactive during this time. Using the JTAG emulation download circuit's online simulation function to quickly verify software code design accuracy and output waveforms meet design expectations.

[0055] The data storage circuit U3 is used to store and read various required data parameters; after the FPGA master control circuit 2 converts the level through the serial port conversion circuit 4, it receives the master control debugging command and sends the status information and exchanges information through two sets of external asynchronous serial interfaces; by extracting the frequency parameters of the 3-way external master control command input and performing frequency conversion calculation processing, the frequency configuration register parameters are sent to U13 in the high-speed frequency conversion circuit 5 to achieve fast frequency locking conversion, and the power attenuation setting parameters are sent to the power regulation circuit 6 to adjust the attenuation of the RF channel of the attenuator U12 to achieve power size adjustment; through I 2 The C two-wire interface is set to write the 8-channel self-test monitoring status input channel selection configuration register, read the sampling value of the current analog-to-digital conversion channel, and cyclically detect and sample the 8-channel self-test monitoring status input at a certain interval. The sampling value is sent to the FPGA main control circuit 2 for calculation and processing, and the corresponding power amplifier standing wave closed-loop protection and status monitoring data reporting functions are enabled.

[0056] Clock circuit 3 (see Figure 4 ) The JTM1907 temperature-compensated crystal oscillator in U8 fine-tunes the clock output frequency through the built-in RXD serial port input control commands to improve the error accuracy of the 28.8MHz reference clock.

[0057] The RXD pin 7 of U8 is connected to the R142 resistor in the serial port conversion circuit 4 through the R160 resistor. The square wave output signal F_CLK of the 2nd pin of U8 is suppressed by the LC low-pass filter (L8, L9, C30, C31, C32) to suppress the harmonics and noise. The output 28.8MHz signal is connected to the R180 in the high-speed frequency conversion circuit through the capacitor C29. At the same time, the F_CLK signal is sent to the FPGA main control circuit 2 (see Figure 3-1 ) at resistor R61; clock circuit 3 mainly provides a high-precision reference input clock for the GW1N-LV9PG256C6 / I5 and BR9177 integrated phase-locked circuit chip.

[0058] Serial port conversion circuit 4 (see Figure 5 ) In U7, the SM3232EEUE level converter is used to convert RS232 levels to LVCMOS 3.3V levels.

[0059] The RXD232 and TXD232 in the external interface circuit 9 adapt the interface levels of the C7 and B5 pins of U1D in the FPGA main control circuit 2 through the U7 level;

[0060] JTM_RX_232 in the external interface circuit 9 matches the 7-pin interface level of U8 in the clock circuit 3; realizes 8-way self-test monitoring status and alarm information reporting, and sends the external asynchronous serial interface debug control command to the FPGA main control circuit 2 or the reference clock circuit 3.

[0061] High-speed frequency conversion circuit 5 (see Figure 6 ) consists of a BR9177 integrated phase-locked circuit, a third-order loop filter, and a radio frequency transformer conversion circuit.

[0062] The three-wire data interfaces F_CLK, F_DATA, and F_LE of the FPGA master control circuit 2 are connected to R186, R188, and R191 in the BR9177 integrated phase-locked circuit.

[0063] Six register configuration parameters are input through the three-wire data interface to change the configuration data of the associated registers within the BR9177 integrated phase-locked circuit to achieve rapid frequency conversion and locking. The third-order loop filter is composed of resistor and capacitor components C57, C58, C60, R194, and R195. The loop filter bandwidth is changed by adjusting the resistor and capacitor parameters. The wider the bandwidth, the faster the locking frequency and the weaker the spurious phase noise suppression capability, making it suitable for applications with rapid frequency switching. The narrower the bandwidth, the slower the locking frequency but the stronger the spurious phase noise suppression capability, making it suitable for fixed frequency applications.

[0064] U15 in the RF transformer conversion circuit is mainly used to match the differential RF output into a single-ended RF output signal. U13 in the BR9177 integrated phase-locked circuit integrates the fractional-N fast-locking PLL of the voltage-controlled oscillator VCO, combined with an external third-order loop filter and an external reference 28.8MHz input clock to realize the fractional-N or integer-N phase-locked loop PLL frequency synthesizer function. By selecting the fractional-N configuration to achieve fast locking, the locking time is only 40us under a loop bandwidth of 120K, which is particularly suitable for use in fast frequency conversion systems.

[0065] The BR9177 has an internal integrated VCO with a fundamental output frequency range of 1.62GHz to 3.24GHz. Through 1 / 2 / 4 / 8 / 16 / 32 / 64 frequency division circuits, it generates an RF output frequency of 25.5MHz to 3240MHz. All on-chip registers are controlled through a standard serial peripheral interface. Register 0 is mainly used to set the charge pump current and feedback the integer part INT of the frequency division coefficient. It is used in the formula RF OUT =[INT+(FRAC / MOD)]×F pfd / RF divider, where RF OUT is the RF output frequency, INT is the integer division coefficient, FRAC is the fractional division coefficient, MOD is the modulus, F pfd is the phase detector frequency, F pfd =28.8MHz / FREF_DIV, FREF_DIV is the reference clock frequency division configuration value, and the RF divider is the RF output frequency division number of the VCO.

[0066] The RF divider divides the VCO RF divider from 1 to 64. The FRAC setting bits DB[23:0] in register 1 are used to set the numerator value of the fractional input. This, in conjunction with the denominator MOD value of the fractional input, implements the feedback of the fractional portion of the frequency division coefficient.

[0067] The MOD modulus setting bits DB[24:0] of register 2 are used to set the denominator modulus value of the SDM fractional input. When the MOD modulus setting bits DB[24:0] = 25'd10000000, the SDM output random sequence has a strong periodicity, resulting in good phase noise performance and poor fractional spurious performance. When the MOD modulus setting bits DB[24:0] = 25'd16777216, the SDM output random sequence has a poor periodicity, resulting in good fractional spurious performance and poor phase noise performance.

[0068] The VCO selection setting bit DB

[24] in register 3 is used to select the VCO for different RF band outputs. When 1620MHz≤RF output frequency<2400MHz, the low-band VCO is selected; when 2400MHz≤RF output frequency≤3240MHz, the high-band VCO is selected.

[0069] The reference pre-scaling setting bits DB[20:7] of register 4 are used to pre-divide the input reference clock frequency 28.8MHz by FREF_DIV to meet the input frequency F pfd The VCO RF divider setting bits DB[6:0] in register 4 are used to divide the RF output frequency by 1 to 64, and the frequency band range can be widened by changing the RF divider parameters.

[0070] The phase-detection delay enable setting bit DB[4] of register 5 is used to optimize the fractional mode phase noise. When the frequency division ratio is in fractional mode, DB[4] is set to 1 for the phase-locked loop fast lock mode setting. When 4.7uF, 0.1uF, and 0.01uF capacitors are placed on the power pins in sequence to filter out the interference on the power line to the maximum extent and after power is turned on normally, the BR9177 integrated phase-locked circuit completes the configuration according to the register sequence shown below: register 5 → register 4 → register 3 → register 2 → register 1 → register 0. The RF is extracted according to the FPGA main control circuit. OUT The frequency value is calculated by the formula to obtain the configuration value of each register, and is sent to the corresponding register respectively, and the high-speed frequency conversion is realized through the fractional frequency phase-locked loop.

[0071] Power regulation circuit 6 (see Figure 7 ) consists of a U12 serial-parallel digital controlled attenuator BR9153S and peripheral circuits. The FPGA main control circuit is connected to R187, R190, and R193 of the U12 serial-parallel digital controlled attenuator BR9153S through the ATT_CLK, ATT_DATA, and ATT_EN three-wire serial input control signal interface. The FPGA main control circuit controls the attenuation value of the register in the serial-parallel digital controlled attenuator BR9153S through the three-wire serial control interface to achieve RF channel gain adjustment.

[0072] The serial-parallel digital controlled attenuator BR9153S is a wideband 6-bit serial / parallel digital controlled attenuator chip designed with GaAs technology, covering the frequency range of DC to 8GHz, achieving an attenuation step of 0.5dB, an attenuation range of 0.5-31.5dB, and a typical insertion loss of 1.2dB. The 6-bit control pins represent 0.5, 1, 2, 4, 8, and 16dB attenuation respectively. When each attenuation control bit is controlled at a low level, a full attenuation state of 31.5dB is achieved; the serial-parallel digital controlled attenuator BR9153S chip dual-mode control interface is compatible with CMOS / TTL and supports three-wire serial input control. When P / S is high, SPI operation is valid, and the 6-bit serial data is loaded with the MSB first. The rising edge triggers the clock CLK and LE to be cleared and converted. The 6-bit serial data is sequentially sent to the register and output to the attenuator to adjust the power of the RF signal generated by the high-speed frequency conversion circuit 5. While the FPGA main control circuit 2 transforms the frequency parameters of the high-speed frequency conversion circuit 5, the power attenuation channel is adjusted synchronously, making full use of the overlapping of the unstable time period of the phase-locked loop fast locking and the unstable time of the channel link caused by the power adjustment, thereby increasing the effective time of the channel steady-state information transmission during rapid frequency change and ensuring the index range of the wide-band output power fluctuation.

[0073] State monitoring circuit 7 (see Figure 8 ) consists of U14 and peripheral resistor-capacitor components, among which Vin1~Vin8 in the external interface circuit 9 are connected to the corresponding pins of U14 through resistors R214, R215, R216, R217, R222, R223, R225, and R224 respectively; the F_JAD_SDA and F_JAD_SCL signals in U1C in the FPGA main control circuit 2 are connected to U14 through resistors R204, R203.

[0074] U14 uses the analog-to-digital converter JAD7998 from the 58th Research Institute of China Electronics Technology Group Corporation; JAD7998 is an 8-channel, 12-bit, high-speed, low-power, successive approximation ADC that operates on a single 2.7V to 5.5V power supply, has a conversion time of 2 microseconds, a reference input voltage range from 1.2V to the power supply voltage, and an analog input voltage range from 0V to the reference voltage. The package is CLCC20; the JAD7998 device has a built-in 8-channel multiplexer and sample-and-hold amplifier, and provides an I2C-compatible two-wire serial interface.

[0075] (See Figure 8 ), Figure 8It is primarily used for loop detection and sampling of analog voltages for self-test monitoring status on 8 channels, converting analog DC voltages into digital signals. The data signals obtained from the 8-channel analog channel voltage sampling are sent to the FPGA master control circuit for processing via the shared clock line F_JAD_SCL and data line F_JAD_SDA. F_JAD_SDA is a bidirectional data port, also used to configure the JAD7998 channel selection input register data. Vin1 channel 1 is the forward standing wave analog voltage input for the power amplifier, Vin2 channel 2 is the reverse standing wave analog voltage input for the power amplifier, and Vin3 channel 3 is the temperature detection analog voltage input for the power amplifier. The remaining five channels, Vin4 through Vin8, are used for the external interface's other five self-test monitoring analog voltage status inputs.

[0076] FPGA_AS_JAD is used to select and address the JAD7998 device. This IO pin is configured to be fixed at a high level. The JAD7998 write device address is 8'H48, and the read device address is 8'H49. The 8 analog input channels are selected by sending one of the 8 byte data groups 8'H80, 8'H90, 8'HA0, 8'HB0, 8'HC0, 8'HD0, 8'HE0, and 8'HF0 to the COMMAND / ADDRESS POINT BYTE configuration register to select the channel. When the configuration register configuration data is 8'H80, the Vin1 channel is selected. When the configuration data is 8'HF0, the Vin8 analog channel is selected, and so on.

[0077] By using a fixed interval sequential cycle scan to change the 8-channel configuration register value, the 8-way analog channel sampling data is obtained. The fixed interval sequential cycle configuration data is achieved by adjusting the timer duration; read the JAD7998 analog-to-digital conversion value timing diagram (see Figure 11 ), where 7-BIT ADDRESS+W is filled with 8'H48 to write the device address, and 7-BIT ADDRESS+R is filled with 8'H49 to read the device address. FIRST_DATA_BYTE (MSBS) reads the upper 8 bits of the sampled data, and SECOND_DATA_BYTE (LSBS) reads the lower 8 bits of the sampled data. The upper four bits in FIRST_DATA_BYTE represent the number of analog channels, 0 represents the Vin1 channel, and 7 represents the Vin8 channel. The lower four bits in FIRST_DATA_BYTE and the lower 8 bits of SECOND_DATA_BYTE together constitute the 12-bit analog voltage sampling value. The JAD7998 software driver code flow chart (see Figure 12 ).

[0078] The standing wave protection function software of the power amplifier is calculated and processed, and the following formula is used: (vol_vf_buf7998-vol_vr_buf7998)×data=vol_vf_buf7998+vol_vr_buf7998 to calculate the standing wave reverse protection voltage start value.

[0079] vol_vf_buf7998 standing wave forward channel Vin1 samples 12-bit data value, vol_vr_buf7998 standing wave reverse channel Vin2 samples 12-bit data value, when COMMAND_ADDRESS_POINT_BYTE=X"A0", vol_vf_buf7998[11:8]<=FIRST_DATA_BYTE[3:0], vol_vf_buf7998[7:0]<=SECOND_DATA_BYTE[7:0];

[0080] When COMMAND_ADDRESS_POINT_BYTE =

[0081] The data value ranges from 2 to 20, and is used to set the amplifier's reverse standing wave voltage threshold. Smaller data values ​​lower the threshold voltage, while larger data values ​​increase the threshold voltage. The data value is determined based on the amplifier's reverse standing wave analog voltage. When the reverse voltage exceeds the threshold, the amplifier enters protection mode. For example, if data is 5 and the amplifier's forward standing wave voltage is 1.2V, then vol_vf_buf7998 = (1.2V ÷ 3.3V) × 4096 = 1493. Substituting this value into (1493 - vol_vr_buf7998) × 5 = 1493 + vol_vr_buf7998 yields vol_vr_buf7998 = 995. This data is then converted to an analog voltage of (995 ÷ 4096) × 3.3 = 0.8V. Theoretically, short-circuit protection is activated when the amplifier's reverse standing wave voltage exceeds 0.8V; otherwise, the amplifier operates normally.

[0082] kd_state_tmp represents the standing wave protection status flag of the power amplifier. When the power amplifier is in the transmitting state, if the positive and negative standing wave protection calculation results make kd_state_tmp<='0', the power amplifier enters the standing wave protection state. Otherwise, when kd_state_tmp<='1' is detected, the power amplifier enters the normal working state. The main codes for the power amplifier standing wave protection software calculation and processing are as follows: if vol_vf_buf7998>vol_vr_buf7998 thenif(vol_vf_buf7998-vol_vr_buf7998)×data=vol_vf_buf7998+vol_vr_buf7998

[0083] then kd_state_tmp<='1'; else kd_state_tmp<='0'; end if; end if;

[0084] The calculation and processing of the forward and reverse voltage sampling data of the power amplifier standing wave is mainly used to protect the power amplifier from being burned out by the high power transmission when the standing wave of the power amplifier is too large; similarly, the input analog voltage of the other 6 self-test monitoring analog voltage status is monitored and analyzed. When the analog voltage of a certain channel is detected and scanned as abnormal, a fault alarm and control signal are issued to achieve software reliability protection and real-time reporting and monitoring of the working status of multiple power supplies.

[0085] The power amplifier standing wave protection software design is implemented using a 3-bit state machine cyclic detection. It enters state 1 by default when reset. When the reference clock 28.8MHz rises, the current channel data sampling end flag configured in the JAD7998 analog-to-digital conversion circuit software driver code program is detected. When the sampling end flag is valid, it enters state 2. When it is invalid, it continues to detect state 1. In state 2, the sampling value read from the channel is compared with the channel judgment standard value based on the value of the currently configured channel register COMMAND_ADDRESS_POINT_BYTE. If the sampled value read is greater than the standard value, the channel is judged to be working normally, otherwise it is judged to be working abnormally.

[0086] The present invention uses JAD7998(n)<='1' to indicate that the channel is normal, and JAD7998(n)<='0' to indicate that the channel is faulty, wherein n represents the current working channel. When JAD7998(n)<='1' of 8 channels are all 1, it is determined that the 8-way self-test monitoring status inputs are normal. In other cases, it is determined that the 8-way self-test monitoring status inputs are faulty and the system jumps to state 3. After a certain delay, state 3 enters state 1, thereby realizing a self-test cycle scan of the 8-way self-test monitoring status.

[0087] The abnormal analog voltage input channel can be quickly located through the JAD7998(n)<='0' flag, the power alarm protection function can be enabled, and the fault power monitoring point can be reported.

[0088] Power supply circuit 8 (see Figure 9 ) consists of two ultra-low voltage difference linear JS74401 regulators U5 and U6 and peripheral circuits. One output is 1.2V, and the output voltage accuracy is fine-tuned by resistors R131 and R133; the other output is 3.3V, and the 3.3V output voltage accuracy is fine-tuned by resistor R137. It supplies power to all circuit modules that require DC power, and sends a +3.6V DC power supply to the input pins of the L10 and L5 ferrite beads from pin 7 of the external interface circuit 9.

[0089] External interface circuit 9 (see Figure 10 ) consists of the connector DS-SFM-125-02-LDA and multiple sensing components. The external interface circuit 9 has external interface properties, pin signal definitions, and where the pins are connected. Please refer to the external interface signal table 1. It is used for connection, interaction, joint debugging, control and status monitoring with external interface signals.

[0090] The following is the main components and material composition of this control device Table 2

[0091] Serial number Name Model Required dosage Remark 1 Unit printed circuit board 1 2 GW1N-LV9PG256C6 / I5 1 BGA256, Guangdong Gowin Semiconductor 3 GD25Q64CSIG 1 SOP-8, GigaDevice 4 JAD7998 1 CLCC20, China Electronics 58th Research Institute 5 SM3232EEUE 1 CSOP16, Shenzhen SMIC Co., Ltd. 6 JS74401 2 DFN20, China Electronics 58th Research Institute 7 TC1-26-1 1 S08, Chengdu Yaguang 8 JTM1907 1 10-pin SMD, Shanghai Hongye Electronics 9 DS-sFM-125-02-LDA 1 Mianyang Dise 10 BR9153S 1 QFN24, Xi'an Borui Jixin 11 BR9177 1 QFN32, Xi'an Borui Jixin

[0092] Control software signal flow chart (see Figure 2 ) mainly realizes the detection and reception of external interface master control commands, extraction of frequency power attenuation status monitoring and control processing, frequency conversion calculation processing, integrated phase-locked circuit BR9177 register configuration, power attenuation parameter conversion, serial-parallel digital attenuator BR9153S attenuator parameter configuration, analog-to-digital conversion circuit JAD7988 channel selection register configuration, reading of configuration channel analog-to-digital conversion sampling values, status monitoring and identification processing, serial port transceiver processing and power amplifier standing wave closed-loop protection function.

[0093] The working process and specific embodiment of the high-speed frequency conversion and state monitoring control device are as follows:

[0094] For specific embodiments, see Figures 1 to 17 , see Table 2 for main device materials;

[0095] Figure 1 The control device body 1 is composed of the module circuits corresponding to the FPGA main control circuit 2, clock circuit 3, serial port conversion circuit 4, high-speed frequency conversion circuit 5, power regulation circuit 6, status monitoring circuit 7, power supply circuit 8 and external interface circuit 9 placed on the same printed circuit board. The circuit schematic diagram corresponding to each part of the module circuit is shown in Figure 3~ Figure 10 .

[0096] Prepare FSP spectrum analyzer, UT61F multimeter, DC regulated power supply, USB2.0-RS232 serial cable, GOWIN USB Cable download emulator, test cable, PC, SSCOM3.2 debugging assistant, Gowin_v1.9.9 (64-bit) software compilation environment, and connect the control device according to the verification test diagram (see Figure 13 ) to connect.

[0097] First, perform a safety check on the control device body 1 to confirm that the device soldering is intact and to check for short circuits or cold solder joints. If the inspection passes, supply +3.6V DC power to pin 7 of the control device XP1 socket through a DC regulated power supply. Input the test DC voltage to Vin1-Vin8. Set the baud rate of the SSCOM3.2 serial port debugging assistant to 115200bps, data bits to 8, and stop bits to 1, and enter the configured Gowin Analyzer Oscilloscope waveform online simulation interface.

[0098] The serial port debugging assistant SSCOM3.2 first sends a verification example. The 180.825MHz frequency parameters, power attenuation and other master control commands are sent through the TXD232 port. Through JTAG online simulation, it is found that INT16B = 0x64 = 0d100, FRAC24B [23:0] = 0x755555 = 0d7689557; the frequency conversion circuit output frequency is equal to: RF OUT =[INT16B+(FRAC24B / MOD)]×F pfd / RF divider = (100 + 7689557 / 16777216) × 28.8 / 16 = 180.825MHz, where the RF divider selects 16-division of the RF output, MOD is a fixed value of 16777216, and F pfd The reference frequency is 28.8MHz and divided by 1. Figure 14 ), Figure 14 This is the online simulation data diagram of frequency parameter transformation. The FSP spectrum analyzer is used to measure the frequency of RF_OUT at pin 25 of the XP1 socket to be 180.82495MHz. At this time, the fine-tuning frequency control command is sent through the JTM_RX_232 serial port. The spectrum analyzer observes the change of the RF_OUT port frequency as the fine-tuning frequency control command changes. When the spectrum analyzer outputs 180.825MHz, the save control command is sent, and the output frequency is maintained at 180.825MHz. The FPGA control software program sends a 6-bit 101111 register parameter configuration to the attenuator BR9153S. The reference insertion loss of this value is 8dB (see Figure 7 )exist Figure 7The power of the C51 output RF_OUT port and the RF_IN input port C55 were tested by FSP spectrum analyzer. The difference between the two was 8.2dB. The waveform timing diagram of the attenuation of the BR9153S attenuator (see Figure 17 ).

[0099] Analog channel sampling data and amplifier standing wave online simulation waveform (see Figure 15 ) shows the simulated waveform sampling data value 0x64D7 when the analog voltage of channel 7 is 1.0V. The 8-channel analog-to-digital conversion channel cycle sampling data is measured using the serial port RXD232 (see Figure 16 ) displays 0x64D8, 0x64D9, 0x64DA, etc. Theoretically, the 12-bit analog-to-digital conversion sampling value is equal to (V in ÷V refi )×2 12 , that is (1.0÷3.286)×2 12 =d1246=0x4DE. Since the upper four bits of the upper 8-bit byte of the 7th channel Vin7 are fixed at 0x6, the theoretical calculated value is 0x64DE. At the same time, when a fixed voltage value is input to the 1st channel Vin1 and the analog voltage input to the 2nd channel Vin2 changes above and below the threshold, the power amplifier standing wave state parameter flag kd_state_tmp also flips between 0 and 1. When testing the XP1 socket 40 pin with a multimeter, the output F_PTT also flips between high and low levels as the Vin2 input analog voltage fluctuates above and below the threshold.

[0100] During actual circuit verification, the standing wave forward input voltage Vin1 is fixed at 1.2V, and the standing wave reverse input voltage value is gradually changed. When the voltage value is greater than 0.8V, F_PTT is 0, and when the voltage value is less than 0.8V, F_PTT is 3.3V. The sampling values ​​of the 8 analog-to-digital conversion channels are displayed in sequence. The gray part of the following data 70 F1 01DB 10F9 25D4 30F9 41 7A 5190 64 D8 70 F1 01 D1 indicates that the sampling analog-to-digital conversion channels Vin8, Vin1, Vin2...Vin8, Vin1 are sampled in sequence according to a certain period. For example, 5D4 in 25D4 indicates that the current input voltage value of the third channel Vin3 is 1.2V. 51 8E 64DA 70 F1 02 46 10 F9 25 D4 30 F9 41 7E 51 8F 64 D9 70 F1 02 45 10 F925 D4 30 F9 41 7B 51 8E 64 D8 70 F1 02 25 10 F9 25 D4 30 F9 41 7F 51 8F 64 DA shows the fixed voltage sampling value of Vin7 of channel 7. The value of each analog-to-digital conversion is slightly different.

[0101] The above 1.0V is the analog input voltage value of the 7th channel Vin7, and 3.286V is the actual test voltage value of REFI, the 6th pin of JAD7998. After comparison and verification, the actual serial port output value is equal to or very close to the theoretical calculated value and the JTAG online software simulation result, achieving the expected effect of the design.

[0102] The control device body (1) is designed with domestically produced components to achieve rapid frequency conversion, adjustable output frequency error accuracy and output power, real-time monitoring and reporting of device link status, self-closed-loop protection of power amplifier faults, synchronous adjustment of frequency parameter conversion and power attenuation, and increased effective duration of steady-state information transmission of the channel during rapid frequency conversion, ensuring a wide-band output power fluctuation range index, and effectively improving the transmission efficiency of the channel during rapid frequency conversion. The problem of low domestic production rate, slow frequency conversion speed, difficulty in fault location of status monitoring, and low transmission rate of useful information of the channel during rapid frequency conversion of existing corresponding devices is solved.

[0103] This high-speed frequency conversion and status monitoring control device, as a test platform for exploring and tackling key technologies of various high-speed frequency conversion communication equipment, avoids key technical design risks such as large reflected power that can easily burn equipment and poor output power flatness caused by power amplifier load mismatch in broadband wireless high-power communication equipment. Through status monitoring and closed-loop control, it effectively improves working reliability, maintainability, safety, testability and environmental adaptability, fully meeting the high standards required for specific application scenarios.

[0104] The above description is only a preferred embodiment of the present invention. The above examples do not impose any form of limitation on the essential content of the present invention. After reading this specification, ordinary technicians in the relevant technical field make any simple modifications or deformations to the above specific implementation methods based on the technical essence of the present invention, as well as equivalent embodiments that may be changed or modified into equivalent changes using the technical content disclosed above, all fall within the scope of the technical solution of the present invention and do not deviate from the essence and scope of the present invention.

Claims

1. A frequency conversion and state monitoring control device, comprising a control device body (1), an FPGA main control circuit (2), a clock circuit (3), a serial port conversion circuit (4), a frequency conversion circuit (5), a power regulation circuit (6), a state monitoring circuit (7), a power supply circuit (8) and an external interface circuit (9); characterized in that: The control device body (1) is composed of an FPGA main control circuit (2), a clock circuit (3), a serial port conversion circuit (4), a frequency conversion circuit (5), a power regulation circuit (6), a state monitoring circuit (7), a power supply circuit (8) and an external interface circuit (9), and is placed on the same printed circuit board; the FPGA main control circuit (2) is composed of an FPGA control circuit, a JTAG simulation download circuit, a data storage circuit, and a Flash program loading circuit; the clock circuit (3) is composed of a JTM1907 and its peripheral devices; the serial port conversion circuit (4) is composed of an SM3232EEU The system is composed of an E signal transceiver and resistors and capacitors; a frequency conversion circuit (5) is composed of a BR9177 integrated phase-locked circuit, a third-order loop filter, and a radio frequency transformer conversion circuit; a power regulation circuit (6) is composed of a serial-parallel digital controlled attenuator BR9153S and peripheral circuits; a state monitoring circuit (7) is composed of an analog-to-digital conversion circuit JAD7998 and peripheral resistor and capacitor components; a power supply circuit (8) is composed of two ultra-low voltage difference linear JS74401 regulators and peripheral circuits; an external interface circuit (9) is composed of a connector DS-SFM-125-02-LDA and multiple sensor and capacitor components; When the frequency needs to be converted at high speed, the external master control command is sent to the FPGA master control circuit (2). After the master control command is received, the extracted frequency parameters are processed by frequency conversion calculation and sent to the frequency conversion circuit (5). By changing the configuration bits of the relevant registers of the integrated phase-locked circuit BR9177, the fractional frequency phase-locked loop is quickly locked to generate a stable radio frequency RF_IN signal. After the signal is attenuated by the digital control gain attenuator of the power regulation circuit (6), the radio frequency power signal of the required frequency is output from the RF_OUT port. The frequency accuracy of the RF_OUT output signal is fine-tuned by sending debugging commands through the JTM_RX_232 serial port. At the same time, the 8-way The analog input voltages Vin1 to Vin8 of the self-test monitoring state are sent to the state monitoring circuit (7) for analog-to-digital conversion, and the sampled data after the analog-to-digital conversion is sent to the FPGA main control circuit (2) for calculation and comparison processing; when the comparison result of the sampled values ​​of the forward detection input voltage Vin1 and the reverse input voltage Vin2 of the power amplifier standing wave is abnormal, the F_PTT output signal starts the power amplifier standing wave protection function; when the sampled values ​​of the analog input voltage of the power amplifier temperature detection channel Vin3 and the analog input voltages of other monitoring state channels Vin4 to Vin8 are abnormal, the abnormal state information is sent out through the serial port F_TXD, and the closed-loop protection or alarm display function of the corresponding channel is started.

2. A frequency conversion and state monitoring control device according to claim 1, characterized in that: The FPGA master control circuit (2) realizes master control command detection and reception, frequency conversion calculation processing, integrated phase-locked circuit BR9177 register configuration, power attenuation parameter conversion, serial-parallel digital controlled attenuator BR9153S attenuator parameter configuration, analog-to-digital conversion circuit JAD7988 channel selection register configuration, reading configuration channel analog-to-digital conversion sampling value, state monitoring identification processing, serial port transceiver processing and amplifier standing wave closed-loop protection functions, and simultaneously realizes JTAG online program simulation, execution program power-on loading, program download and storage of various data parameters required for reading.

3. The frequency conversion and state monitoring control device according to claim 1, characterized in that: The clock circuit (3) provides a reference clock for the FPGA control circuit and the integrated phase-locked circuit BR9177.

4. A frequency conversion and state monitoring control device according to claim 1, characterized in that: The serial port conversion circuit (4) realizes data interaction of 8-way self-check monitoring status and alarm information reporting, and receiving debugging control commands through mutual conversion between two groups of RS232 levels and LVCMOS3.3V levels.

5. The frequency conversion and state monitoring control device according to claim 1, characterized in that: The frequency conversion circuit (5) is composed of a BR9177 integrated phase-locked circuit, a third-order loop filter, and a radio frequency transformer conversion circuit. By changing the parameter configuration of six registers inside the integrated phase-locked circuit BR9177, frequency locking of fractional frequency division is achieved.

6. The frequency conversion and state monitoring control device according to claim 1, characterized in that: The power regulation circuit (6) is composed of a 6-bit serial-parallel digital controlled attenuator BR9153S and peripheral resistor and capacitor components. The attenuation value of the register in the serial-parallel digital controlled attenuator BR9153S is controlled through a three-wire serial interface to achieve radio frequency channel gain regulation.

7. The frequency conversion and state monitoring control device according to claim 1, characterized in that: The state monitoring circuit (7) is composed of an 8-channel analog-to-digital conversion circuit JAD7998 and peripheral components, and realizes digital conversion of 8-channel analog signals through fixed-cycle detection and sampling.

8. The frequency conversion and state monitoring control device according to claim 1, characterized in that: The power supply circuit (8) is composed of two ultra-low voltage difference linear JS74401 regulators and peripheral circuits, and provides the required direct current to all circuit modules.

9. The frequency conversion and state monitoring control device according to claim 1, characterized in that: The external interface circuit (9) is composed of a connector DS-SFM-125-02-LDA and a plurality of sensing components, and is used for connection, interaction, joint debugging, control and status monitoring with external interface signals.

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