Dedicated management network port connection system, physical layer chip management method, equipment, product and medium

Abstract

The present application discloses a dedicated management network port connection system, a physical layer chip management method, equipment, product and medium, and relates to the field of computer technology. The system includes: a security control module board and a main board provided with a first connector, the security control module board is provided with a management device and a first physical layer chip connected thereto; and the system also includes: an input-output board installed on the front panel of the server chassis, the input-output board is provided with a target socket of a dedicated management network port of the management device, a second physical layer chip and a second connector; wherein the first physical layer chip utilizes a serial communication bus and is connected in series with the second physical layer chip on the input-output board through a connector; and the management device on the security control module board controls the first physical layer chip and the second physical layer chip through several management buses. The technical solution of the present application can solve the problem that some current sockets do not meet the circuit design specifications.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a dedicated management network port connection system, a physical layer chip management method, equipment, product and medium. Background Art

[0002] The dedicated management network port of BMC (Baseboard Management Controller) refers to the network interface provided on the server motherboard specifically for BMC, which is used to remotely monitor and manage the server hardware status. This dedicated management network port is usually independent of the main network interface of the server. Even if the server operating system crashes or fails to start, the administrator can still remotely access the server through the dedicated management network port of BMC for management and troubleshooting.

[0003] The BMC dedicated management network port relies on the PHY (Physical Layer) chip to implement its physical layer functions to ensure effective data transmission and smooth management operations. Figure 1 The figure shows a hardware design diagram for managing the PHY chip through the BMC. Usually, the RJ45 socket of the dedicated management network port is placed on the SCM (Secure Control Module) board to directly connect to the PHY chip. However, the RJ45 may cause electromagnetic interference to the circuit. Since some GPU (Graphics Processing Unit) manufacturers have relatively high hardware circuit requirements, their hardware design standards cannot be met. Therefore, how to provide a solution to the above technical problems is a problem that technicians in this field currently need to solve. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a dedicated management network port connection system, a physical layer chip management method, equipment, product and medium, which can solve the problem that some sockets of the dedicated management network port do not meet the circuit design specifications. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses a dedicated management network port connection system, including a security control module board and a main board provided with a first connector, wherein the security control module board is provided with a management device and a first physical layer chip connected to the management device; and the dedicated management network port connection system further includes:

[0006] An input-output board installed on the front panel of the server chassis, wherein the input-output board is provided with a target socket of the dedicated management network port of the management device, a second physical layer chip and a second connector; wherein the first physical layer chip on the security control module board is connected in series with the second physical layer chip on the input-output board through the first connector and the second connector in sequence using a serial communication bus; the first connector and the second connector are connectors supporting preset high-density storage connections; the target socket is a socket capable of generating electromagnetic interference to the security control module board;

[0007] Furthermore, the management device on the security control module board controls the first physical layer chip and the second physical layer chip through a plurality of management buses.

[0008] Optionally, the management device on the security control module board is connected to the first physical layer chip via a reduced gigabit media independent interface bus.

[0009] Optionally, the first physical layer chip on the security control module board is connected in series with the second physical layer chip on the input and output board via the first connector and the second connector in sequence using a serial Gigabit Media Independent Interface bus.

[0010] Optionally, the management device on the security control module board controls the first physical layer chip and the second physical layer chip through a plurality of management data input and output buses.

[0011] Optionally, the management device is used to control the transmission rates of the first physical layer chip and the second physical layer chip.

[0012] Optionally, the management device is used to use the management bus to set the first physical layer chip and the second physical layer chip to a rate self-matching mode to achieve transmission rate control.

[0013] Optionally, the management device is used to obtain a transmission rate setting parameter of the second physical layer chip, and use the management bus to set the transmission rate setting parameter to the transmission rate of the first physical layer chip to achieve transmission rate control.

[0014] Optionally, the management device is connected to the first physical layer chip using a first management bus, and is connected to the second physical layer chip using a second management bus and sequentially through the first connector and the second connector; wherein the first management bus and the second management bus are connected based on a multi-function single board multiplexing resistor;

[0015] Based on the multi-functional single board multiplexing resistor, the first target position is reserved without resistor, so that the link between the management device and the second physical layer chip is in a disconnected state; wherein, when controlling the physical layer chip, the management device sends a first control command to the first physical layer chip through the first management bus, and sends a second control command to the second physical layer chip through the first management bus, so that the management device controls the first physical layer chip and the second physical layer chip respectively through one management bus and based on different control commands.

[0016] Optionally, the management device is connected to the first physical layer chip using a third management bus, and is connected to the second physical layer chip using a fourth management bus and sequentially through the first connector and the second connector; wherein the third management bus and the fourth management bus are connected based on a multi-function single board multiplexing resistor;

[0017] Based on the multi-functional single board multiplexing resistor, the second target position is reserved without resistor, so that the link between the management device and the second physical layer chip is in a connected state; wherein, when controlling the physical layer chip, the management device sends a third control command to the first physical layer chip through the third management bus, and sends a fourth control command to the second physical layer chip through the fourth management bus, so as to realize that the management device controls the first physical layer chip and the second physical layer chip respectively through two management buses and based on different control commands.

[0018] Optionally, the management device is connected to the first physical layer chip via a fifth management bus;

[0019] The first physical layer chip utilizes the fifth management bus and is connected to the second physical layer chip through the first connector and the second connector in sequence; wherein, when controlling the physical layer chip, the management device sends a fifth control command to the first physical layer chip through the fifth management bus, and the first physical layer chip sends the fifth control command to the second physical layer chip through the fifth management bus, so that the management device controls the first physical layer chip and the second physical layer chip based on the same control command.

[0020] Optionally, the first physical layer chip utilizes a sixth management bus and is connected to the second physical layer chip via the first connector and the second connector in sequence, and the management device is connected to the first connector via a seventh management bus; wherein, when controlling the physical layer chip, the management device sends a sixth control command to the second physical layer chip via the seventh management bus, and the second physical layer chip sends the sixth control command to the first physical layer chip via the sixth management bus, so that the management device controls the first physical layer chip and the second physical layer chip based on the same control command.

[0021] In a second aspect, the present application discloses a physical layer chip management method, which is applied to the dedicated management network port connection system as described above; wherein the method comprises:

[0022] Determine a control link between a management device on a security control module board of the dedicated management network port connection system in the server and each physical layer chip; the control link is a communication link created between the management device and each physical layer chip based on a plurality of management buses, and each physical layer chip includes a first physical layer chip on the security control module board and a second physical layer chip on an input and output board in the dedicated management network port connection system;

[0023] A control command is sent to the first physical layer chip and the second physical layer chip through the management device and by using the control link, so as to control the first physical layer chip and the second physical layer chip.

[0024] In a third aspect, the present application discloses an electronic device, comprising:

[0025] Memory for storing computer programs;

[0026] The processor is used to load and execute the computer program to implement the aforementioned physical layer chip management method.

[0027] In a fourth aspect, the present application discloses a computer program product, including a computer program / instruction, which implements the steps of the aforementioned physical layer chip management method when executed by a processor.

[0028] In a fifth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program implements the aforementioned physical layer chip management method when executed by a processor.

[0029] The present application provides a dedicated management network port connection system, including a security control module board and a main board provided with a first connector, wherein the security control module board is provided with a management device and a first physical layer chip connected to the management device; and the dedicated management network port connection system also includes: an input and output board installed on the front panel of a server chassis, wherein the input and output board is provided with a target socket of a dedicated management network port of the management device, a second physical layer chip and a second connector; wherein the first physical layer chip on the security control module board is connected in series with the second physical layer chip on the input and output board through a serial communication bus and the first connector and the second connector in sequence; the first connector and the second connector are connectors supporting preset high-density storage connections; the target socket is a socket that can generate electromagnetic interference to the security control module board; and the management device on the security control module board controls the first physical layer chip and the second physical layer chip through several management buses.

[0030] The beneficial technical effect of the present application is: by placing two physical layer chips on the safety control module board and the input and output board installed on the front panel of the server chassis, and connecting the physical layer chip far away from the main circuit position to the target socket of the dedicated management network port, since the target socket can generate electromagnetic interference to the safety control module board, it can prevent certain hardware adaptations caused by electromagnetic interference and the like from not meeting the standards after being far away from the main circuit, and solve the problem that some sockets of the dedicated management network port will cause non-compliance with the circuit design specifications. When the physical layer chip is managed by the management device located on the safety control module board in the server, the physical layer chip can be managed by using a connector that supports a preset high-density storage connection and a number of management buses, which not only solves the transmission wiring distance problem between the mainboard and the input and output board, but also ensures the data transmission capacity and transmission quality, and realizes the management of the physical layer chip by the management device.

[0031] In addition, the present application provides a physical layer chip management method, device, program product and medium, which correspond to the above-mentioned management network port connection system and have the same effect as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0033] Figure 1 A schematic diagram of an exemplary hardware design for the current BMC to manage the PHY chip;

[0034] Figure 2 A structural diagram of a dedicated management network port connection system disclosed in this application;

[0035] Figure 3 This is a system architecture diagram for managing PHY chips based on multi-function single-board multiplexed resistors disclosed in this application;

[0036] Figure 4 This is a specific system architecture diagram disclosed in this application that controls two PHY chips respectively through a management bus;

[0037] Figure 5 A simplified schematic diagram of an architecture disclosed in the present application for controlling two PHY chips respectively through a management bus;

[0038] Figure 6 This is a specific system architecture diagram disclosed in the present application that controls two PHY chips respectively through two management buses;

[0039] Figure 7 A simplified schematic diagram of an architecture disclosed in the present application for controlling two PHY chips respectively through two management buses;

[0040] Figure 8 A specific system architecture diagram disclosed in the present application for simultaneously controlling two PHY chips through a communication link of a management bus;

[0041] Fig. 9 A specific system architecture diagram disclosed in the present application for simultaneously controlling two PHY chips through a communication link of a management bus;

[0042] Fig.10 A flow chart of a physical layer chip management method disclosed in this application;

[0043] Fig.11 This is a schematic diagram of the structure of a physical layer chip management device disclosed in this application;

[0044] Fig.12 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] Currently, due to the relatively high hardware circuit requirements of some GPU manufacturers, placing the RJ45 socket of the BMC dedicated management network port on the SCM board and directly connecting it to the PHY chip will cause electromagnetic interference to the circuit and fail to meet its hardware design standards. To this end, the present application provides a dedicated management network port connection system, which can solve the problem that some sockets of the current dedicated management network port do not meet the circuit design specifications, and at the same time realize the management of the PHY chip.

[0047] The embodiment of the present invention discloses a dedicated management network port connection system, see Figure 2 As shown, the system includes a security control module board 11 and a main board 21 provided with a first connector 211, the security control module board 11 is provided with a management device 111 and a first physical layer chip 112 connected to the management device 111; and the dedicated management network port connection system also includes:

[0048] An input-output board 31 installed on the front panel of the server chassis, wherein the input-output board 31 is provided with a target socket 313 of the dedicated management network port of the management device 111, a second physical layer chip 312 and a second connector 311; wherein the first physical layer chip 112 on the security control module board 11 is connected in series with the second physical layer chip 312 on the input-output board 31 by using a serial communication bus and sequentially through the first connector 211 and the second connector 311; the first connector 211 and the second connector 311 are connectors supporting preset high-density storage connections; the target socket is a socket that can generate electromagnetic interference to the security control module board;

[0049] Furthermore, the management device 111 on the security control module board 11 controls the first physical layer chip 112 and the second physical layer chip 312 through a plurality of management buses.

[0050] In the embodiment of the present application, a dedicated management network port connection system is designed, which can be applied to a GPU server. Further, for a GPU server, in a specific implementation, the management device 111 is described by taking a BMC as an example, and the target socket 313 is described by taking an RJ45 socket as an example. It can be understood by a person skilled in the art that the specific types of the above-mentioned devices are only for illustration and do not constitute a technical limitation thereto. In the following embodiments, BMC and RJ45 sockets are used as examples for description, and no further description will be given later.

[0051] It is understandable that due to the GPU manufacturer's requirements for hardware design standards, the RJ45 socket of the BMC dedicated network port cannot be placed on the same SCM board as the BMC chip. Therefore, in the present invention, the RJ45 socket of the BMC dedicated management network port is placed on the IO (Input / output) board, and then the IO board is placed in front of the server chassis to obtain the Front IOBoard, that is, Figure 2 In this way, placing the RJ45 socket away from the main circuits of the SCM board and the motherboard can circumvent the GPU manufacturer's standards and avoid electromagnetic and light wave interference.

[0052] In general, the BMC dedicated management network port corresponds to an Ethernet PHY chip at the physical layer and a MAC controller of a BMC chip at the MAC (Media Access Control) layer. The MAC layer transmits data with the Ethernet PHY chip at the physical layer through the RGMII (Reduced Gigabit Media Independent Interface) bus. The MAC chip is responsible for processing data frames, while the PHY chip converts the data frames into electrical signals and transmits them through the network cable. The MDIO (Management Data Input / output) bus is usually used to configure and monitor the PHY chip. The BMC accesses the management registers of the PHY chip through the MDIO bus to configure the behavior of the PHY chip and monitor its status.

[0053] Therefore, in the embodiment of the present application, the management device 111 on the security control module board 11 is connected to the first physical layer chip 112 via a reduced Gigabit Media Independent Interface bus. The management device 111 on the security control module board 11 controls the physical layer chip via the management data input and output bus.

[0054] It should be pointed out that RGMII is used to connect MAC (media access control layer) and PHY chip, which reduces the number of pins and is suitable for Gigabit Ethernet. When BMC manages the PHY chip connection, a relatively simple solution is to directly connect RJ45 to the first physical layer chip PHY1 on the SCM board through a cable. However, since the wiring distance is too far and the connecting cable will cause electromagnetic interference to the circuit, the RJ45 cannot cross the IO board and the main board, and directly connect to the PHY1 on the SCM board through a very long cable. Therefore, in order to solve this problem, in the embodiment of the present application, a second physical layer chip PHY2 is placed on the IO board, and it is connected to the PHY1 on the SCM board through the SGMII (SerDes Gigabit Media Independent Interface) bus. At the same time, the BMC needs to manage the two physical layer chips through the MDIO bus.

[0055] The SGMII bus is an interface standard for high-speed data transmission between computers and peripheral devices (such as hard disk drives, tape drives, scanners, printers, etc.). Since the SGMII bus has a relatively strong transmission capacity and a relatively long wiring distance, the use of two PHY chips in series and the conversion of RGMII transmission into SGMII transmission can not only meet the design of the BMC dedicated management network port, but also overcome the problems of RGMII's wiring distance limitation, insufficient transmission capacity, and inability to achieve long-distance wiring.

[0056] Furthermore, in order to ensure data transmission capacity and transmission quality, a first connector 211 and a second connector 311 supporting preset high-density storage connections are placed on the main board 21 and the input-output board 31, respectively. In a specific embodiment, the connector can be connected using a cable such as Slim Line (SASx8) to efficiently and efficiently transmit data from the SGMII bus over long distances. The SASx8 (Serial Attached SCSI) device is a compact solution that supports high-density storage connections and is suitable for high-performance storage requirements in servers and storage systems. By providing 8 SAS ports, efficient data storage and management can be achieved in a limited space. In this way, the problem of SGMII / MDIO bus transmission and short wiring distance is further solved, while data transmission capacity and transmission quality can also be guaranteed.

[0057] That is, the first physical layer chip 112 on the security control module board 11 is connected in series with the second physical layer chip 312 on the input / output board 31 via the first connector 211 and the second connector 311 in sequence using the serial Gigabit Media Independent Interface bus.

[0058] In addition, for the SCM board, main board and IO board in the dedicated management network port connection system architecture, their positions in the server chassis can also be reasonably designed to save the main space required for the dedicated management network port connection system, and make full use of the chassis position to reserve enough space, so as to set up as many other boards as possible, so as to provide favorable conditions for function expansion and performance improvement by optimizing its space design without increasing the product size.

[0059] The present application provides a dedicated management network port connection system, including a security control module board and a main board provided with a first connector, wherein the security control module board is provided with a management device and a first physical layer chip connected to the management device; and the dedicated management network port connection system also includes: an input and output board installed on the front panel of a server chassis, wherein the input and output board is provided with a target socket of a dedicated management network port of the management device, a second physical layer chip and a second connector; wherein the first physical layer chip on the security control module board is connected in series with the second physical layer chip on the input and output board through a serial communication bus and the first connector and the second connector in sequence; the first connector and the second connector are connectors supporting preset high-density storage connections; the target socket is a socket that can generate electromagnetic interference to the security control module board; and the management device on the security control module board controls the first physical layer chip and the second physical layer chip through several management buses.

[0060] The beneficial technical effect of the present application is: by placing two physical layer chips on the safety control module board and the input and output board installed on the front panel of the server chassis, and connecting the physical layer chip far away from the main circuit position to the target socket of the dedicated management network port, since the target socket can generate electromagnetic interference to the safety control module board, it can prevent certain hardware adaptations caused by electromagnetic interference and the like from not meeting the standards after being far away from the main circuit, and solve the problem that some sockets of the dedicated management network port will cause non-compliance with the circuit design specifications. When the physical layer chip is managed by the management device located on the safety control module board in the server, the physical layer chip can be managed by using a connector that supports a preset high-density storage connection and a number of management buses, which not only solves the transmission wiring distance problem between the mainboard and the input and output board, but also ensures the data transmission capacity and transmission quality, and realizes the management of the physical layer chip by the management device.

[0061] In the present invention, the management device 111 on the security control module board 11 needs to control the first physical layer chip 112 and the second physical layer chip 312 through several management buses to achieve the management of the physical layer chip by the management device. Figure 3The figure shows a schematic diagram of a driving scheme that can realize BMC managing two PHY chips respectively through one or two MDIO buses. A multifunctional single-board multiplexing resistor 113Colay is set on the security control module.

[0062] In circuit design, Colay resistors are a technology that achieves multi-functional single-board reuse through specific routing structures and resistor layouts. Specifically, by properly placing Colay resistors on the PCB (Printed Circuit Board) and setting corresponding vias and signal lines, multiple functional application scenarios can be compatible on the same board without the need to develop new boards for each function, thereby saving costs and improving design efficiency.

[0063] Based on the above embodiment, in a feasible implementation manner, as Figure 4 The figure shows a driving scheme schematic diagram of the BMC managing two PHY chips respectively through an MDIO bus.

[0064] Specifically, the management device 111 is connected to the first physical layer chip 112 using the first management bus, and is connected to the second physical layer chip 312 using the second management bus and sequentially through the first connector 211 and the second connector 311; wherein the first management bus and the second management bus are connected based on the multi-function single board multiplexing resistor 113;

[0065] Based on the multi-functional single-board multiplexing resistor 113, the first target position R2 is reserved without resistance, so that the link between the management device 111 and the second physical layer chip 312 is in a disconnected state; wherein, when controlling the physical layer chip, the management device 111 sends a first control command to the first physical layer chip 112 through the first management bus, and sends a second control command to the second physical layer chip 312 through the first management bus, so as to realize that the management device 111 controls the first physical layer chip 112 and the second physical layer chip 312 respectively through one management bus and based on different control commands.

[0066] In the embodiment of the present application, at the hardware link level, the reserved resistor R2 position is not equipped with a resistor. In this way, the MDC2 / MDIO2 link between the BMC and the second physical layer chip 312 on the IO board is in a disconnected state. Therefore, the BMC is simultaneously connected to the first physical layer chip 112 on the SCM board and the second physical layer chip 312 on the IO board through the MDC1 / MDIO1 bus, thus forming a solution in which the BMC controls two PHYs respectively through one MDIO bus.

[0067] That is, in Figure 4The corresponding final hardware link is: (1) The BMC on the SCM board is connected to PHY1 (the first physical layer chip) through the RGMII bus, and PHY1 is connected to the Slim Line SASx8 interface on the motherboard through the SGMII bus; (2) The MDIO bus of the BMC on the SCM board is connected to PHY1 and the Slim Line SASx8 interface on the motherboard respectively; (3) PHY2 (the second physical layer chip) on the IO board is connected to its Slim Line SASx8 interface through the SGMII bus and the MDIO bus; (4) Finally, the Slim Line SASx8 interface on the motherboard and the Slim Line SASx8 interface on the IO board are connected through the Slim Line SASx8 cable. The corresponding simplified architecture diagram is shown below. Figure 5 shown.

[0068] It should be pointed out that at the driver level, the BMC kernel binds mdio1 to PHY1 and PHY2. At the same time, because PHY2 is connected to the RJ45 socket, the outside world accesses the BMC's dedicated management network through PHY2, so mac2 is bound to PHY2. Since PHY1 is a transit chip, there is no need to bind mac. When the BMC kernel starts, the configuration of the PHY1 and PHY2 chips (such as data transmission rate, duplex mode, media type, etc.) is initialized through mdio1. When sending control commands to PHY1 and PHY2 chips, BMC communicates with PHY1 and PHY2 through mdio1, so BMC needs to carry the address of the PHY chip when sending commands, for example, the address of PHY1 is 0x0 and the address of PHY2 is 0x1. Further, according to the control command, the BMC implements the driver scheme of managing two PHY chips separately through an MDIO bus.

[0069] In addition, in an embodiment of the present application, in order to prevent the transmission speed from being reduced due to inconsistent transmission rates between PHY1 and PHY2, the transmission rates of the first physical layer chip and the second physical layer chip are controlled by the management device so that PHY1 follows PHY2 to maintain a consistent transmission rate.

[0070] In a first specific implementation, the management device uses the management bus to set the first physical layer chip and the second physical layer chip to the rate self-matching mode to achieve transmission rate control. That is, the BMC sets PHY1 / PHY2 to the rate self-matching mode through mdio1, so that it can automatically negotiate the best transmission rate and mode with the connected device, ensuring compatibility and optimal performance between the two. And it automatically adjusts the data transmission rate under different network conditions, improving communication efficiency and stability.

[0071] In a second specific implementation, the management device obtains the transmission rate setting parameters of the second physical layer chip, and uses the management bus to set the transmission rate setting parameters to the transmission rate of the first physical layer chip to achieve transmission rate control. That is, after the BMC obtains the setting parameters of PHY2, it sets them to PHY1 through mdio1.

[0072] Based on the above embodiment, in a feasible implementation manner, as Figure 6 The figure shows a driving scheme schematic diagram of the BMC managing two PHY chips respectively through two MDIO buses.

[0073] Specifically, the management device 111 is connected to the first physical layer chip 112 using the third management bus, and is connected to the second physical layer chip 312 using the fourth management bus and sequentially through the first connector 211 and the second connector 311; wherein the third management bus and the fourth management bus are connected based on the multi-function single board multiplexing resistor 113;

[0074] Based on the multi-functional single-board multiplexing resistor 113, the second target position R1 is reserved without resistance, so that the link between the management device 111 and the second physical layer chip 312 is in a connected state; wherein, when controlling the physical layer chip, the management device 111 sends a third control command to the first physical layer chip 112 through the third management bus, and sends a fourth control command to the second physical layer chip 312 through the fourth management bus, so as to realize that the management device 111 controls the first physical layer chip 112 and the second physical layer chip 312 respectively through two management buses and based on different control commands.

[0075] In the embodiment of the present application, at the hardware link level, the reserved resistor R1 position is not equipped with a resistor. In this way, the MDC2 / MDIO2 link between the BMC and the second physical layer chip 312 on the IO board is in a connected state. Therefore, the BMC is connected to the first physical layer chip 112 on the SCM board through the MDC1 / MDIO1 bus, and is connected to the second physical layer chip 312 on the IO board through the MDC2 / MDIO2 bus, thus forming a solution in which the BMC controls two PHYs respectively through two MDIO buses.

[0076] That is, in Figure 6The corresponding final hardware link is: (1) The BMC on the SCM board is connected to PHY1 (the first physical layer chip) through the RGMII bus, and PHY1 is connected to the Slim Line SASx8 interface on the motherboard through the SGMII bus; (2) The MDIO bus of the BMC on the SCM board is connected to PHY1 and the Slim Line SASx8 interface on the motherboard respectively; (3) PHY2 (the second physical layer chip) on the IO board is connected to its Slim Line SASx8 interface through the SGMII bus and the MDIO bus; (4) Finally, the Slim Line SASx8 interface on the motherboard and the Slim Line SASx8 interface on the IO board are connected through the Slim Line SASx8 cable. The corresponding simplified architecture diagram is shown below. Figure 7 shown.

[0077] It should be pointed out that at the driver level, the BMC kernel binds mdio1 to PHY1 and mdio2 to PHY2. At the same time, because PHY2 is connected to the RJ45 socket, the outside world accesses the BMC's dedicated management network through PHY2, so mac2 is bound to PHY2. Since PHY1 is a transit chip, it does not need to be bound to mac. When the BMC kernel starts, the configuration of the PHY1 and PHY2 chips (such as data transmission rate, duplex mode, media type, etc.) is initialized through mdio1 and mdio2 respectively.

[0078] Similarly, in the embodiment of the present application, in order to prevent the transmission speed from being reduced due to the inconsistent transmission rates of PHY1 and PHY2, PHY1 must be required to maintain a consistent transmission rate with PHY2. Therefore, the BMC sets PHY1 / PHY2 to the rate self-matching mode through mdio1, or the BMC obtains the setting parameters of PHY2 and then sets them to PHY1 through mdio1.

[0079] Further, such as Figure 8 , Fig. 9 The figure shows a schematic diagram of an exemplary driving solution that enables the BMC to control two PHY chips simultaneously through only one MDIO bus communication link.

[0080] In a specific embodiment, Figure 8 As shown, specifically, the management device 111 is connected to the first physical layer chip 112 via a fifth management bus;

[0081] The first physical layer chip 112 utilizes the fifth management bus and is connected to the second physical layer chip 312 through the first connector 211 and the second connector 311 in sequence; wherein, when controlling the physical layer chip, the management device 111 sends a fifth control command to the first physical layer chip 112 through the fifth management bus, and the first physical layer chip 112 sends the fifth control command to the second physical layer chip 312 through the fifth management bus, so that the management device controls the first physical layer chip 112 and the second physical layer chip 312 based on the same control command.

[0082] The corresponding hardware links in the embodiment of the present application are: (1) the BMC on the SCM board is connected to PHY1 (the first physical layer chip) through the RGMII bus, and PHY1 is connected to the Slim Line SASx8 interface on the mainboard through the SGMII bus; (2) the MDIO bus of the BMC on the SCM board is connected to PHY1; (3) the PHY1 on the SCM board is connected to the Slim Line SASx8 interface on the mainboard through the MDIO bus; (4) the PHY2 (the second physical layer chip) on the IO board is connected to its Slim Line SASx8 interface through the SGMII bus and the MDIO bus; (5) finally, the Slim Line SASx8 interface on the mainboard and the Slim Line SASx8 interface on the IO board are connected through a Slim Line SASx8 cable.

[0083] It should be pointed out that at the driver level, the BMC kernel binds mdio1 to PHY1. At the same time, because PHY2 is connected to the RJ45 socket, the outside world accesses the BMC's dedicated management network through PHY2, so mac2 is bound to PHY2. Since PHY1 is a transit chip, it does not need to be bound to mac. When the BMC kernel starts, it initializes PHY1 through mdio1, sends control commands to PHY1 through the mdio1 bus, and then PHY1 sends the same control command just sent by BMC to PHY2 through the MDIO bus, completing the BMC's control and management of PHY1 and PHY2 at the same time.

[0084] In another specific embodiment, Fig. 9As shown, specifically, the first physical layer chip 112 utilizes the sixth management bus and is connected to the second physical layer chip 312 through the first connector 211 and the second connector 311 in sequence, and the management device 111 is connected to the first connector 211 through the seventh management bus; wherein, when controlling the physical layer chip, the management device 111 sends a sixth control command to the second physical layer chip 312 through the seventh management bus, and the second physical layer chip 312 sends the sixth control command to the first physical layer chip 112 through the sixth management bus, so as to enable the management device 111 to control the first physical layer chip 112 and the second physical layer chip 312 based on the same control command.

[0085] The corresponding hardware links in the embodiment of the present application are: (1) the BMC on the SCM board is connected to PHY1 (the first physical layer chip) through the RGMII bus, and PHY1 is connected to the Slim Line SASx8 interface on the mainboard through the SGMII bus; (2) the MDIO bus of the BMC on the SCM board is connected to the Slim Line SASx8 interface on the mainboard; (3) the PHY1 on the SCM board is connected to the Slim Line SASx8 interface on the mainboard through the MDIO bus; (4) the PHY2 (the second physical layer chip) on the IO board is connected to its Slim Line SASx8 interface through the SGMII bus and the MDIO bus; (5) finally, the Slim Line SASx8 interface on the mainboard and the Slim Line SASx8 interface on the IO board are connected through a Slim Line SASx8 cable.

[0086] It should be pointed out that at the driver level, the BMC kernel binds mdio2 to PHY2. At the same time, because PHY2 is connected to the RJ45 socket, the outside world accesses the BMC's dedicated management network through PHY2, so mac2 is bound to PHY2. Since PHY1 is a transit chip, it does not need to be bound to mac. When the BMC kernel starts, it initializes PHY2 through mdio2, sends control commands to PHY2 through the mdio2 bus, and then PHY2 sends the same control command just sent by BMC to PHY1 through MDIO, completing the BMC's control and management of PHY1 and PHY2 at the same time.

[0087] The present application embodiment discloses a physical layer chip management method, which is applied to the dedicated management network port connection system disclosed in the above embodiment; see Fig.10 As shown, the method includes:

[0088] Step S11: Determine the control link between the management device on the security control module board of the dedicated management network port connection system in the server and each physical layer chip; the control link is a communication link created between the management device and each physical layer chip based on several management buses, and each physical layer chip includes a first physical layer chip located on the security control module board and a second physical layer chip on the input and output board in the dedicated management network port connection system.

[0089] Step S12: Sending a control command to the first physical layer chip and the second physical layer chip through the management device and using the control link to control the first physical layer chip and the second physical layer chip.

[0090] In the embodiment of the present application, two physical layer chips are placed to solve the problem that some sockets of the dedicated management network port of the management device will not meet the circuit design specifications. Therefore, when applied to the dedicated management network port connection system designed by the present invention, by determining the control link between the management device on the security control module board of the dedicated management network port connection system in the server and each physical layer chip, data transmission is further realized according to the control link, and the management of the physical layer chip by the management device is realized through control commands. Among them, the more specific processing process of the above steps can refer to the corresponding content disclosed in the aforementioned embodiment, and will not be repeated here.

[0091] In this embodiment, a physical layer chip management method is provided, which is applied to a dedicated management network port connection system, including: determining a control link between a management device on a security control module board in the server and each physical layer chip; the control link is a communication link created between the management device and each physical layer chip based on a number of management buses, and each physical layer chip includes a first physical layer chip on the security control module board and a second physical layer chip on an input and output board in the dedicated management network port connection system; and sending a control command to the first physical layer chip and the second physical layer chip through the management device and using the control link to achieve control of the first physical layer chip and the second physical layer chip.

[0092] The beneficial technical effect of the present application is: by placing two physical layer chips on the safety control module board and the input and output board installed on the front panel of the server chassis, and connecting the physical layer chip far away from the main circuit position to the target socket of the dedicated management network port, since the target socket can generate electromagnetic interference to the safety control module board, it can prevent certain hardware adaptations caused by electromagnetic interference and the like from not meeting the standards after being far away from the main circuit, and solve the problem that some sockets of the dedicated management network port will cause non-compliance with the circuit design specifications. When the physical layer chip is managed by the management device located on the safety control module board in the server, the physical layer chip can be managed by using a connector that supports a preset high-density storage connection and a number of management buses, which not only solves the transmission wiring distance problem between the mainboard and the input and output board, but also ensures the data transmission capacity and transmission quality, and realizes the management of the physical layer chip by the management device.

[0093] Correspondingly, the embodiment of the present application also discloses a physical layer chip management device, see Fig.11 As shown, the device comprises:

[0094] The link determination module 51 is used to determine the control link between the management device on the security control module board of the dedicated management network port connection system in the server and each physical layer chip; the control link is a communication link established between the management device and each physical layer chip based on a plurality of management buses, and each physical layer chip includes a first physical layer chip on the security control module board and a second physical layer chip on the input and output board of the dedicated management network port connection system;

[0095] The chip control module 52 is used to send control commands to the first physical layer chip and the second physical layer chip through the management device and using the control link to achieve control of the first physical layer chip and the second physical layer chip.

[0096] Among them, for more specific working processes of the above-mentioned modules, please refer to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0097] It can be seen that the above-mentioned scheme of this embodiment is applied to the dedicated management network port connection system, including: determining the control link between the management device on the security control module board of the dedicated management network port connection system in the server and each physical layer chip; the control link is a communication link created between the management device and each physical layer chip based on several management buses, and each physical layer chip includes a first physical layer chip located on the security control module board and a second physical layer chip on the input and output board in the dedicated management network port connection system; sending control commands to the first physical layer chip and the second physical layer chip through the management device and using the control link to achieve control of the first physical layer chip and the second physical layer chip.

[0098] The beneficial technical effect of the present application is: by placing two physical layer chips on the safety control module board and the input and output board installed on the front panel of the server chassis, and connecting the physical layer chip far away from the main circuit position to the target socket of the dedicated management network port, since the target socket can generate electromagnetic interference to the safety control module board, it can prevent certain hardware adaptations caused by electromagnetic interference and the like from not meeting the standards after being far away from the main circuit, and solve the problem that some sockets of the dedicated management network port will cause non-compliance with the circuit design specifications. When the physical layer chip is managed by the management device located on the safety control module board in the server, the physical layer chip can be managed by using a connector that supports a preset high-density storage connection and a number of management buses, which not only solves the transmission wiring distance problem between the mainboard and the input and output board, but also ensures the data transmission capacity and transmission quality, and realizes the management of the physical layer chip by the management device.

[0099] Furthermore, the present application also discloses an electronic device. Fig.12 This is a structural diagram of an electronic device 60 according to an exemplary embodiment, and the content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0100] Fig.12 A schematic diagram of the structure of an electronic device 60 provided in an embodiment of the present application. The electronic device 60 may specifically include: at least one processor 61, at least one memory 62, a power supply 63, a communication interface 64, an input / output interface 65, and a communication bus 66. The memory 62 is used to store a computer program, which is loaded and executed by the processor 61 to implement the relevant steps in the physical layer chip management method disclosed in any of the aforementioned embodiments. In addition, the electronic device 60 in this embodiment may specifically be a server.

[0101] In this embodiment, the power supply 63 is used to provide working voltage for each hardware device on the electronic device 60; the communication interface 64 can create a data transmission channel between the electronic device 60 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 65 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0102] In addition, the memory 62 as a carrier for resource storage may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon may include an operating system 621, a computer program 622 and data 623, etc. The data 623 may include various data. The storage method may be temporary storage or permanent storage.

[0103] The operating system 621 is used to manage and control the hardware devices on the electronic device 60 and the computer program 622, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the physical layer chip management method performed by the electronic device 60 disclosed in any of the aforementioned embodiments, the computer program 622 can further include a computer program that can be used to complete other specific tasks.

[0104] Furthermore, the embodiment of the present application also discloses a computer-readable storage medium, wherein the computer-readable storage medium mentioned here includes a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a magnetic disk or an optical disk, or any other form of storage medium known in the technical field. Wherein, when the computer program is executed by the processor, the aforementioned physical layer chip management method is implemented. For the specific steps of the method, reference can be made to the corresponding contents disclosed in the aforementioned embodiment, and no further description will be given here.

[0105] Furthermore, an embodiment of the present application also provides a computer program product, including a computer program / instruction, which implements any one of the above-mentioned physical layer chip management methods when executed by a processor.

[0106] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0107] The steps of the physical layer chip management method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the technical field.

[0108] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0109] The above is a detailed introduction to a dedicated management network port connection system, physical layer chip management method, equipment, product and medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A dedicated management network port connection system, characterized in that: It includes a safety control module board and a main board provided with a first connector, wherein the safety control module board is provided with a management device and a first physical layer chip connected to the management device; and the dedicated management network port connection system also includes: An input-output board installed on the front panel of the server chassis, wherein the input-output board is provided with a target socket of the dedicated management network port of the management device, a second physical layer chip and a second connector; wherein the first physical layer chip on the security control module board is connected in series with the second physical layer chip on the input-output board through the first connector and the second connector in sequence using a serial communication bus; the first connector and the second connector are connectors supporting preset high-density storage connections; the target socket is a socket capable of generating electromagnetic interference to the security control module board; Furthermore, the management device on the security control module board controls the first physical layer chip and the second physical layer chip through a plurality of management buses.

2. The dedicated management network port connection system according to claim 1, characterized in that: The management device on the security control module board is connected to the first physical layer chip via a reduced Gigabit Media Independent Interface bus.

3. The dedicated management network port connection system according to claim 1, characterized in that: The first physical layer chip on the security control module board is connected in series with the second physical layer chip on the input-output board via the first connector and the second connector in sequence using a serial Gigabit Media Independent Interface bus.

4. The dedicated management network port connection system according to claim 1, characterized in that: The management device on the safety control module board controls the first physical layer chip and the second physical layer chip through a plurality of management data input and output buses.

5. The dedicated management network port connection system according to claim 1, characterized in that: The management device is used to control the transmission rates of the first physical layer chip and the second physical layer chip.

6. The dedicated management network port connection system according to claim 5, characterized in that: The management device is used to set the first physical layer chip and the second physical layer chip to a rate self-matching mode by using the management bus to achieve transmission rate control.

7. The dedicated management network port connection system according to claim 5, characterized in that: The management device is used to obtain the transmission rate setting parameter of the second physical layer chip, and use the management bus to set the transmission rate setting parameter to the transmission rate of the first physical layer chip to achieve transmission rate control.

8. The dedicated management network port connection system according to any one of claims 1 to 7, characterized in that: The management device is connected to the first physical layer chip by using a first management bus, and is connected to the second physical layer chip by using a second management bus and sequentially through the first connector and the second connector; wherein the first management bus and the second management bus are connected based on a multi-function single board multiplexing resistor; Based on the multi-functional single board multiplexing resistor, the first target position is reserved without resistor, so that the link between the management device and the second physical layer chip is in a disconnected state; wherein, when controlling the physical layer chip, the management device sends a first control command to the first physical layer chip through the first management bus, and sends a second control command to the second physical layer chip through the first management bus, so that the management device controls the first physical layer chip and the second physical layer chip respectively through one management bus and based on different control commands.

9. The dedicated management network port connection system according to any one of claims 1 to 7, characterized in that: The management device is connected to the first physical layer chip by using the third management bus, and is connected to the second physical layer chip by using the fourth management bus and sequentially through the first connector and the second connector; wherein the third management bus and the fourth management bus are connected based on a multi-function single board multiplexing resistor; Based on the multi-functional single board multiplexing resistor, the second target position is reserved without resistor, so that the link between the management device and the second physical layer chip is in a connected state; wherein, when controlling the physical layer chip, the management device sends a third control command to the first physical layer chip through the third management bus, and sends a fourth control command to the second physical layer chip through the fourth management bus, so as to realize that the management device controls the first physical layer chip and the second physical layer chip respectively through two management buses and based on different control commands.

10. The dedicated management network port connection system according to any one of claims 1 to 7, characterized in that: The management device is connected to the first physical layer chip via a fifth management bus; The first physical layer chip utilizes the fifth management bus and is connected to the second physical layer chip through the first connector and the second connector in sequence; wherein, when controlling the physical layer chip, the management device sends a fifth control command to the first physical layer chip through the fifth management bus, and the first physical layer chip sends the fifth control command to the second physical layer chip through the fifth management bus, so that the management device controls the first physical layer chip and the second physical layer chip based on the same control command.

11. The dedicated management network port connection system according to any one of claims 1 to 7, characterized in that: The first physical layer chip utilizes a sixth management bus and is connected to the second physical layer chip through the first connector and the second connector in sequence, and the management device is connected to the first connector through a seventh management bus; wherein, when controlling the physical layer chip, the management device sends a sixth control command to the second physical layer chip through the seventh management bus, and the second physical layer chip sends the sixth control command to the first physical layer chip through the sixth management bus, so that the management device controls the first physical layer chip and the second physical layer chip based on the same control command.

12. A physical layer chip management method, characterized in that: Applicable to the dedicated management network port connection system according to any one of claims 1 to 11; wherein the method comprises: Determine a control link between a management device on a security control module board of the dedicated management network port connection system in the server and each physical layer chip; the control link is a communication link created between the management device and each physical layer chip based on a plurality of management buses, and each physical layer chip includes a first physical layer chip on the security control module board and a second physical layer chip on an input and output board in the dedicated management network port connection system; A control command is sent to the first physical layer chip and the second physical layer chip through the management device and by using the control link, so as to control the first physical layer chip and the second physical layer chip.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, used to load and execute the computer program to implement the physical layer chip management method according to claim 12.

14. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the physical layer chip management method according to claim 12 are implemented.

15. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein the computer program, when executed by the processor, implements the physical layer chip management method described in claim 12.

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