NPU, instruction set, control method based on instruction set, device and storage medium

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By storing the same information using the same bits in the instruction set of the NPU, the resolution difficulty problem caused by the complex instruction set format is solved, and the effect of simplifying instruction analysis logic and improving hardware efficiency is achieved.

CN118939321BActive Publication Date: 2025-02-28AXERA SEMICON (SHANGHAI) CO LTD

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Patent Information

Application Number: CN202411418565.1
Authority / Receiving Office: CN · China
Patent Type: Patents(China)
Current Assignee / Owner
Filing Date: 2024-10-12
Publication Date: 2025-02-28
Estimated Expiration: 2044-10-12

AI Technical Summary

Technical Problem

The instruction set format of existing NPUs is complex and difficult to parse, which leads to increased design difficulty and area of hardware analysis modules.

Method used

In each instruction in the instruction set, the same information is stored in part of the same bits, and the control module can use the same read logic and parsing logic to simplify the read and parsing logic of the instructions.

Benefits of technology

Reduces the number of registers used to store read logic and parsing logic, reduces the hardware area, and improves the parsing efficiency of instructions, so that each instruction can be parsed within one clock cycle.

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Abstract

The present application relates to the field of chip technology, and provides an NPU, an instruction set, a control method based on an instruction set, a device and a storage medium, wherein the NPU comprises: a control module; a control module for acquiring and parsing an instruction set or an instruction, wherein the instruction set comprises a plurality of instructions, each instruction has the same number of bits, and the first position is the same as the second position; the control module is also used to determine the running moment and running time of the tth task being executed by the NPU based on the first type of indication information; t is an integer greater than or equal to 1; each task corresponds to at least one instruction; the control module is also used to determine the operation type corresponding to the instruction based on the second type of indication information, and control the NPU to perform the operation corresponding to the operation type; the operation type includes at least a configuration operation and a processing operation. The technical solution of the present application can reduce the design difficulty of the hardware parsing module.

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Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an NPU, an instruction set, a control method based on the instruction set, a device and a storage medium. Background Art

[0002] NPU (Neural Processing Unit) is mainly composed of a computing module and a control module. The computing module is responsible for data computing and processing, and the control module is responsible for configuring relevant information for the computing module and controlling the startup and scheduling of the computing module.

[0003] In the related art, the control module performs related operations by parsing and executing the instruction set. The instruction set is a collection of instructions that the NPU can recognize and execute. These instructions define the basic operations that the NPU can perform, including logical operations and data transmission.

[0004] However, the instruction set currently used in NPU has a complex format and is difficult to parse. Summary of the invention

[0005] The embodiment of the present application provides an NPU, an instruction set, a control method based on the instruction set, a device and a storage medium. In each instruction in the instruction set, the same information is stored in some of the same bits. Therefore, the control module can use the same reading logic to read and the same parsing logic to parse the same position, thereby reducing the design difficulty and area of the hardware parsing module. The technical solution is as follows:

[0006] According to a first aspect of an embodiment of the present application, there is provided an NPU, including:

[0007] Control module;

[0008] The control module is used to obtain and parse an instruction set or an instruction, the instruction set includes a plurality of the instructions, each of the instructions has the same number of bits, and the first position is the same as the second position; the first position is the position of the first type of indication information included in the instruction in the instruction, and the second position is the position of the second type of indication information included in the instruction in the instruction;

[0009] The control module is further used to determine the running time and running time of the tth task being executed by the NPU based on the first type of indication information; t is an integer greater than or equal to 1; each of the tasks corresponds to at least one of the instructions;

[0010] The control module is also used to determine the operation type corresponding to the instruction based on the second type of indication information, and control the NPU to perform the operation corresponding to the operation type; the operation type at least includes a configuration operation and a processing operation.

[0011] In a possible implementation, the first type of indication information includes dot information and task update information;

[0012] The control module is further used to control the NPU not to print the running time based on the dot information; the running time is the start time or end time of the task; the running time is obtained based on the start time and end time of the task;

[0013] Or the control module is further used to control the NPU to print the start time or the end time based on the dot information;

[0014] The control module is also used to determine that the NPU is executing the t+1th task based on the task update information; control the NPU to print the start time or the end time of the t+1th task based on the dot information; or determine that the NPU is executing the tth task based on the task update information; and control the NPU to print the start time or the end time of the tth task based on the dot information.

[0015] In a possible implementation, the first type of indication information further includes verification information; the verification information includes an initial verification code;

[0016] The control module is further used to determine whether an exception occurs in the corresponding instruction based on the verification information; the exception indicates that the NPU times out and generates an interrupt or an error occurs in the operation of the NPU;

[0017] Wherein, when the initial verification code is consistent with the actual verification code, the control module determines that the corresponding instruction is normal; the actual verification code is generated when the NPU parses the corresponding instruction;

[0018] Or when the initial verification code is inconsistent with the actual verification code, the control module determines that an exception occurs in the corresponding instruction.

[0019] In a possible implementation, the instruction set includes a configuration instruction; the configuration instruction also includes first address information and first data information;

[0020] The control module is further used to determine the address of the first function register based on the first address information;

[0021] The control module is also used to configure the first data information to the first function register based on the second type of indication information of the configuration instruction; the first function register is set in the NPU.

[0022] In a possible implementation, the instruction set further includes a load instruction; the load instruction further includes second address information, quantity information, and second data information;

[0023] The control module is further used to determine the address of the first general register to be rewritten in the control module based on the second address information;

[0024] The control module is further used to determine the quantity of the first general register to be rewritten based on the quantity information;

[0025] The control module is further used to determine the address of the loaded data in the memory based on the second data information;

[0026] The control module is further used to load the load data into the first general register based on the second type of indication information of the load instruction; the address of the load data includes an initial address and an offset address.

[0027] In a possible implementation, the instruction set further includes a move instruction; the move instruction further includes third address information and fourth address information;

[0028] The control module is further used to determine the address of a second general register in the control module based on the third address information;

[0029] The control module is further used to determine the address of the second function register in the NPU based on the fourth address information;

[0030] The control module is also used to control the NPU to move the data in the second general register to the second function register based on the second type of indication information of the move instruction.

[0031] In a possible implementation, the NPU further includes a scheduling module; the scheduling module is electrically connected to the control module; the instruction set further includes an interrupt instruction; the interrupt instruction further includes a third type of indication information; the third type of indication information is used to indicate the operation type;

[0032] The control module is further used to control the scheduling module to generate an interrupt based on the second type of indication information and the third type of indication information of the interrupt instruction.

[0033] In a possible implementation, the NPU further includes a data processing module and a data transmission module; the control module is electrically connected to the data processing module and the data transmission module respectively; the scheduling module is electrically connected to the data processing module and the data transmission module respectively;

[0034] The instruction set also includes an update instruction and a wait instruction; the update instruction and the wait instruction also include the third type of indication information;

[0035] The control module is further used to control the data processing module or the data transmission module to wait for the third function register to be updated based on the second type of indication information and the third type of indication information of the waiting instruction;

[0036] The control module is further used to control the data processing module or the data transmission module to update the third function register based on the second type of indication information and the third type of indication information of the update instruction;

[0037] The scheduling module is used to notify the waiting data processing module or data transmission module to end the waiting operation after detecting that the third function register is updated to a corresponding value;

[0038] The control module is also used to control the data transmission module or the data processing module to update the third function register; the third function register is set in the scheduling module.

[0039] In a possible implementation, the update instruction further includes first determination information, first absolute address information, first relative address information, and an initial update value;

[0040] The control module is further used to determine that first initial data needs to be acquired based on the first determination information; the first initial data is part of the data of the third general register; the third general register is set in the control module;

[0041] The control module is further used to determine the address of the third general register based on the first absolute address information;

[0042] The control module is further used to determine the address of the third function register based on the first relative address information;

[0043] The control module is also used to control the data processing module or the data transmission module to write the initial update value and the first initial data into the third function register based on the second type of indication information and the third type of indication information of the update instruction.

[0044] In a possible implementation manner, the control module is further configured to determine, based on the first determination information, that it is not necessary to obtain the first initial data;

[0045] The control module is further used to determine the address of the third function register based on the first relative address information;

[0046] The control module is also used to control the data processing module or the data transmission module to write the initial update value into the third function register based on the second type of indication information and the third type of indication information of the update instruction.

[0047] In a possible implementation, the waiting instruction further includes second determination information, second absolute address information, second relative address information, and an initial waiting value;

[0048] The control module is further used to determine that second initial data needs to be acquired based on the second determination information; the second initial data is a portion of data of a fourth general register; the fourth general register is set in the control module;

[0049] The control module is further used to determine the address of the fourth general register based on the second absolute address information;

[0050] The control module is further used to determine the address of the fourth function register based on the second relative address information;

[0051] The control module is also used to control the data processing module or the data transmission module to write the initial waiting value and the second initial data into the fourth function register; the fourth function register is set in the scheduling module.

[0052] In a possible implementation manner, the control module is further configured to determine, based on the second determination information, that it is not necessary to obtain the second initial data;

[0053] The control module is further used to determine the address of the fourth function register based on the second relative address information;

[0054] The control module is also used to control the data processing module or the data transmission module to write the initial waiting value into the fourth function register.

[0055] In a possible implementation, the first address position and the second address position are the same; the first address position is the position of the first absolute address information in the update instruction; the second address position is the position of the second absolute address information in the wait instruction;

[0056] The first indication position, the second indication position and the third indication position are the same; the first indication position is the position of the third type of indication information in the interrupt instruction; the second indication position is the position of the third type of indication information in the update instruction; the third indication position is the position of the third type of indication information in the wait instruction.

[0057] In a possible implementation, the instruction set further includes a waiting task completion instruction; the waiting task completion instruction further includes waiting indication information;

[0058] The control module is further used to control the NPU to perform a waiting operation based on the second type of indication information of the waiting task completion instruction;

[0059] The control module is further used to control the NPU to wait for the data transmission task to be completed based on the waiting indication information;

[0060] or the control module is further used to control the NPU to wait for the data processing task to be completed based on the waiting indication information;

[0061] Or the control module is further used to control the NPU to wait for the data transmission task and the data processing task to be completed based on the waiting indication information.

[0062] In a possible implementation, the instruction set further includes a no-operation instruction; the no-operation instruction further includes number information; the number information indicates a target number of no-operations;

[0063] The control module is also used to control the NPU to execute a target number of no-operations based on the second type of indication information of the no-operation instruction.

[0064] In a possible implementation, the instruction set further includes a jump instruction; the jump instruction further includes jump address information;

[0065] The control module is further used to interrupt the acquisition of all unacquired instructions in the initial instruction queue based on the second type of indication information of the jump instruction; acquire each preset instruction in the preset instruction sequence; the initial instruction queue is part of the instruction set; the preset instruction sequence is part of the instruction set;

[0066] The control module is also used to determine the address of the fifth general register based on the jump address information; the fifth general register is used to store the base address; the base address is used to store the preset instruction sequence; the fifth general register is set in the control module.

[0067] In a possible implementation, the instruction set further includes a skip instruction; the skip instruction further includes validity information and skip quantity information;

[0068] The control module is further used to determine that a skip operation needs to be performed based on the validation information;

[0069] The control module is further used to control the NPU to skip the skipped number of unparsed instructions based on the second type of indication information of the skipped instruction; parse the target instruction in the initial instruction queue; the target instruction is the next unparsed instruction of the skipped number of unparsed instructions; or

[0070] The control module is further used to determine that the NPU does not need to perform a skip operation based on the validation information;

[0071] The control module is also used to directly parse the next unparsed instruction in the initial instruction queue.

[0072] In a possible implementation, the instruction set further includes a reset instruction;

[0073] The control module is also used to control the NPU to perform a reset operation based on the second type of indication information in the reset instruction.

[0074] In a possible implementation, the instruction set further includes an addition instruction; the addition instruction further includes operation information, an immediate value, a first initial value, write address information, a second initial value, and read address information;

[0075] The control module is further used to determine the addition type based on the operation information;

[0076] The control module is further used to determine an initial value of a sixth general register based on the first initial value; the sixth general register is set in the control module;

[0077] The control module is further used to determine the address of the sixth general register based on the write address information;

[0078] The control module is further used to determine an initial value of a seventh general register based on the second initial value; the seventh general register is set in the control module;

[0079] The control module is further used to determine the address of the seventh general register based on the read address information;

[0080] The control module is also used to control the NPU to perform an addition operation based on the second type of indication information of the addition instruction.

[0081] In a possible implementation, the control module is further configured to control the NPU to write the immediate value into the sixth general register based on the second type of indication information of the addition instruction and the operation information when the operation information indicates the first addition type;

[0082] or the control module is further used to control the NPU to write the immediate value and the first initial value into the sixth general register based on the second type indication information of the addition instruction and the operation information when the operation information indicates a second addition type;

[0083] or the control module is further configured to, when the operation information indicates a third addition type, control the NPU to write the immediate value and the second initial value into the sixth general register based on the second type indication information of the addition instruction and the operation information;

[0084] Or the control module is also used to control the NPU to write the first initial value and the second initial value into the sixth general register based on the second type of indication information of the addition instruction and the operation information when the operation information indicates a fourth addition type.

[0085] In a possible implementation, each of the instructions further includes a free position.

[0086] According to a second aspect of an embodiment of the present application, an instruction set is provided, the instruction set comprising:

[0087] A plurality of instructions; each of the instructions has the same number of bits; each of the instructions includes first-type indication information and second-type indication information; the first position is the same as the second position; the first position is the position of the first-type indication information in the corresponding instruction, and the second position is the position of the second-type indication information in the corresponding instruction;

[0088] The first type of indication information is used to determine the running time and running time of the tth task being executed by the NPU; t is an integer greater than or equal to 1; each of the tasks corresponds to at least one of the instructions;

[0089] The second type of indication information is used to determine the operation type corresponding to the instruction; the operation type at least includes a configuration operation and a processing operation.

[0090] According to a third aspect of an embodiment of the present application, a control method based on an instruction set is provided, the method comprising:

[0091] Obtain and parse an instruction set or an instruction, the instruction set including a plurality of the instructions, each of the instructions having the same number of bits, and the first position being the same as the second position; the first position being the position of the first type of indication information included in the instruction in the instruction, and the second position being the position of the second type of indication information included in the instruction in the instruction;

[0092] Determine the running time and running time of the tth task being executed by the NPU based on the first type of indication information; t is an integer greater than or equal to 1; each of the tasks corresponds to at least one of the instructions;

[0093] Based on the second type of indication information, the operation type corresponding to the instruction is determined, and the NPU is controlled to perform the operation corresponding to the operation type; the operation type at least includes a configuration operation and a processing operation.

[0094] According to a fourth aspect of an embodiment of the present application, a computer device is provided, which includes a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the above-mentioned instruction set-based control method.

[0095] According to a fifth aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which at least one program is stored. The at least one program is loaded and executed by a processor to implement the above-mentioned instruction set-based control method.

[0096] In an embodiment of the present application, an NPU is provided, in which the same information is stored in some of the same bits of each instruction in the instruction set, so that the control module can use the same read logic to read and the same parsing logic to parse the same position, thereby simplifying the reading logic and parsing logic of the instruction, thereby reducing the number of registers used to store the reading logic and the parsing logic, and reducing the hardware area. In addition, the same position can be read using the same read logic and the same parsing logic, which also improves the parsing efficiency of the instruction, so that each instruction can be parsed within one clock cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0097] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0098] Figure 1 is a schematic diagram of an implementation environment provided according to an embodiment of the present application;

[0099] Figure 2 is a schematic diagram of the structure of an NPU provided according to an embodiment of the present application;

[0100] Figure 3 is a schematic diagram of the structure of a configuration instruction provided according to an embodiment of the present application;

[0101] Figure 4 is a structural diagram of a load instruction provided according to an embodiment of the present application;

[0102] Figure 5 is a structural diagram of a move instruction provided according to an embodiment of the present application;

[0103] Figure 6 is a schematic diagram of the structure of an interrupt instruction provided according to an embodiment of the present application;

[0104] Figure 7 is a schematic diagram of the structure of an update instruction provided according to an embodiment of the present application;

[0105] Figure 8 is a structural diagram of a wait instruction provided according to an embodiment of the present application;

[0106] Fig. 9 It is a structural diagram of a waiting task completion instruction provided according to an embodiment of the present application;

[0107] Fig.10 is a schematic diagram of the structure of a no-operation instruction provided according to an embodiment of the present application;

[0108] Fig.11 is a schematic diagram of the structure of a jump instruction provided according to an embodiment of the present application;

[0109] Fig.12 is a schematic diagram of a structure of a skip instruction provided according to an embodiment of the present application;

[0110] Fig.13 is a structural diagram of a reset instruction provided according to an embodiment of the present application;

[0111] Fig.14 is a structural diagram of an addition instruction provided according to an embodiment of the present application;

[0112] Fig.15 It is a flowchart of a control method based on an instruction set provided according to an embodiment of the present application;

[0113] Fig.16 is a schematic diagram of the structure of a terminal provided according to an embodiment of the present application;

[0114] Fig.17 It is a structural diagram of a server provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0115] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0116] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0117] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on the quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms.

[0118] These terms are only used to distinguish one element from another element. For example, without departing from the scope of various examples, a first action can be referred to as a second action, and similarly, a second action can also be referred to as a first action. Both the first action and the second action can be actions, and in some cases, can be separate and different actions.

[0119] Here, at least one means one or more than one, for example, at least one action can be one action, two actions, three actions, or any other action that is an integer greater than or equal to one. And multiple means two or more than two, for example, multiple actions can be two actions, three actions, or any other action that is an integer greater than or equal to two.

[0120] Figure 1 It is a schematic diagram of an implementation environment provided according to an embodiment of the present application, and the implementation environment may include a terminal 101 and a server 102.

[0121] In the terminal 101, an NPU is provided, for example, an NPU provided on a computer.

[0122] The terminal 101 may be a smart phone with an NPU, a wearable device, a personal computer, a laptop, a tablet computer, a smart TV, a car terminal, etc.

[0123] The server 102 may be a single server, a server cluster consisting of multiple servers, or a cloud processing center.

[0124] The terminal 101 is connected to the server 102 via a wired or wireless network.

[0125] In some embodiments, the wireless network or wired network uses standard communication technology and / or protocol. The network is usually the Internet, but it can also be any network, including but not limited to any combination of local area network (LAN), metropolitan area network (MAN), wide area network (WAN), mobile, wired or wireless network, private network or virtual private network. In some embodiments, the data exchanged through the network is represented by technology and / or format including Hyper Text Mark-up Language (HTML), Extensible Markup Language (XML), etc. In addition, conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Network (VPN), Internet Protocol Security (IPsec) can also be used to encrypt all or some links. In other embodiments, customized and / or dedicated data communication technology can also be used to replace or supplement the above data communication technology.

[0126] Figure 2 2 is a schematic diagram of the structure of an NPU 200 provided according to an embodiment of the present application, including: a control module 201.

[0127] In one example, DDR (Double Data Rate Synchronous Dynamic Random Access Memory), RDMA (Remote Direct Memory Access), OCM (On Chip Memory), and control module 201 are electrically connected in sequence. RDMA reads instruction sets from DDR and outputs the instruction sets to OCM. Control module 201 obtains instruction sets from OCM.

[0128] For example, the read bit width of RDMA is 128 bits or 256 bits.

[0129] In one example, a parser and an executor are provided in the control module 201. The parser parses the instruction to obtain a parsing result. The executor executes the parsing result. The parsing result includes an operation type, an address, and data.

[0130] The executor executing the parsing result can be understood as the executor acquiring data based on the parsing result. The NPU 200 processes the data based on the parsing result.

[0131] In some embodiments, the control module 201 is used to obtain and parse an instruction set or an instruction, wherein the instruction set includes multiple instructions, each instruction has the same number of bits, and the first position is the same as the second position; the first position is the position of the first type of indication information included in the instruction in the instruction, and the second position is the position of the second type of indication information included in the instruction in the instruction.

[0132] The control module 201 is further used to determine the running time and running time of the tth task being executed by the NPU 200 based on the first type of indication information; t is an integer greater than or equal to 1; each task corresponds to at least one instruction.

[0133] The control module 201 is also used to determine the operation type corresponding to the instruction based on the second type of indication information, and control the NPU 200 to perform the operation corresponding to the operation type; the operation type at least includes a configuration operation and a processing operation.

[0134] In one example, in addition to the control module 201, other modules exist in the NPU 200. Other modules may be a scheduling module and a computing module. For example, the computing module performs a computing task, which may be relatively complex, and is therefore divided into multiple subtasks, each of which corresponds to an instruction. That is, the computing task corresponds to multiple instructions.

[0135] In one example, the control module 201 presets fixed parameters and obtains instruction data from the OCM based on the preset fixed parameters. The preset fixed parameters are used to instruct the control module 201 to intercept the instruction data once every fixed bit width to obtain an instruction, so that there is no need to additionally determine the specific length of each instruction, thereby simplifying the operation logic, thereby saving the number of registers used to store the operation logic, reducing the hardware area, and reducing the complexity of the hardware.

[0136] For example, each instruction is composed of a 64-bit binary number, that is, the read bit width of RDMA is an integer multiple of the bit width of the instruction, so that the control module 201 can perform interception operations, that is, the control module 201 intercepts the instruction data in the OCM once every 64 bits, thereby realizing the parsing of the instruction set.

[0137] In one example, the first position of each instruction is the same as the second position, and the control module 201 has the same logic for parsing and reading the information of the first position of each instruction, and the same logic for parsing and reading the second position, thereby simplifying the instruction reading logic and parsing logic, improving the instruction reading and parsing efficiency, reducing the number of registers used to store the reading logic and parsing logic, reducing the hardware area, and reducing the hardware complexity.

[0138] In addition, since the first position for storing the first type of indication information and the second position for storing the second type of indication information in each instruction are the same, only one type of register is needed to store the first type of indication information in each instruction. Similarly, only one type of register is needed to store the second type of indication information in each instruction. In the related art, the positions for storing the first type of indication information and the second type of indication information in different instructions may be different. Therefore, multiple registers are needed to store the first type of indication information and the second type of indication information of different instructions respectively. Therefore, compared with the related art, the technical solution of the present application further reduces the number of registers and reduces the hardware area.

[0139] For example, 7 bits in the instruction are used as the first position, and the other 8 bits in the instruction are used as the second position.

[0140] In some embodiments, the first type of indication information includes dot information and task update information;

[0141] The control module 201 is also used to control the NPU 200 not to print the running time based on the dot information; the running time is the start time or end time of the task; the running time is obtained based on the start time and end time of the task.

[0142] The running time is the difference between the end time and the start time.

[0143] or the control module 201 is further used to control the NPU 200 to print a start time or an end time based on the dotting information;

[0144] The control module 201 is also used to determine that the NPU 200 is executing the t+1th task based on the task update information; control the NPU 200 to print the start time or end time of the t+1th task based on the dot information; or determine that the NPU 200 is executing the tth task based on the task update information; control the NPU 200 to print the start time or end time of the tth task based on the dot information.

[0145] In an example, for the tth task, the actual running time of the tth task, that is, the running time, can be determined according to the difference between the end time and the start time.

[0146] For example, one bit in the instruction is used to store task update information. The task update information indicates whether the currently executed task is a new task.

[0147] For another example, one bit of the instruction is used to store dotting information, and the dotting information indicates whether dotting is to be performed.

[0148] In some embodiments, the first type of indication information further includes verification information; the verification information includes an initial verification code;

[0149] The control module 201 is also used to determine whether the corresponding instruction is abnormal based on the verification information; the abnormality indicates that the NPU 200 times out and generates an interrupt or an error occurs in the operation of the NPU 200;

[0150] Wherein, when the initial verification code is consistent with the actual verification code, the control module 201 determines that the corresponding instruction is normal; the actual verification code is generated when the NPU 200 parses the corresponding instruction;

[0151] Or when the initial verification code is inconsistent with the actual verification code, the control module 201 determines that an abnormality occurs in the corresponding instruction.

[0152] In one example, a running time threshold of the tth task is preset, and when the actual running time of the tth task exceeds the preset running time threshold, the NPU 200 times out and generates an interrupt. Or when the NPU 200 executes the tth task, an error may occur during operation.

[0153] In one example, when the NPU 200 times out and generates an interrupt, or an error occurs during operation, the instruction being executed is stopped. In order to find the reason why the NPU 200 times out and generates an interrupt, or an error occurs during operation, the instruction being executed is found from the register. In particular, a register is provided in the control module 201, and the register is used to store the instruction being executed.

[0154] Specifically, the control module 201 reads the verification information of the instruction and obtains the actual verification code; compares the actual verification code with the initial verification code. If the actual verification code is inconsistent with the initial verification code, it indicates that there is an error in the instruction. If the actual verification code is consistent with the initial verification code, it indicates that there is no error in the instruction. Among them, the verification information indicates the initial verification code. In the process of parsing the instruction, the relevant software can calculate the initial verification code corresponding to the instruction. When an error occurs in the instruction, the actual verification code of the instruction read is inconsistent with the initial verification code.

[0155] In one example, if there is no error in the instruction, it is determined whether the data required for the normal operation of the instruction is not obtained. If the required data is not obtained, the failure to obtain the required data is the cause of the NPU 200 abnormality; or if the required data is obtained, other causes of the NPU 200 abnormality are searched for.

[0156] For example, the verification code is a CRC (Cyclic Redundancy Check) value.

[0157] For example, 5 bits in the instruction are used to store verification information.

[0158] In some embodiments, each instruction in the instruction set also includes a spare location.

[0159] The free position is a position that is not currently occupied. It can be used to store additional information of the instruction according to actual needs, thereby improving the configuration flexibility of the instruction and increasing the function of the instruction.

[0160] For ease of description, in the embodiments of the present application, [a:b] is used to represent the bth bit to the ath bit, [c] represents the cth bit, and a, b and c are integers greater than or equal to 0.

[0161] For example, in the instructions involved in the embodiments of the present application, [7:0] are all used to store the second type of indication information. [12:8] are all used to store verification information. The 18th bit is used to store task update information. The 19th bit is used to store dotting information. [7:0], [12:8],

[18] and

[19] are not repeated in the following exemplary description of each instruction.

[0162] For example, the authentication information is represented as cmd_crc.

[0163] For example, the task update information is represented as trace_segment_en. When the value of trace_segment_en is 1, it indicates that the task being executed by the NPU 200 is a new task, that is, the NPU 200 starts to execute the t+1th task. Or when the value of trace_segment_en is 0, it indicates that the task being executed by the NPU 200 is not a new task, that is, the NPU 200 is still executing the tth task.

[0164] For example, the dot information is represented by trace_set_point. When the value of trace_set_point is 1, it means that the time needs to be printed. When the value of trace_set_point is 0, it means that the time does not need to be printed.

[0165] When the value of trace_set_point is 1 and the value of trace_segment_en is 1, the time is printed, and the time is the start time of the t+1th task.

[0166] Among them, cmd_crc, trace_set_point and trace_segment_en can all be recognized by the control module 201.

[0167] Figure 3 It is a structural diagram of a configuration instruction provided according to an embodiment of the present application.

[0168] Combine the following Figure 3 The configuration instructions are described by way of example.

[0169] In some embodiments, the instruction set includes configuration instructions; the configuration instructions also include first address information and first data information.

[0170] The control module 201 is further configured to determine the address of the first function register based on the first address information.

[0171] The control module 201 is further configured to configure the first data information to the first function register based on the second type of indication information of the configuration instruction; the first function register is set in the NPU 200.

[0172] The control module 201 includes a plurality of function registers and general registers, each of which has a bit width of 32 bits.

[0173] In one example, the control module 201 parses the configuration instruction to obtain a parsing result, and acquires the first data information from the first function register based on the parsing result. The control module 201 configures the first function register based on the first data information.

[0174] For example, 10 bits in the configuration instruction are used to store the first address information, and 32 bits in the configuration instruction are used to store the first data information.

[0175] For example, [17:13] of the configuration instruction is an idle position. [31:20] of the configuration instruction is used to store the first address information. [63:32] of the configuration instruction is used to store the first data information.

[0176] For another example, the second type of indication information of the configuration instruction is assigned a value of 0XA1, indicating a configuration operation. The first address information is represented as regs_addr. The first data information is represented as regs_value.

[0177] in, Figure 3The first address information in omits the 20th to 29th bits. That is, the actual addressing is the 20th to 29th bits.

[0178] Figure 4 It is a structural diagram of a loading instruction provided according to an embodiment of the present application.

[0179] Combine the following Figure 4 The load instruction is exemplified.

[0180] In some embodiments, the instruction set further includes a load instruction; the load instruction further includes second address information, quantity information, and second data information.

[0181] The control module 201 is further configured to determine the address of the first general register in the control module 201 to be rewritten based on the second address information.

[0182] The control module 201 is further configured to determine the number of first general registers to be rewritten based on the quantity information.

[0183] The control module 201 is further configured to determine an address of the loaded data in the memory based on the second data information.

[0184] The control module 201 is further configured to load the load data into the first general register based on the second type of indication information of the load instruction; the address of the load data includes an initial address and an offset address.

[0185] In one example, the control module 201 parses the load instruction, obtains the parsing result, obtains the load data based on the parsing result, and performs the load operation on the load data. For example, the control module 201 obtains some load data from the OCM and loads it into the first general register.

[0186] In one example, the initial address is the first address of the loaded data in the OCM. The offset address is the total address that needs to be read from the first address of the loaded data in the OCM. That is, the end address of the loaded data in the OCM is the initial address + the offset address.

[0187] For example, [17:13] of the load instruction is used to store the initial address of the address of the loaded data. [24:20] of the load instruction is used to store the starting address of the first general register. [29:25] of the load instruction is used to store the number of the first general register minus 1. [31:30] of the load instruction is an idle position. [63:32] of the load instruction is used to store the offset address of the address of the loaded data.

[0188] Since the counting rule in the instruction starts from 0, the control module 201 can determine the number of first general registers actually required based on the number of first general registers minus 1. For example, if [29:25] is assigned a value of 4, the number of first general registers actually required is 5.

[0189] For another example, the second type of indication information of the load instruction is assigned a value of 0XA7, indicating a load operation. The initial address can be represented as gprs_idx. The starting address of the first general register is represented as gprs_idx_start. gprs_idx_start can be assigned a value of "00000". The number of first general registers minus 1 can be represented as gprs_cnt_num_m1. The offset address is represented as loadm_offs_et_4B, and 2 bits of the offset address are omitted. That is, the actual addressing of the offset address is from the 32nd bit to the 61st bit. The offset address is 4-byte aligned, that is, 4B aligned. The idle position is represented as reserved.

[0190] Among them, gprs_idx, gprs_idx_start, gprs_cnt_num_m1, loadm_offs_et_4B and reserved can all be recognized by the control module 201.

[0191] Figure 5 It is a structural diagram of a movement instruction provided according to an embodiment of the present application.

[0192] Combine the following Figure 5 The load instruction is exemplified.

[0193] In some embodiments, the instruction set further includes a move instruction; the move instruction further includes third address information and fourth address information.

[0194] The control module 201 is further configured to determine the address of the second general register in the control module 201 based on the third address information.

[0195] The control module 201 is further configured to determine an address of a second function register in the NPU 200 based on the fourth address information.

[0196] The control module 201 is further configured to control the NPU 200 to move the data in the second general register to the second function register based on the second type of indication information of the move instruction.

[0197] In one example, the control module 201 parses the move instruction to obtain a parsing result, and obtains the data to be moved from the second general register based on the parsing result. The NPU 200 moves the data to be moved to the second function register based on the parsing result.

[0198] For example, [17:13] of the move instruction is an idle position. [31:20] is used to store the starting address of the second function register. [36:32] is used to store the starting address of the second general register. [41:37] is used to store the number of the second general register minus 1. [63:42] is an idle position.

[0199] For another example, the second type of indication information of the load instruction is assigned a value of 0XA8, indicating a move operation. The starting address of the second function register can be represented as regs_addr. The starting address of the second general register is represented as gprs_idx_start. The number of the second general register minus 1 can be represented as gprs_cnt_num_m1. The free position is represented as reserved.

[0200] For another example, when regs_addr is assigned a value of 0XF, gprs_idx_start is assigned a value of 0X8, and gprs_cnt_num_m1 is assigned a value of 0X4, the move instruction indicates that the data in gpr[8] is moved to the second function register with a starting address of 0XF. The data in gpr[9] is moved to the second function register with an address of 0X10. The data in gpr

[10] is moved to the second function register with an address of 0X11. The data in gpr

[11] is moved to the second function register with an address of 0X12. The data in gpr

[12] is moved to the second function register with an address of 0X13.

[0201] Generally, in the related art, the data to be moved is directly written into the instruction, and the data bit width read from the register is 32 bits, that is, the data needs to occupy 32 bits of the instruction. In the embodiment of the present application, the data is not directly stored in the instruction, but the starting address of the second general register for storing data is stored, and the bit width of the starting address is 5 bits. Therefore, storing the starting address can save the bit width of the instruction, so that each instruction can store more information, thereby reducing the number of required instructions, shortening the loading time and parsing time of the instruction, and improving the parsing efficiency of the instruction.

[0202] In addition, configuring the function register based on the move instruction can be used as a second way to configure the function register, thereby improving the flexibility of configuring the function register.

[0203] In some embodiments, the NPU includes a scheduling module, which is used to perform synchronization operations. The synchronization operations include generating interrupts and scheduling other modules. The scheduling module generates interrupts based on interrupt instructions and schedules other modules based on update instructions and wait instructions.

[0204] The interrupt instruction, the update instruction and the wait instruction are respectively exemplarily described below with reference to the accompanying drawings.

[0205] Figure 6 It is a structural diagram of an interrupt instruction provided according to an embodiment of the present application.

[0206] Combine the following Figure 6 An example explanation of the interrupt instruction is given.

[0207] In some embodiments, the NPU 200 further includes a scheduling module; the control module 201 is electrically connected to the scheduling module; the instruction set further includes an interrupt instruction; the interrupt instruction further includes a third type of indication information; the third type of indication information is used to indicate an operation type;

[0208] The control module 201 is further used to control the scheduling module to generate an interrupt based on the second type of indication information and the third type of indication information of the interrupt instruction.

[0209] In one example, the control module 201 parses the interrupt instruction to obtain a parsing result, and the scheduling module generates an interrupt based on the parsing result.

[0210] For example, [17:13] of the interrupt instruction is an idle position. [31:20] is an idle position. [35:32] is used to store the third type of indication information. [63:32] is an idle position.

[0211] For another example, the second type of indication information of the interrupt instruction is assigned a value of 0XA2, and the third type of indication information is assigned a value of 0X1, and the second type of indication information and the third type of indication information together indicate an interrupt operation. The free position is indicated as reserved.

[0212] In some embodiments, the NPU 200 further includes a convolution module and a data transmission module; the control module 201 is electrically connected to the data processing module and the data transmission module respectively; the scheduling module is electrically connected to the data processing module and the data transmission module respectively;

[0213] The instruction set also includes an update instruction and a wait instruction; the update instruction and the wait instruction also include a third type of indication information;

[0214] The control module 201 is further used to control the convolution module to wait for the third function register to be updated and to update the fourth function register based on the second type of indication information and the third type of indication information of the waiting instruction;

[0215] The control module 201 is further used to control the data processing module or the data transmission module to update the third function register based on the second type of indication information and the third type of indication information of the update instruction;

[0216] A scheduling module, configured to notify a waiting data processing module or a waiting data transmission module to end a waiting operation after detecting that the third function register is updated to a corresponding value;

[0217] The control module is also used to control the data transmission module or the data processing module to update the third function register; the third function register is set in the scheduling module.

[0218] In one example, the scheduling module is also used to schedule the work of other modules in the NPU 200. The scheduling module includes a plurality of function registers, which are used for other modules to write the information of the task being executed into a function register of the scheduling module through an update instruction.

[0219] In one example, the NPU 200 further includes a data processing module and a data transmission module. The scheduling module is electrically connected to the data transmission module and the data processing module respectively. The control module 201 parses the update instruction to obtain a parsing result. The data transmission module is updated based on the parsing result. The control module 201 parses the waiting instruction to obtain a parsing result. The data processing module waits based on the parsing result.

[0220] In one example, the data processing module needs to wait for the task being executed by the data transmission module to end. Then the data processing module waits for a function register in the scheduling module to be updated based on the waiting instruction. After the task being executed by the data transmission module ends, the function register being waited for in the scheduling module is updated. When the scheduling module detects that the value of the third function register being waited for has been updated, the scheduling module feeds back to the data processing module, that is, notifies the data processing module that the waiting operation is over, and then the data processing module ends waiting.

[0221] For example, when the data transmission module writes 1 to the third function register in the scheduling module, if the scheduling module detects that the value of the third function register being waited has been updated to 1, the scheduling module feeds back to the data processing module, that is, notifies the data processing module that the waiting is over, and the data processing module ends the waiting.

[0222] Figure 7 It is a structural diagram of an update instruction provided according to an embodiment of the present application.

[0223] Combine the following Figure 7 An example of an update instruction is given.

[0224] In some embodiments, the update instruction further includes first determination information, first absolute address information, first relative address information, and an initial update value;

[0225] The control module 201 is further used to determine that first initial data needs to be acquired based on the first determination information; the first initial data is part of the data of the third general register; the third general register is set in the control module 201;

[0226] The control module 201 is further configured to determine an address of a third general register based on the first absolute address information;

[0227] The control module 201 is further configured to determine an address of a third function register based on the first relative address information;

[0228] The control module 201 is further used to control the data processing module or the data transmission module to write the initial update value and the first initial data into the third function register based on the second type of indication information and the third type of indication information of the update instruction.

[0229] In one example, the data stored in the upper 16 bits of the third general register is used as the first initial data, or the data stored in the lower 16 bits of the third general register is used as the first initial data.

[0230] In an example, the control module 201 controls the data transmission module to write the sum of the initial update value and the first initial data into the third function register.

[0231] In some embodiments, the control module 201 is further configured to determine, based on the first determination information, that it is not necessary to obtain the first initial data.

[0232] The control module 201 is further configured to determine an address of a third function register based on the first relative address information;

[0233] The control module 201 is further used to control the data processing module or the data transmission module to write the initial update value into the third function register based on the second type of indication information and the third type of indication information of the update instruction.

[0234] In one example, after the task being executed by the data transmission module is completed, the first initial data is obtained from the third general register, and the function register being waited in the scheduling module is updated based on the initial update value in the update instruction and / or the first initial data.

[0235] For example, [17:13] of the update instruction is an idle position. The 20th bit is used to store the upper 16 bits or the lower 16 bits. [25:21] is used to store the first absolute address information. The 26th bit is used to store the first determination information. [31:27] is an idle position. [35:32] is used to store the third type of indication information. [51:36] is used to store the initial update value. [57:52] is used to store the first relative address information. [63:58] is an idle position.

[0236] For another example, the 20th bit is expressed as high or low. When the 20th bit is assigned a value of 1, the 20th bit is expressed as high, that is, the data stored in the upper 16 bits of the third general register is used as the first initial data. Or when the 20th bit is assigned a value of 0, the 20th bit is expressed as low, that is, the data stored in the lower 16 bits of the third general register is used as the first initial data.

[0237] For another example: the second type of indication information of the update instruction is assigned a value of 0XA2. The first absolute address information is represented as sync_base_gpr_addr. The third type of indication information is assigned a value of 0X2. The first determination information is represented as sync_base_value_en. When sync_base_value_en is assigned a value of 1, it indicates that the first initial data needs to be obtained. When sync_base_value_en is assigned a value of 0, it indicates that the first initial data does not need to be obtained. The initial update value is represented as update_reg_value. The value assigned to update_reg_value is the initial update value. The first relative address information is represented as update_reg_addr. The free position is represented as reserved.

[0238] For another example, when sync_base_value_en is set to 1 and the 20th bit is set to 0, [51:36]+gprs[25:21][15:0] is written into the third function register, where gprs[25:21][15:0] represents the data stored in the lower 16 bits of the third general register.

[0239] Figure 8 It is a structural diagram of a waiting instruction provided according to an embodiment of the present application.

[0240] Combine the following Figure 8 The wait instruction is exemplified.

[0241] In some embodiments, the wait instruction further includes second determination information, second absolute address information, second relative address information, and an initial wait value.

[0242] The control module 201 is further used to determine that the second initial data needs to be acquired based on the second determination information; the second initial data is a part of the data of the fourth general register. The fourth general register is set in the control module 201;

[0243] The control module 201 is further configured to determine an address of a fourth general register based on the second absolute address information;

[0244] The control module 201 is further configured to determine an address of a fourth function register based on the second relative address information;

[0245] The control module 201 is further used to control the data processing module or the data transmission module to write the initial waiting value and the second initial data into the fourth function register; the fourth function register is stored in the scheduling module.

[0246] In one example, the data stored in the upper 16 bits of the fourth general register is used as the second initial data, or the data stored in the lower 16 bits of the fourth general register is used as the second initial data.

[0247] In an example, the control module 201 controls the data processing module or the data transmission module to write the sum of the initial waiting value and the second initial data into the fourth function register.

[0248] In some embodiments, the control module 201 is further configured to determine that it is not necessary to obtain the second initial data based on the second determination information;

[0249] The control module 201 is further configured to determine an address of a fourth function register based on the second relative address information;

[0250] The control module 201 is further used to control the data processing module or the data transmission module to write the initial waiting value into the fourth function register.

[0251] In one example, the data processing module or the data transmission module obtains the second initial data from the fourth general register, and updates the fourth function register based on the second initial data and / or the initial wait value in the wait instruction.

[0252] For example, [17:13] of the wait instruction is an idle position. The 20th bit is used to store the read high 16 bits or the read low 16 bits. [25:21] is used to store the second absolute address information. The 26th bit is used to store the second determination information. [31:27] is an idle position. [35:32] is used to store the third type of indication information. [51:36] is used to store the initial wait value. [57:52] is used to store the second relative address information. [63:58] is an idle position.

[0253] For another example, the 20th bit is expressed as high or low. When the 20th bit is assigned a value of 1, the 20th bit is expressed as high, that is, the data stored in the upper 16 bits of the fourth general register is used as the second initial data. Or when the 20th bit is assigned a value of 0, the 20th bit is expressed as low, that is, the data stored in the lower 16 bits of the fourth general register is used as the second initial data.

[0254] For another example, the second type of indication information of the wait instruction is assigned a value of 0XA2. The second absolute address information is represented as sync_base_gpr_addr. The third type of indication information is assigned a value of 0X3. The second confirmation information is represented as sync_base_value_en.

[0255] When sync_base_value_en is set to 1, it indicates that the second initial data needs to be obtained. Or when sync_base_value_en is set to 0, it indicates that the second initial data does not need to be obtained.

[0256] The initial wait value is represented by wait_reg_value. The value assigned to wait_reg_value is the initial wait value. The second relative address information is represented by wait_reg_addr. The free position is represented by reserved.

[0257] For another example, when sync_base_value_en is set to 1 and the 20th bit is set to 1, [51:36]+gprs[25:21][31:16] is written into the fourth function register, where gprs[25:21][31:16] represents the data stored in the upper 16 bits of the fourth general register.

[0258] In some embodiments, the first address position and the second address position are the same; the first address position is the position of the first absolute address information in the update instruction; the second address position is the position of the second absolute address information in the wait instruction;

[0259] The first indication position, the second indication position and the third indication position are the same; the first indication position is the position of the third type of indication information in the interrupt instruction; the second indication position is the position of the third type of indication information in the update instruction; the third indication position is the position of the third type of indication information in the wait instruction.

[0260] In the embodiment of the present application, the position of the first absolute address information in the update instruction is the same as the position of the second absolute address information in the wait instruction, so that the control module 201 uses the same parsing logic when parsing the first absolute address information and the second absolute address information. In addition, the position of the third type of indication information in the interrupt instruction, the position in the update instruction, and the position in the wait instruction are the same, and the control module 201 uses the same parsing logic when parsing the third type of indication in these three instructions, thereby simplifying the parsing logic of the instruction and improving the parsing efficiency of the instruction.

[0261] Fig. 9 It is a structural diagram of a waiting task completion instruction provided according to an embodiment of the present application.

[0262] Combine the following Fig. 9 An example explanation of the instruction of waiting for task completion is given.

[0263] In some embodiments, the instruction set further includes a waiting task completion instruction; the waiting task completion instruction further includes waiting indication information;

[0264] The control module 201 is further used to control the NPU 200 to perform a waiting operation based on the second type of indication information of the waiting task completion instruction;

[0265] The control module 201 is further used to control the NPU 200 to wait for the data transmission task to be completed based on the waiting indication information;

[0266] or the control module 201, further configured to control the NPU 200 to wait for the data processing task to be completed based on the waiting indication information;

[0267] Or the control module 201 is also used to control the NPU 200 to wait for the data transmission task to be completed and the data processing task to be completed.

[0268] In some embodiments, the NPU 200 further includes a data module, which is electrically connected to the control module 201. The control module 201 parses the waiting task completion instruction, obtains a parsing result, and acquires data based on the parsing result. The data module processes the data based on the parsing result.

[0269] The data module includes at least one data transmission submodule and at least one data processing submodule. The data transmission submodule is used to perform data transmission tasks. The data processing submodule is used to perform data processing tasks.

[0270] During the operation of the NPU 200, the data processing submodule and the data transmission submodule may be started successively. The tasks of the data transmission submodule and the data processing submodule are independent and can be run at the same time. However, the running time of the current task of the data transmission submodule may also be shorter than the running time of the current task of the data processing submodule.

[0271] In one example, the data transmission submodule only needs to wait for the current task of the data transmission submodule to finish running, without waiting for the current task of the data processing submodule to finish running, and the data transmission submodule starts to execute the next data transmission task.

[0272] In one example, the data transmission submodule only needs to wait for the current task of the data processing submodule to finish running before it starts to execute the next data transmission task.

[0273] In one example, the data transmission submodule starts to execute the next data transmission task after waiting for the current task of the data transmission submodule and the current task of the data processing submodule to finish.

[0274] For example, the wait task completion instruction specifies 8 bits to store the wait indication information.

[0275] For another example, when the data module includes 4 data transmission submodules and 4 data processing submodules, 1 bit out of 8 bits is used to store the first sub-wait indication information. The first sub-wait indication information is used to indicate whether it is necessary to wait for the current task of 1 data transmission submodule to finish running. That is, 4 bits out of 8 bits can be used to store 4 first sub-wait indication information. The other 4 bits out of 8 bits can be used to store 4 second sub-wait indication information. The second sub-wait indication information is used to indicate whether it is necessary to wait for the current task of 1 data processing submodule to finish running.

[0276] When the first sub-wait indication information is assigned a value of 1, it indicates that it is necessary to wait for the current task of a data transmission submodule to finish running. When the second sub-wait indication information is assigned a value of 0, it indicates that it is not necessary to wait for the current task of a data processing submodule to finish running.

[0277] For another example, when the data module includes 4 data transmission submodules and 4 data processing submodules, 1 bit of the 8 bits is used to store the waiting indication information, and the remaining 7 bits are idle. When the waiting indication information is assigned a value of 1, it means that it is necessary to wait for the current tasks of all data processing submodules and all data transmission submodules to complete.

[0278] For another example, when the data module includes 2 data transmission submodules and 2 data processing submodules, 1 bit of the 8 bits is used to store the waiting indication information, and the remaining 7 bits are idle. When the waiting indication information is assigned a value of 1, it means that it is necessary to wait for the current tasks of all data processing submodules and all data transmission submodules to complete.

[0279] For another example: [17:13] of the waiting task completion instruction is an idle position. [27:20] is used to store the waiting instruction information. [63:28] is an idle position.

[0280] The waiting indication information is represented by an 8-bit disable field. The second type of indication information of the waiting task completion instruction is assigned a value of 0XA3. The idle position is represented by reserved.

[0281] In the embodiment of the present application, except for instructions that need to wait until data processing and data transmission are completed, the execution of other instructions can be completed within two clock cycles.

[0282] In an embodiment of the present application, at least one bit in the waiting task completion instruction is used to store waiting indication information, wherein the number of bits and the number of sub-modules indicated by the waiting indication information can be adjusted according to actual needs, greatly increasing the flexibility of instruction configuration.

[0283] Fig.10 It is a structural diagram of a no-operation instruction provided according to an embodiment of the present application.

[0284] Combine the following Fig.10 An example description of a no-operation instruction is given.

[0285] In some embodiments, the instruction set further includes a no-operation instruction; the no-operation instruction further includes number information; the number information indicates a target number of no-operations;

[0286] The control module 201 is further configured to control the NPU 200 to execute a target number of no-operations based on the second type of indication information of the no-operation instruction.

[0287] The control module 201 parses the no-operation instruction and controls the NPU 200 to execute the target number of no-operations. Since the no-operation instruction does not include the actual data to be processed, the execution of the no-operation by the NPU 200 does not affect the running result of the task.

[0288] In one example, 32 bits in the no-operation instruction are used to store the number information.

[0289] For example, [17:13] in the no-operation instruction is an idle position. [31:20] is an idle position. [63:32] is used to store the count information.

[0290] For another example, the number of times information is represented as wait_cycles_m1. The value of wait_cycles_m1 is the number of cycles of the no-operation minus 1. The second type of indication information of the no-operation instruction is assigned a value of 0XA4. The free position is represented as reserved.

[0291] Fig.11 It is a structural diagram of a jump instruction provided according to an embodiment of the present application.

[0292] Combine the following Fig.11 The jump instruction is described exemplarily.

[0293] In some embodiments, the instruction set further includes a jump instruction; the jump instruction further includes jump address information;

[0294] The control module 201 is further used to interrupt the acquisition of all unacquired instructions in the initial instruction queue based on the second type of indication information of the jump instruction; acquire each preset instruction in the preset instruction sequence; the initial instruction queue is part of the instruction set; the preset instruction sequence is part of the instruction set;

[0295] The control module 201 is also used to determine the address of the fifth general register based on the jump address information; the fifth general register is used to store the base address; the base address is used to store the preset instruction sequence; the fifth general register is set in the control module 201.

[0296] The base address is the address in OCM.

[0297] In one example, the control module 201 parses the jump instruction, obtains the parsing result, and obtains all remaining instructions in the initial instruction queue from the OCM based on the parsing result interrupt. The control module 201 starts to obtain the preset instruction from the preset instruction sequence stored at the base address.

[0298] In one example, 5 bits in a jump instruction are used to store jump address information.

[0299] For example: [17:13] of the jump instruction is used to store the jump address information. [31:20] is an idle location. [63:32] is an idle location.

[0300] For another example, the jump address information is represented as gpr_addr. The second type of indication information of the jump instruction is assigned a value of 0XA5.

[0301] Fig.12 It is a structural diagram of a skip instruction provided according to an embodiment of the present application.

[0302] Combine the following Fig.12 The skip instruction is exemplified.

[0303] In some embodiments, the instruction set further includes a skip instruction; the skip instruction further includes validation information and skip quantity information;

[0304] The control module 201 is further used to determine whether a skip operation needs to be performed based on the validation information;

[0305] The control module 201 is further configured to skip the number of unparsed instructions based on the second type of instruction information of the skip instruction; parse the target instruction in the initial instruction queue; the target instruction is the next unparsed instruction of the number of unparsed instructions; or

[0306] The control module 201 is further used to determine that a skip operation does not need to be performed based on the validation information;

[0307] The control module 201 is further configured to directly parse the next unparsed instruction in the initial instruction queue.

[0308] In one example, the control module 201 parses the skip instruction and controls the NPU 200 to perform the skip operation based on the skip instruction. The NPU 200 determines the instructions to be skipped based on the validity information and the skip quantity information, and only scans the instructions to be skipped without parsing them.

[0309] In one example, 5 bits in the skip instruction are used to store validation information, and 32 bits in the skip instruction are used to store skip quantity information.

[0310] For example, [17:13] of the skip instruction is an idle position. [24:20] is used to store the effective information. [31:25] is an idle position. [63:32] is used to store the skip quantity information.

[0311] For another example, the skip number information is represented as skip_num_m1. The validity information is represented as gprs_id. When gprs_id is assigned a value of 1, the skip instruction is valid and the skip operation needs to be performed. When gprs_id is assigned a value of 0, the skip instruction is invalid and the skip operation does not need to be performed. The second type of indication information of the skip instruction is assigned a value of 0XA6. The free position is represented as reserved.

[0312] Fig.13 It is a structural diagram of a reset instruction provided according to an embodiment of the present application.

[0313] Combine the following Fig.13 The reset instruction is exemplified.

[0314] In some embodiments, the instruction set further includes a reset instruction;

[0315] The control module 201 is further configured to control the NPU 200 to perform a reset operation based on the second type of indication information in the reset instruction.

[0316] Among them, the reset instruction is used to block the execution of subsequent instructions.

[0317] In one example, when the control module 201 receives a reset instruction, it first checks the status of the bus and other modules. If the bus and other modules are in an idle state, the control module 201 parses the reset instruction, obtains a parsing result, configures a clear signal based on the parsing result, and resets the registers based on the clear signal.

[0318] For example, the second type of indication information of the reset instruction is assigned a value of 0XA9. The free position is indicated as reserved.

[0319] Fig.14It is a structural diagram of an addition instruction provided according to an embodiment of the present application.

[0320] Combine the following Fig.14 An example of an addition instruction is given below.

[0321] In some embodiments, the instruction set further includes an addition instruction; the addition instruction further includes operation information, an immediate value, a first initial value, write address information, a second initial value, and read address information;

[0322] The control module 201 is further used to determine the addition type based on the operation information;

[0323] The control module 201 is further configured to determine an initial value of a sixth general register based on the first initial value; the sixth general register is set in the control module 201;

[0324] The control module 201 is further used to determine the address of the sixth general register based on the write address information;

[0325] The control module 201 is further configured to determine an initial value of a seventh general register based on the second initial value; the seventh general register is set in the control module 201;

[0326] The control module 201 is further configured to determine the address of the seventh general register based on the read address information;

[0327] The control module 201 is further configured to control the NPU 200 to perform an addition operation based on the second type of indication information of the addition instruction.

[0328] In one example, the control module 201 parses the addition instruction, obtains a parsing result, and obtains data based on the parsing result. The NPU 200 modifies the initial value of the sixth general register based on the parsing result and the data.

[0329] In one example, each addition instruction includes one addition type. Different addition instructions include the same or different addition types.

[0330] In some embodiments, the control module 201 is further configured to control the NPU 200 to write the immediate value into the sixth general register based on the second type of indication information and the operation information of the addition instruction when the operation information indicates the first addition type;

[0331] or the control module 201, further configured to control the NPU 200 to write the immediate value and the first initial value into the sixth general register based on the second type of indication information and the operation information of the addition instruction when the operation information indicates the second addition type;

[0332] or the control module 201 is further configured to control the NPU 200 to write the immediate value and the second initial value into the sixth general register based on the second type of indication information and the operation information of the addition instruction when the operation information indicates the third addition type;

[0333] Or the control module 201 is further used to control the NPU 200 to write the first initial value and the second initial value into the sixth general register based on the second type of indication information and the operation information of the addition instruction when the operation information indicates the fourth addition type.

[0334] In one example, when the operation type in the parsing result is the first addition type, the NPU 200 writes the immediate value into the sixth general register.

[0335] In one example, when the operation type in the parsing result is the second addition type, the NPU 200 calculates the sum of the immediate value and the first initial value, and writes the sum of the immediate value and the first initial value into the sixth general register.

[0336] In one example, when the operation type in the parsing result is the third addition type, the NPU 200 calculates the sum of the immediate value and the second initial value, and writes the sum of the immediate value and the second initial value into the sixth general register.

[0337] In one example, when the operation type in the parsing result is the fourth addition type, the NPU 200 calculates the sum of the initial value in the sixth general register and the initial value in the seventh general register, and writes the sum of the initial value in the sixth general register and the initial value in the seventh general register into the sixth general register.

[0338] In one example, 5 bits in the addition instruction are used to store read address information. 5 bits in the addition instruction are used to store write address information. 2 bits in the addition instruction are used to store operation information. 32 bits in the addition instruction are used to store immediate values.

[0339] For example, [17:13] is used to store read address information. [24:20] is used to store write address information. [26:25] is used to store operation information. [31:27] is an idle location. [63:32] is used to store immediate data.

[0340] For another example: the read address information is represented as gpr_Y_idx. The write address information is represented as gpr_X_idx. The operation information is represented as add_type. The immediate value is represented as IMM. The second type of indication information of the addition instruction is assigned a value of 0XAA. The free position is represented as reserved.

[0341] When add_type is assigned a value of 0, it indicates the first addition type.

[0342] When add_type is assigned a value of 1, it indicates the second addition type.

[0343] When add_type is assigned a value of 2, it indicates the third addition type.

[0344] When add_type is assigned a value of 3, it indicates the fourth addition type.

[0345] It should be noted that: when the NPU provided in the above embodiment executes the corresponding steps, it only uses the division of the above functional modules as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0346] In the embodiment of the present application, in each instruction in the instruction set, the same information is stored in some of the same bits, so the control module can use the same read logic to read and the same parsing logic to parse the same position, thereby simplifying the reading logic and parsing logic of the instruction, thereby reducing the number of registers used to store the reading logic and parsing logic, and reducing the hardware area. In addition, the same position can be read using the same read logic and the same parsing logic, which also improves the parsing efficiency of the instruction, so that each instruction can be parsed within one clock cycle.

[0347] The embodiment of the present application further provides an instruction set, which is applied to the NPU in the above embodiment, and the instruction set includes:

[0348] A plurality of instructions; each of the instructions has the same number of bits; each of the instructions includes first-type indication information and second-type indication information; the first position is the same as the second position; the first position is the position of the first-type indication information in the corresponding instruction, and the second position is the position of the second-type indication information in the corresponding instruction;

[0349] The first type of indication information is used to determine the running time and running time of the tth task being executed by the NPU; t is an integer greater than or equal to 1; each of the tasks corresponds to at least one of the instructions;

[0350] The second type of indication information is used to determine the operation type corresponding to the instruction; the operation type at least includes a configuration operation and a processing operation.

[0351] In some embodiments, the first type of indication information includes dot information and task update information;

[0352] The dot information indicates that the NPU does not print the running time; the running time is the start time or the end time of the task; the running time is obtained based on the start time and the end time of the task;

[0353] Or the dot information, instructing the NPU to print the start time or the end time;

[0354] The task update information is used to determine that the NPU is executing the t+1th task; the dot information indicates that the NPU prints the start time or the end time of the t+1th task; or the task update information is used to determine that the NPU is executing the tth task; the dot information indicates that the NPU prints the start time or the end time of the tth task.

[0355] In some embodiments, the first type of indication information further includes verification information; the verification information includes an initial verification code;

[0356] The verification information is used to determine whether an exception occurs in the corresponding instruction; the exception indicates that the NPU times out and generates an interrupt or an error occurs in the operation of the NPU;

[0357] The actual verification code is generated when the NPU parses the corresponding instruction.

[0358] In some embodiments, the instruction set includes a configuration instruction; the configuration instruction also includes first address information and first data information;

[0359] The first address information is used to determine the address of the first function register;

[0360] The second type of indication information of the configuration instruction is used to configure the first data information to the first function register; the first function register is set in the NPU.

[0361] In some embodiments, the instruction set further includes a load instruction; the load instruction further includes second address information, quantity information, and second data information;

[0362] The second address information is used to determine the address of the first general register to be rewritten;

[0363] The quantity information is used to determine the quantity of the first general register to be rewritten;

[0364] The second data information is used to determine the address of the loaded data in the memory;

[0365] The second type of indication information of the load instruction is used to load the load data into the first general register; the address of the load data includes an initial address and an offset address.

[0366] In some embodiments, the instruction set further includes a move instruction; the move instruction further includes third address information and fourth address information;

[0367] The third address information is used to determine the address of the second general register;

[0368] The fourth address information is used to determine the address of the second function register in the NPU;

[0369] The second type of indication information of the move instruction is used to move the data in the second general register to the second function register.

[0370] In some embodiments, the instruction set further includes an interrupt instruction; the interrupt instruction further includes a third type of indication information; the third type of indication information is used to indicate the operation type;

[0371] The second type of indication information and the third type of indication information of the interrupt instruction are used to indicate the generation of an interrupt.

[0372] In some embodiments, the instruction set further includes an update instruction and a wait instruction; the update instruction and the wait instruction further include the third type of indication information;

[0373] The second type of indication information and the third type of indication information of the waiting instruction are used to instruct the data processing module or the data transmission module to wait for the third function register to be updated;

[0374] The second type of indication information and the third type of indication information of the update instruction are used to instruct the data processing module or the data transmission module to update the third function register.

[0375] In some embodiments, the update instruction further includes first determination information, first absolute address information, first relative address information, and an initial update value;

[0376] The first determination information is used to determine that first initial data needs to be obtained; the first initial data is a portion of data of the third general register;

[0377] The first absolute address information is used to determine the address of the third general register;

[0378] The first relative address information is used to determine the address of the third function register;

[0379] The second type of indication information and the third type of indication information of the update instruction are used to instruct to write the initial update value and the first initial data into the third function register.

[0380] In some embodiments, the first determination information is used to determine that it is not necessary to obtain the first initial data;

[0381] The first relative address information is used to determine the address of the third function register;

[0382] The second type of indication information and the third type of indication information of the update instruction are used to indicate writing the initial update value into the third function register.

[0383] In some embodiments, the wait instruction further includes second determination information, second absolute address information, second relative address information, and an initial wait value;

[0384] The second determination information is used to determine that second initial data needs to be obtained; the second initial data is a portion of data of the fourth general register;

[0385] The second absolute address information is used to determine the address of the fourth general register;

[0386] The second relative address information is used to determine the address of the fourth function register.

[0387] In some embodiments, the second determination information is used to determine that the second initial data does not need to be acquired;

[0388] The second relative address information is used to determine the address of the fourth function register.

[0389] In some embodiments, the first address position and the second address position are the same; the first address position is the position of the first absolute address information in the update instruction; the second address position is the position of the second absolute address information in the wait instruction;

[0390] The first indication position, the second indication position and the third indication position are the same; the first indication position is the position of the third type of indication information in the interrupt instruction; the second indication position is the position of the third type of indication information in the update instruction; the third indication position is the position of the third type of indication information in the wait instruction.

[0391] In some embodiments, the instruction set further includes a waiting task completion instruction; the waiting task completion instruction further includes waiting indication information;

[0392] The second type of indication information of the waiting task completion instruction is used to instruct the NPU to perform a waiting operation;

[0393] The waiting indication information is used to instruct the NPU to wait for the data transmission task to be completed;

[0394] or the waiting indication information, used to instruct the NPU to wait for the data processing task to be completed;

[0395] Or the waiting indication information is used to instruct the NPU to wait for the data transmission task to be completed and the data processing task to be completed.

[0396] In some embodiments, the instruction set further includes a no-operation instruction; the no-operation instruction further includes number information; the number information indicates a target number of no-operations;

[0397] The second type of indication information of the no-operation instruction is used to instruct the NPU to execute a target number of no-operations.

[0398] In some embodiments, the instruction set further includes a jump instruction; the jump instruction further includes jump address information;

[0399] The second type of indication information of the jump instruction is used to indicate interrupting the acquisition of all the unacquired instructions in the initial instruction queue; acquiring each preset instruction in the preset instruction sequence; the initial instruction queue is part of the instruction set; the preset instruction sequence is part of the instruction set;

[0400] The jump address information is used to determine the address of the fifth general register; the fifth general register is used to store a base address; the base address is used to store the preset instruction sequence.

[0401] In some embodiments, the instruction set further includes a skip instruction; the skip instruction further includes validation information and skip quantity information;

[0402] The validation information is used to determine whether a skip operation needs to be performed;

[0403] The second type of indication information of the skip instruction is used to instruct the NPU to skip the skipped number of the unparsed instructions; to instruct to parse the target instruction in the initial instruction queue; the target instruction is the next unparsed instruction of the skipped number of the unparsed instructions; or

[0404] The validation information is used to determine that the NPU does not need to perform a skip operation.

[0405] In some embodiments, the instruction set further includes a reset instruction;

[0406] The second type of indication information in the reset instruction is used to instruct the NPU to perform a reset operation.

[0407] In some embodiments, the instruction set further includes an addition instruction; the addition instruction further includes operation information, an immediate value, a first initial value, write address information, a second initial value, and read address information;

[0408] The operation information is used to determine the addition type;

[0409] The first initial value is used to determine the initial value of the sixth general register;

[0410] The write address information is used to determine the address of the sixth general register;

[0411] The second initial value is used to determine the initial value of the seventh general register;

[0412] The read address information is used to determine the address of the seventh general register;

[0413] The second type of indication information of the addition instruction is used to instruct the NPU to perform an addition operation.

[0414] In some embodiments, when the operation information indicates a first addition type, the second type indication information of the addition instruction and the operation information are used to instruct the NPU to write the immediate value into the sixth general register;

[0415] or when the operation information indicates a second addition type, the second type indication information and the operation information of the addition instruction are used to instruct the NPU to write the immediate value and the first initial value into the sixth general register;

[0416] or when the operation information indicates a third addition type, the second type indication information of the addition instruction and the operation information are used to instruct the NPU to write the immediate value and the second initial value into the sixth general register;

[0417] Or when the operation information indicates the fourth addition type, the second type indication information of the addition instruction and the operation information are used to instruct the NPU to write the first initial value and the second initial value into the sixth general register.

[0418] In some embodiments, each of the instructions also includes a free location.

[0419] In the embodiment of the present application, in each instruction in the instruction set, the same information is stored in some of the same bits, so for the same position, the same read logic can be used to read and the same parsing logic can be used to parse, thereby simplifying the reading logic and parsing logic of the instruction, thereby reducing the number of registers used to store the reading logic and parsing logic, and reducing the hardware area. In addition, the same position can be read using the same read logic and the same parsing logic, which also improves the parsing efficiency of the instruction, so that each instruction can be parsed within one clock cycle.

[0420] Fig.15 is a flow chart of a control method based on an instruction set provided in an embodiment of the present application, such as Fig.15 As shown, in the embodiment of the present application, the application is described by taking the application on a terminal having an NPU 200 as an example. The method comprises the following steps:

[0421] In step 1501, the terminal obtains and parses an instruction set or an instruction, the instruction set includes a plurality of instructions, each of the instructions has the same number of bits, and the first position is the same as the second position; the first position is the position of the first type of indication information included in the instruction in the instruction, and the second position is the position of the second type of indication information included in the instruction in the instruction;

[0422] In step 1502, the terminal determines the running time and running time of the tth task being executed by the NPU based on the first type of indication information; t is an integer greater than or equal to 1; each of the tasks corresponds to at least one of the instructions;

[0423] In step 1503, the terminal determines the operation type corresponding to the instruction based on the second type of indication information, and controls the NPU to perform the operation corresponding to the operation type; the operation type at least includes a configuration operation and a processing operation.

[0424] In some embodiments, the first type of indication information includes dot information and task update information;

[0425] The method comprises:

[0426] Based on the dot information, the NPU is controlled not to print the running time; the running time is the start time or the end time of the task; the running time is obtained based on the start time and the end time of the task;

[0427] Or based on the dot information, control the NPU to print the start time or the end time;

[0428] Based on the task update information, determine that the NPU is executing the t+1th task; based on the dot information, control the NPU to print the start time or the end time of the t+1th task; or based on the task update information, determine that the NPU is executing the tth task; based on the dot information, control the NPU to print the start time or the end time of the tth task.

[0429] In some embodiments, the first type of indication information further includes verification information; the verification information includes an initial verification code;

[0430] The method further includes:

[0431] Based on the verification information, determining whether the corresponding instruction has an exception; the exception indicates that the NPU timed out and an interrupt was generated or an error occurred in the operation of the NPU;

[0432] Wherein, when the initial verification code is consistent with the actual verification code, the control module determines that the corresponding instruction is normal; the actual verification code is generated when the NPU parses the corresponding instruction;

[0433] Or when the initial verification code is inconsistent with the actual verification code, the control module determines that an exception occurs in the corresponding instruction.

[0434] In some embodiments, the instruction set includes a configuration instruction; the configuration instruction also includes first address information and first data information;

[0435] The method further includes:

[0436] determining an address of a first function register based on the first address information;

[0437] Based on the second type of indication information of the configuration instruction, the first data information is configured to the first function register; and the first function register is set in the NPU.

[0438] In some embodiments, the instruction set further includes a load instruction; the load instruction further includes second address information, quantity information, and second data information;

[0439] The method further includes:

[0440] Determine the address of the first general register to be rewritten in the control module based on the second address information;

[0441] Determining the quantity of the first general register to be rewritten based on the quantity information;

[0442] Determine an address of the loaded data in the memory based on the second data information;

[0443] Based on the second type of indication information of the load instruction, the load data is loaded into the first general register; the address of the load data includes an initial address and an offset address.

[0444] In some embodiments, the instruction set further includes a move instruction; the move instruction further includes third address information and fourth address information;

[0445] The method further includes:

[0446] Determining an address of a second general register in the control module based on the third address information;

[0447] determining an address of a second function register in the NPU based on the fourth address information;

[0448] Based on the second type of indication information of the move instruction, the NPU is controlled to move the data in the second general register to the second function register.

[0449] In some embodiments, the NPU further includes a scheduling module; the scheduling module is electrically connected to the control module; the instruction set further includes an interrupt instruction; the interrupt instruction further includes a third type of indication information; the third type of indication information is used to indicate the operation type;

[0450] The method further includes:

[0451] Based on the second type of indication information and the third type of indication information of the interrupt instruction, the scheduling module is controlled to generate an interrupt.

[0452] In some embodiments, the instruction set further includes an update instruction and a wait instruction; the update instruction and the wait instruction further include the third type of indication information;

[0453] The method further includes:

[0454] Based on the second type of indication information and the third type of indication information of the waiting instruction, control the data processing module or the data transmission module to wait for the third function register to be updated;

[0455] Based on the second type of indication information and the third type of indication information of the update instruction, control the data processing module or the data transmission module to update the third function register;

[0456] After detecting that the third function register is updated to a corresponding value, notifying the waiting data processing module or data transmission module to end the waiting operation;

[0457] The data transmission module or the data processing module is controlled to update the third function register; the third function register is set in the scheduling module.

[0458] In some embodiments, the update instruction further includes first determination information, first absolute address information, first relative address information, and an initial update value;

[0459] The method further includes:

[0460] Determining that first initial data needs to be acquired based on the first determination information; the first initial data is part of data of a third general register; the third general register is set in the control module;

[0461] determining an address of the third general register based on the first absolute address information;

[0462] determining an address of the third function register based on the first relative address information;

[0463] Based on the second type of indication information and the third type of indication information of the update instruction, the data processing module or the data transmission module is controlled to write the initial update value and the first initial data into the third function register.

[0464] In some embodiments, the method further comprises:

[0465] Determining based on the first determination information that it is not necessary to obtain the first initial data;

[0466] determining an address of the third function register based on the first relative address information;

[0467] Based on the second type of indication information and the third type of indication information of the update instruction, the data processing module or the data transmission module is controlled to write the initial update value into the third function register.

[0468] In some embodiments, the wait instruction further includes second determination information, second absolute address information, second relative address information, and an initial wait value;

[0469] The method further includes:

[0470] Determining that second initial data needs to be acquired based on the second determination information; the second initial data is a portion of data of a fourth general register; the fourth general register is set in the control module;

[0471] determining an address of the fourth general register based on the second absolute address information;

[0472] determining an address of the fourth function register based on the second relative address information;

[0473] The data processing module or the data transmission module is controlled to write the initial waiting value and the second initial data into the fourth function register; the fourth function register is set in the scheduling module.

[0474] In some embodiments, the method further comprises:

[0475] Determining, based on the second determination information, that it is not necessary to obtain the second initial data;

[0476] determining an address of the fourth function register based on the second relative address information;

[0477] The data processing module or the data transmission module is controlled to write the initial waiting value into the fourth function register.

[0478] In some embodiments, the first address position and the second address position are the same; the first address position is the position of the first absolute address information in the update instruction; the second address position is the position of the second absolute address information in the wait instruction;

[0479] The first indication position, the second indication position and the third indication position are the same; the first indication position is the position of the third type of indication information in the interrupt instruction; the second indication position is the position of the third type of indication information in the update instruction; the third indication position is the position of the third type of indication information in the wait instruction.

[0480] In some embodiments, the instruction set further includes a waiting task completion instruction; the waiting task completion instruction further includes waiting indication information;

[0481] The method further includes:

[0482] Based on the second type of indication information of the waiting task completion instruction, controlling the NPU to perform a waiting operation;

[0483] Control the NPU to wait for the data transmission task to be completed based on the waiting indication information;

[0484] Controlling the NPU to wait for the data processing task to be completed based on the waiting indication information;

[0485] Based on the waiting indication information, the NPU is controlled to wait for the completion of the data transmission task and the completion of the data processing task.

[0486] In some embodiments, the instruction set further includes a no-operation instruction; the no-operation instruction further includes number information; the number information indicates a target number of no-operations;

[0487] The method further includes:

[0488] Based on the second type of indication information of the no-operation instruction, the NPU is controlled to execute a target number of no-operations.

[0489] In some embodiments, the instruction set further includes a jump instruction; the jump instruction further includes jump address information;

[0490] The method further includes:

[0491] Based on the second type of indication information of the jump instruction, interrupt the acquisition of all the unacquired instructions in the initial instruction queue; acquire each preset instruction in the preset instruction sequence; the initial instruction queue is part of the instruction set; the preset instruction sequence is part of the instruction set;

[0492] The address of the fifth general register is determined based on the jump address information; the fifth general register is used to store a base address; the base address is used to store the preset instruction sequence; the fifth general register is set in the control module.

[0493] In some embodiments, the instruction set further includes a skip instruction; the skip instruction further includes validation information and skip quantity information;

[0494] The method further includes:

[0495] Determining that a skip operation needs to be performed based on the validation information;

[0496] Based on the second type of indication information of the skip instruction, control the NPU to skip the skipped number of the unparsed instructions; parse the target instruction in the initial instruction queue; the target instruction is the next unparsed instruction of the skipped number of the unparsed instructions; or

[0497] Determining, based on the validation information, that the NPU does not need to perform a skip operation;

[0498] Directly parse the next unparsed instruction in the initial instruction queue.

[0499] In some embodiments, the instruction set further includes a reset instruction;

[0500] The method further includes:

[0501] Based on the second type of indication information in the reset instruction, the NPU is controlled to perform a reset operation.

[0502] In some embodiments, the instruction set further includes an addition instruction; the addition instruction further includes operation information, an immediate value, a first initial value, write address information, a second initial value, and read address information;

[0503] The method further includes:

[0504] determining an addition type based on the operation information;

[0505] The method further includes:

[0506] Determining an initial value of a sixth general register based on the first initial value; the sixth general register is set in the control module;

[0507] determining an address of the sixth general register based on the write address information;

[0508] Determining an initial value of a seventh general register based on the second initial value; the seventh general register is set in the control module;

[0509] determining an address of the seventh general register based on the read address information;

[0510] Based on the second type of indication information of the addition instruction, the NPU is controlled to perform the addition operation.

[0511] In some embodiments, the method further comprises:

[0512] When the operation information indicates the first addition type, based on the second type indication information of the addition instruction and the operation information, control the NPU to write the immediate number into the sixth general register;

[0513] or when the operation information indicates a second addition type, based on the second type indication information of the addition instruction and the operation information, controlling the NPU to write the immediate value and the first initial value into the sixth general register;

[0514] or when the operation information indicates a third addition type, based on the second type indication information of the addition instruction and the operation information, controlling the NPU to write the immediate value and the second initial value into the sixth general register;

[0515] Or when the operation information indicates a fourth addition type, based on the second type indication information of the addition instruction and the operation information, the NPU is controlled to write the first initial value and the second initial value into the sixth general register.

[0516] In some embodiments, each of the instructions also includes a free location.

[0517] In addition, the instruction set-based control device and instruction set-based control method embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the NPU embodiments, which will not be repeated here.

[0518] In the embodiment of the present application, in each instruction in the instruction set, the same information is stored in some of the same bits, so the control module can use the same read logic to read and the same parsing logic to parse the same position, thereby simplifying the reading logic and parsing logic of the instruction, thereby reducing the number of registers used to store the reading logic and parsing logic, and reducing the hardware area. In addition, the same position can be read using the same read logic and the same parsing logic, which also improves the parsing efficiency of the instruction, so that each instruction can be parsed within one clock cycle.

[0519] An embodiment of the present application further provides a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above method when executing the computer program.

[0520] Taking computer equipment as the terminal as an example, Fig.16 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present application, see Fig.16The terminal 1600 may be a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 player (Moving Picture Experts Group Audio Layer IV), a laptop computer, or a desktop computer. The terminal 1600 may also be called a user device, a portable terminal, a laptop terminal, a desktop terminal, or other names.

[0521] Typically, the terminal 1600 includes a processor 1601 and a memory 1602 .

[0522] The processor 1601 may include one or more processing cores, such as a 4-core processor, a 5-core processor, etc. The processor 1601 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 1601 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 1601 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1601 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0523] The memory 1602 may include one or more computer-readable storage media, which may be non-transitory. The memory 1602 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1602 is used to store at least one program code, which is used to be executed by the processor 1601 to implement the process of terminal execution in the method for mixed-precision floating-point multiplication and accumulation operations provided in the method embodiment of the present application.

[0524] In some embodiments, the terminal 1600 may further optionally include: a peripheral device interface 1603 and at least one peripheral device. The processor 1601, the memory 1602 and the peripheral device interface 1603 may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface 1603 via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a display screen 1604, a camera assembly 1605, an audio circuit 1606 and a power supply 1607.

[0525] The peripheral device interface 1603 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 1601 and the memory 1602. In some embodiments, the processor 1601, the memory 1602, and the peripheral device interface 1603 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1601, the memory 1602, and the peripheral device interface 1603 may be implemented on a separate chip or circuit board, which is not limited in the embodiments of the present application.

[0526] The display screen 1604 is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 1604 is a touch display screen, the display screen 1604 also has the ability to collect touch signals on the surface or above the surface of the display screen 1604. The touch signal can be input to the processor 1601 as a control signal for processing. At this time, the display screen 1604 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 1604 can be one, which is set on the front panel of the terminal 1600; in other embodiments, the display screen 1604 can be at least two, which are respectively set on different surfaces of the terminal 1600 or are folded; in other embodiments, the display screen 1604 can be a flexible display screen, which is set on the curved surface or folded surface of the terminal 1600. Even, the display screen 1604 can also be set as a non-rectangular irregular figure, that is, a special-shaped screen. The display screen 1604 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0527] The camera assembly 1605 is used to capture images or videos. In some embodiments, the camera assembly 1605 includes a front camera and a rear camera. Typically, the front camera is disposed on the front panel of the terminal, and the rear camera is disposed on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize the panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 1605 may also include a flash. The flash may be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0528] The audio circuit 1606 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals and input them into the processor 1601 for processing. For the purpose of stereo acquisition or noise reduction, there may be multiple microphones, which are respectively arranged at different parts of the terminal 1600. The microphone may also be an array microphone or an omnidirectional acquisition microphone. The speaker is used to convert the electrical signal from the processor 1601 into sound waves. The speaker may be a traditional film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 1606 may also include a headphone jack.

[0529] The power supply 1607 is used to power various components in the terminal 1600. The power supply 1607 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 1607 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0530] Those skilled in the art will understand that Fig.16 The structure shown in the figure does not constitute a limitation on the terminal 1600, and the terminal 1600 may include more or less components than those shown in the figure, or combine some components, or adopt a different component arrangement.

[0531] Take the computer device as a server as an example. Fig.17This is a structural diagram of a server provided in an embodiment of the present application. The server 1700 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 1701 and one or more memories 1702, wherein the one or more memories 1702 store at least one computer program, and the at least one computer program is loaded and executed by the one or more processors 1701 to implement the above-mentioned instruction set-based control method. Of course, the server 1700 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The server 1700 may also include other components for implementing device functions, which will not be repeated here.

[0532] The embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the above-mentioned method for generating an image processing model. Optionally, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0533] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0534] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An NPU, characterized in that: include: Control module; The control module is used to obtain and parse an instruction set or an instruction, wherein the instruction set includes a plurality of the instructions, each of the instructions has the same number of bits, and the first position is the same as the second position; the first position is the position of the first type of indication information included in the instruction in the instruction, and the second position is the position of the second type of indication information included in the instruction in the instruction; The control module is further used to determine the running time and running time of the tth task being executed by the NPU based on the first type of indication information; t is an integer greater than or equal to 1; each of the tasks corresponds to at least one of the instructions; the first type of indication information includes dot information and task update information; The control module is further used to control the NPU not to print the running time based on the dot information; the running time is the start time or end time of the task; the running time is obtained based on the start time and end time of the task; The control module is further used to determine the operation type corresponding to the instruction based on the second type of indication information, and control the NPU to perform the operation corresponding to the operation type; the operation type at least includes a configuration operation and a processing operation.

2. The NPU according to claim 1, characterized in that The control module is further used to control the NPU to print the start time or the end time based on the dot information; The control module is also used to determine that the NPU is executing the t+1th task based on the task update information; control the NPU to print the start time or the end time of the t+1th task based on the dot information; or determine that the NPU is executing the tth task based on the task update information; and control the NPU to print the start time or the end time of the tth task based on the dot information.

3. The NPU according to claim 2, characterized in that The first type of indication information also includes verification information; the verification information includes an initial verification code; The control module is further used to determine whether an exception occurs in the corresponding instruction based on the verification information; the exception indicates that the NPU times out and generates an interrupt or an error occurs in the operation of the NPU; Wherein, when the initial verification code is consistent with the actual verification code, the control module determines that the corresponding instruction is normal; the actual verification code is generated when the NPU parses the corresponding instruction; Or when the initial verification code is inconsistent with the actual verification code, the control module determines that an abnormality occurs in the corresponding instruction.

4. The NPU according to claim 1, characterized in that: The instruction set includes configuration instructions; the configuration instructions also include first address information and first data information; The control module is further used to determine the address of the first function register based on the first address information; The control module is further used to configure the first data information to the first function register based on the second type of indication information of the configuration instruction; the first function register is set in the NPU.

5. The NPU according to claim 1, characterized in that: The instruction set further includes a load instruction; the load instruction further includes second address information, quantity information and second data information; The control module is further used to determine the address of a first general register in the control module to be rewritten based on the second address information; The control module is further configured to determine the quantity of the first general registers to be rewritten based on the quantity information; The control module is further used to determine the address of the loaded data in the memory based on the second data information; The control module is further configured to load the load data into the first general register based on the second type of indication information of the load instruction; the address of the load data includes an initial address and an offset address.

6. The NPU according to claim 1, characterized in that: The instruction set further includes a move instruction; the move instruction further includes third address information and fourth address information; The control module is further used to determine the address of a second general register in the control module based on the third address information; The control module is further used to determine the address of the second function register in the NPU based on the fourth address information; The control module is further used to control the NPU to move the data in the second general register to the second function register based on the second type of indication information of the move instruction.

7. The NPU according to claim 1, characterized in that: The NPU further includes a scheduling module; the scheduling module is electrically connected to the control module; the instruction set further includes an interrupt instruction; the interrupt instruction further includes a third type of indication information; the third type of indication information is used to indicate the operation type; The control module is further used to control the scheduling module to generate an interrupt based on the second type of indication information and the third type of indication information of the interrupt instruction.

8. The NPU according to claim 7, characterized in that: The NPU further includes a data processing module and a data transmission module; the control module is electrically connected to the data processing module and the data transmission module respectively; the scheduling module is electrically connected to the data processing module and the data transmission module respectively; The instruction set further includes an update instruction and a wait instruction; the update instruction and the wait instruction further include the third type of indication information; The control module is further used to control the data processing module or the data transmission module to wait for the third function register to be updated based on the second type of indication information and the third type of indication information of the waiting instruction; The control module is further used to control the data processing module or the data transmission module to update the third function register based on the second type of indication information and the third type of indication information of the update instruction; The scheduling module is used to notify the waiting data processing module or data transmission module to end the waiting operation after detecting that the third function register is updated to a corresponding value; The control module is further used to control the data transmission module or the data processing module to update the third function register; the third function register is set in the scheduling module.

9. The NPU according to claim 8, characterized in that: The update instruction also includes first determination information, first absolute address information, first relative address information and an initial update value; The control module is further used to determine that first initial data needs to be acquired based on the first determination information; the first initial data is part of data of a third general register; and the third general register is set in the control module; The control module is further configured to determine the address of the third general register based on the first absolute address information; The control module is further used to determine the address of the third function register based on the first relative address information; The control module is further used to control the data processing module or the data transmission module to write the initial update value and the first initial data into the third function register based on the second type of indication information and the third type of indication information of the update instruction.

10. The NPU according to claim 9, characterized in that: The control module is further configured to determine, based on the first determination information, that it is not necessary to obtain the first initial data; The control module is further used to determine the address of the third function register based on the first relative address information; The control module is further used to control the data processing module or the data transmission module to write the initial update value into the third function register based on the second type of indication information and the third type of indication information of the update instruction.

11. The NPU according to claim 10, characterized in that: The waiting instruction also includes second determination information, second absolute address information, second relative address information and an initial waiting value; The control module is further used to determine that second initial data needs to be acquired based on the second determination information; the second initial data is part of data of a fourth general register; the fourth general register is set in the control module; The control module is further configured to determine the address of the fourth general register based on the second absolute address information; The control module is further used to determine the address of a fourth function register based on the second relative address information; The control module is further used to control the data processing module or the data transmission module to write the initial waiting value and the second initial data into the fourth function register; the fourth function register is set in the scheduling module.

12. The NPU according to claim 11, characterized in that: The control module is further configured to determine, based on the second determination information, that it is not necessary to obtain the second initial data; The control module is further used to determine the address of the fourth function register based on the second relative address information; The control module is further used to control the data processing module or the data transmission module to write the initial waiting value into the fourth function register.

13. The NPU according to claim 12, characterized in that: The first address position and the second address position are the same; the first address position is the position of the first absolute address information in the update instruction; the second address position is the position of the second absolute address information in the wait instruction; The first indication position, the second indication position and the third indication position are the same; the first indication position is the position of the third type of indication information in the interrupt instruction; the second indication position is the position of the third type of indication information in the update instruction; the third indication position is the position of the third type of indication information in the wait instruction.

14. The NPU according to claim 1, characterized in that: The instruction set also includes a waiting task completion instruction; the waiting task completion instruction also includes waiting indication information; The control module is further used to control the NPU to perform a waiting operation based on the second type of indication information of the waiting task completion instruction; The control module is further used to control the NPU to wait for the data transmission task to be completed based on the waiting indication information; or the control module is further used to control the NPU to wait for the data processing task to be completed based on the waiting indication information; Or the control module is also used to control the NPU to wait for the data transmission task and the data processing task to be completed based on the waiting indication information.

15. The NPU according to claim 1, characterized in that: The instruction set further includes a no-operation instruction; the no-operation instruction further includes number information; the number information indicates a target number of no-operations; The control module is further used to control the NPU to execute a target number of no-operations based on the second type of indication information of the no-operation instruction.

16. The NPU according to claim 1, characterized in that: The instruction set also includes a jump instruction; the jump instruction also includes jump address information; The control module is further used to interrupt the acquisition of all the unacquired instructions in the initial instruction queue based on the second type indication information of the jump instruction; acquire each preset instruction in the preset instruction sequence; the initial instruction queue is part of the instruction set; the preset instruction sequence is part of the instruction set; The control module is further used to determine the address of the fifth general register based on the jump address information; the fifth general register is used to store a base address; the base address is used to store the preset instruction sequence; the fifth general register is set in the control module.

17. The NPU according to claim 16, characterized in that: The instruction set also includes a skip instruction; the skip instruction also includes effectiveness information and skip quantity information; The control module is further used to determine that a skip operation needs to be performed based on the validation information; The control module is further used to control the NPU to skip the skipped number of unparsed instructions based on the second type of indication information of the skipped instruction; parse the target instruction in the initial instruction queue; the target instruction is the next unparsed instruction of the skipped number of unparsed instructions; or The control module is further used to determine that the NPU does not need to perform a skip operation based on the validation information; The control module is further used to directly parse the next unparsed instruction in the initial instruction queue.

18. The NPU according to claim 1, wherein: The instruction set also includes a reset instruction; The control module is further used to control the NPU to perform a reset operation based on the second type of indication information in the reset instruction.

19. The NPU according to claim 1, characterized in that: The instruction set also includes an addition instruction; the addition instruction also includes operation information, an immediate value, a first initial value, write address information, a second initial value and read address information; The control module is further used to determine the addition type based on the operation information; The control module is further configured to determine an initial value of a sixth general register based on the first initial value; the sixth general register is set in the control module; The control module is further used to determine the address of the sixth general register based on the write address information; The control module is further configured to determine an initial value of a seventh general register based on the second initial value; the seventh general register is set in the control module; The control module is further used to determine the address of the seventh general register based on the read address information; The control module is further used to control the NPU to perform an addition operation based on the second type of indication information of the addition instruction.

20. The NPU according to claim 19, characterized in that The control module is further configured to control the NPU to write the immediate value into the sixth general register based on the second type of indication information of the addition instruction and the operation information when the operation information indicates a first addition type; or the control module is further configured to, when the operation information indicates a second addition type, control the NPU to write the immediate value and the first initial value into the sixth general register based on the second type indication information of the addition instruction and the operation information; or the control module is further configured to, when the operation information indicates a third addition type, control the NPU to write the immediate value and the second initial value into the sixth general register based on the second type indication information of the addition instruction and the operation information; Or the control module is also used to control the NPU to write the first initial value and the second initial value into the sixth general register based on the second type of indication information of the addition instruction and the operation information when the operation information indicates a fourth addition type.

21. The NPU according to claim 1, characterized in that Each of the instructions also includes a free position.

22. A control method based on an instruction set, characterized in that: include: Acquire and parse an instruction set or an instruction, wherein the instruction set includes a plurality of the instructions, each of the instructions has the same number of bits, and the first position is the same as the second position; the first position is the position of the first type of indication information included in the instruction in the instruction, and the second position is the position of the second type of indication information included in the instruction in the instruction; Determine the running time and running time of the tth task being executed by the NPU based on the first type of indication information; t is an integer greater than or equal to 1; each of the tasks corresponds to at least one of the instructions; the first type of indication information includes dot information and task update information; Based on the dot information, control the NPU not to print the running time; the running time is the start time or end time of the task; The running time is obtained based on the start time and the end time of the task; Based on the second type of indication information, determine the operation type corresponding to the instruction, and control the NPU to perform the operation corresponding to the operation type; the operation type at least includes a configuration operation and a processing operation.

23. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the instruction set-based control method as described in claim 22.

24. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one program, and the at least one program is loaded and executed by the processor to implement the instruction set-based control method as described in claim 22.

Citation Information

Patent Citations

Optimizing method and apparatus for implementing instruction parallel execution
CN101436122A
Embedded processor of storage and calculation integrated chip, instruction set and data processing method
CN110990060A

Patent Information

AI Technical Summary

Abstract

Description

Patent Citations

Optimizing method and apparatus for implementing instruction parallel execution

Embedded processor of storage and calculation integrated chip, instruction set and data processing method