Composite layer and preparation method thereof, epitaxial wafer, and light-emitting diode

Abstract

The present invention provides a composite layer and a preparation method thereof, an epitaxial wafer, and a light-emitting diode, relating to the field of semiconductor technology. The composite layer comprises a transition layer and multiple superlattice structure layers stacked on the transition layer. The superlattice structure layer comprises barrier layers and well layers that are periodically and alternately grown. The transition layer and barrier layers are both Si-doped nitride layers, while the well layers are undoped nitride layers. The thickness ratio of the transition layer to the barrier layer is greater than 10:1, and the Si doping concentration ratio of the transition layer to the barrier layer is greater than 3:1. The Si doping concentration of the barrier layers decreases layer by layer, and the bandgap width of the well layers decreases layer by layer, along the direction from one end near the transition layer to the other end. The present invention improves luminous efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a composite layer and a preparation method thereof, an epitaxial wafer, and a light-emitting diode. Background Art

[0002] The LED epitaxial wafer structure includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer. Due to the lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, a large amount of stress accumulation is generated during the epitaxial wafer growth process, and the quality of the epitaxially grown crystal is poor, which affects the antistatic ability and luminous efficiency of the prepared LED device. Summary of the Invention

[0003] Based on this, the purpose of the present invention is to provide a composite layer and its preparation method, epitaxial wafer, and light-emitting diode, aiming to solve the problem of poor quality of epitaxial growth crystals in the prior art, which affects the antistatic ability and luminous efficiency of the prepared LED devices.

[0004] The embodiment of the present invention is implemented as follows:

[0005] On the one hand, an embodiment of the present invention provides a composite layer, comprising a transition layer and a plurality of superlattice structure layers stacked on the transition layer, wherein the superlattice structure layer comprises barrier layers and well layers that are periodically and alternately grown;

[0006] Among them, the transition layer and the barrier layer are both Si-doped nitride layers, the well layer is an undoped nitride layer, the thickness ratio of the transition layer to the barrier layer is greater than 10:1, and the Si doping concentration ratio of the transition layer to the barrier layer is greater than 3:1. Along the direction from one end close to the transition layer to the other end, the Si doping concentration of the barrier layer in different superlattice structure layers decreases layer by layer, and the band gap width of the well layer decreases layer by layer.

[0007] In addition, the composite layer proposed above may also have at least the following additional technical features:

[0008] Furthermore, the thickness of the transition layer is 150 nm to 250 nm, the thickness of the barrier layer is 5 nm to 20 nm, and the thickness of the well layer is 2 nm to 10 nm.

[0009] Furthermore, the Si doping concentration of the transition layer and the barrier layer is 1×10 17 atoms / cm 3 -1×10 19 atoms / cm 3 .

[0010] Furthermore, the band gap width of the barrier layer is 3.39ev-5.0ev, and the band gap width of the well layer is 2.25ev-3.39ev.

[0011] Furthermore, the number of the superlattice structure layers is 2-5, and the growth period of the superlattice structure layers is 3-8.

[0012] On the other hand, an embodiment of the present invention provides a method for preparing a composite layer, for preparing any of the composite layers described above, the method comprising:

[0013] Growth transition layer;

[0014] Periodically and alternately growing barrier layers and well layers on the transition layer to grow a plurality of superlattice structure layers on the transition layer;

[0015] Among them, the transition layer and the barrier layer are both Si-doped nitride layers, the well layer is an undoped nitride layer, the thickness ratio of the transition layer to the barrier layer is greater than 10:1, and the Si doping concentration ratio of the transition layer to the barrier layer is greater than 3:1. Along the direction from one end close to the transition layer to the other end, the Si doping concentration of the barrier layer in different superlattice structure layers decreases layer by layer, and the band gap width of the well layer decreases layer by layer.

[0016] Furthermore, in the method for preparing the composite layer, the growth temperature of the transition layer is 850° C.-950° C., and the growth pressure of the transition layer is 150 Torr-250 Torr.

[0017] Furthermore, in the method for preparing the composite layer, the growth temperature of the superlattice structure layer is 850° C.-950° C., and the growth pressure of the transition layer is 150 Torr-250 Torr.

[0018] In another aspect, an embodiment of the present invention provides an epitaxial wafer, comprising:

[0019] A substrate, a buffer layer, an undoped gallium nitride layer, an N-type gallium nitride layer, a composite layer, an active layer, and a P-type gallium nitride layer sequentially stacked on the substrate;

[0020] Wherein, the composite layer is the composite layer mentioned above.

[0021] In another aspect, an embodiment of the present invention provides a light emitting diode, comprising the above-mentioned epitaxial wafer.

[0022] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0023] The transition layer in the composite layer has a thickness much greater than that of the barrier layer in the superlattice structure layer, which can fully release the stress accumulated during epitaxial growth and improve the probability of carrier recombination; the transition layer in the composite layer has a Si doping concentration much greater than that of the barrier layer in the superlattice structure layer. Along the direction from one end close to the transition layer to the other end, the Si doping concentration of the barrier layer in different superlattice structure layers decreases layer by layer, and the band gap width of the well layer decreases layer by layer. On the one hand, it can improve the current diffusion capacity of the LED chip, prevent a large amount of charge from being instantly loaded on the two poles of the chip during electrostatic discharge, and prevent the charge from generating local large current and causing the chip to be broken down, thereby improving the anti-static ability of the LED chip and reducing the thyristor effect caused by the low Si doping concentration. On the other hand, it can reduce the migration rate of electrons, reduce the number of electrons overflowing from the active layer, and reduce the probability of non-radiative recombination in the LED structure; ultimately improving the luminous efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the structure of an epitaxial wafer in one embodiment of the present invention;

[0025] Figure 2 A schematic diagram of the structure of the composite layer in the epitaxial wafer according to one embodiment of the present invention

[0026] Figure 3 Flowchart of a method for preparing a composite layer according to an embodiment of the present invention;

[0027] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0028] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate several embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0029] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0031] The embodiments of the present invention address the problem that the quality of existing epitaxially grown crystals is poor, which affects the antistatic ability and luminous efficiency of the prepared LED devices. A composite layer and its preparation method, an epitaxial wafer, and a light-emitting diode are proposed, wherein:

[0032] See also Figure 1 , which is a schematic structural diagram of an epitaxial wafer proposed in one embodiment of the present invention, and includes:

[0033] A substrate 1, a buffer layer 2, a non-doped gallium nitride layer 3, an N-type gallium nitride layer 4, a composite layer 5, an active layer 6, and a P-type gallium nitride layer 7 sequentially stacked on the substrate 1.

[0034] For details, please refer to Figure 2 The composite layer 5 includes a transition layer 51 and a plurality of superlattice structure layers 52 stacked on the transition layer 51 . The superlattice structure layer 52 includes a barrier layer 521 and a well layer 522 that are periodically and alternately grown.

[0035] Specifically, the transition layer 51 and the barrier layer 521 are both Si-doped nitride layers, such as Si-doped GaN layers, and the well layer 522 is a non-doped nitride layer, such as an InGaN layer. The thickness ratio of the transition layer 51 to the barrier layer 521 is greater than 10:1. The thickness of the transition layer 51 in the composite layer 5 is much greater than that of the barrier layer 521 in the superlattice structure layer 52, which can fully release the stress accumulated in the epitaxial growth and improve the carrier recombination probability. The Si doping concentration ratio of the transition layer 51 to the barrier layer 521 is greater than 3:1, and in the direction from one end close to the transition layer 51 to the other end, different superlattice structures are formed. The Si doping concentration of the barrier layer 521 in the lattice structure layer 52 decreases layer by layer, and the band gap width of the well layer 522 decreases layer by layer. This special setting can, on the one hand, improve the current diffusion capability of the LED chip, prevent a large amount of charge from being instantly loaded on the two poles of the chip during electrostatic discharge, and prevent the charge from generating a local large current and causing the chip to be broken down, thereby improving the anti-static capability of the LED chip and reducing the thyristor effect caused by the low Si doping concentration. On the other hand, it can reduce the migration rate of electrons, reduce the number of electrons overflowing from the active layer 6, and reduce the probability of non-radiative recombination in the LED structure, ultimately improving the luminous efficiency.

[0036] Furthermore, the thickness of the transition layer 51 is 150nm-250nm, the thickness of the barrier layer 521 is 5nm-20nm, and the thickness of the well layer 522 is 2nm-10nm, ensuring that the thickness of the transition layer 51 and the barrier layer 521 are in a reasonable ratio. Among them, if the thickness of the transition layer 51 is too thin, it will not be conducive to releasing the stress accumulated during epitaxial growth and reduce the luminous efficiency. If the transition layer 51 is too thick, its interface will be too rough, which will affect the quality of the subsequent epitaxial layer growth crystal and affect the device performance.

[0037] Specifically, the Si doping concentration of the transition layer 51 and the barrier layer 521 is 1×10 17 atoms / cm 3 -1×10 19 atoms / cm 3 ; The band gap width of the barrier layer 521 of the Si-doped nitride layer can be 3.39ev-5.0ev, and the band gap width of the well layer 522 of the undoped nitride layer can be 2.25ev-3.39ev. When the specific value of the Si doping concentration is determined, within this value range, the value of the transition layer 51 is much larger than the Si doping concentration of the barrier layer 521 in the superlattice structure layer 52, thereby improving the current diffusion capacity of the LED chip and preventing a large amount of charge from being instantly loaded on the two poles of the chip during electrostatic discharge, and the charge generating a local large current and causing the chip to be broken down; the number of superlattice structure layers 52 is 2-5, and the growth period of the superlattice structure layer 52 is 3-8, wherein the number of superlattice structure layers can be set to 2~5, and each superlattice structure layer can be obtained by alternating growth of the barrier layer 521 and the well layer 522 with a growth period of 3-8.

[0038] For example, the structures of the other layers of the epitaxial wafer except the composite layer 5 in the embodiment of the present invention correspond to the following:

[0039] The substrate 1 includes but is not limited to a sapphire substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a gallium oxide substrate. As an example of the present invention, a sapphire substrate is used as a growth substrate for the epitaxial layer of this example.

[0040] The buffer layer 2 may be any one of an AlN layer, an AlGaN layer, and a GaN layer, or a combination thereof. In this embodiment, the buffer layer 2 is an AlGaN layer and a GaN layer deposited sequentially. The specific deposition process is as follows: the temperature of the reaction chamber is controlled at 750°C-820°C, the pressure is controlled at 100 torr-200 torr, NH3 is used as the N (nitrogen) source, TMGa is used as the Ga (gallium) source, and TMAl is used as the Al (aluminum) source to grow an AlGaN layer, and the thickness of the deposited AlGaN layer is controlled to be 0.5 nm-3 nm. Then, a GaN layer is grown, and the thickness of the deposited GaN layer is controlled to be 5 nm-25 nm.

[0041] The specific deposition process of the undoped gallium nitride layer is as follows: the temperature of the reaction chamber is controlled at 1000°C-1250°C, the pressure is controlled at 100 torr-300 torr, NH3 is used as the N (nitrogen) source, TMGa is used as the Ga (gallium) source, and an undoped GaN layer is grown. The thickness of the deposited undoped GaN layer is controlled to be 1 μm-1.7 μm. In some optional embodiments of the present invention, the undoped gallium nitride layer may also be an undoped AlGaN layer or a combination of an undoped AlGaN layer and an undoped gallium nitride layer.

[0042] The specific deposition process of the N-type GaN layer is as follows: the reaction chamber temperature is lowered to 1000-1200°C, the pressure is controlled at 100 torr-250 torr, NH3 is used as the N (nitrogen) source, TMGa is used as the Ga (gallium) source, SiH4 is used as the N-type dopant, and the doping concentration of Si (silicon) can be 5×10 17 atoms / cm 3 -1×10 19 atoms / cm 3 , and controlling the thickness of the deposited N-type GaN layer to be 1.0 μm-3 μm. In some optional embodiments of the present invention, the N-type gallium nitride layer may be an N-type AlGaN layer or a combination of an N-type AlGaN layer and an N-type gallium nitride layer;

[0043] Wherein, the active layer 6 is formed by the periodic alternating growth of quantum barrier layers and quantum well layers, and the number of growth cycles is ≥8. In one embodiment of the present invention, the number of cycles can be 10, and the active layer 6 is obtained by alternating the growth of quantum barrier layers and quantum well layers 10 times. Furthermore, the specific deposition process is as follows: when growing the quantum well layer, the temperature of the reaction chamber is controlled to be 760°C-800°C, and the pressure is controlled to be 150torr-250torr, wherein the N (nitrogen) source can be NH3, the Ga (gallium) source can be TEGa, and the In (indium) source can be TMIn, and the thickness of the deposited InGaN quantum well layer is controlled to be 2nm-4nm. When growing the quantum barrier layer, the temperature of the reaction chamber is controlled to be 860°C-900°C, and the pressure is controlled to be 150torr-250torr, wherein the N (nitrogen) source can be NH3, the Ga (gallium) source can be TEGa, and the thickness of the deposited GaN quantum barrier layer is controlled to be 8nm-12nm;

[0044] The P-type gallium nitride layer 7 can be a P-type GaN layer. The specific deposition process is as follows: the reaction chamber temperature is 980°C-1050°C, NH3 is used as the N (nitrogen) source, TEGa is used as the Ga (gallium) source, and CP2Mg is used as the P-type dopant. The thickness of the deposited P-type GaN layer is controlled to be 15nm-20nm in the H2 atmosphere, wherein the Mg doping concentration is 1×10 18 atoms / cm 3 -5×1021 atoms / cm 3 .

[0045] See also Figure 3 On the other hand, an embodiment of the present invention provides a method for preparing a composite layer, which is used to prepare the above-mentioned composite layer. The method includes steps S10 to S12.

[0046] Step S10: growing a transition layer.

[0047] The transition layer is a Si-doped GaN layer. The deposition process is as follows: the reaction chamber temperature is controlled at 850°C-950°C, the pressure is controlled at 150 torr-250 torr, NH3 is used as the N (nitrogen) source, TMGa is used as the Ga (gallium) source, and SiH4 is used as the N-type dopant. The thickness of the deposited Si-doped GaN layer is controlled to be 150nm-250nm, and the Si doping concentration is 1×10 17 atoms / cm 3 -1×10 19 atoms / cm 3 .

[0048] Step S11 : periodically and alternately growing barrier layers and well layers on the transition layer to grow a plurality of superlattice structure layers on the transition layer.

[0049] Among them, the alternately grown barrier layer and well layer can generate a superlattice structure layer. The corresponding superlattice structure layer can be generated by controlling the alternating growth cycle, and the specific growth parameters can be controlled to generate multiple superlattice structure layers with the same structure but different growth parameters. Specifically, the barrier layer deposition process in the superlattice structure layer is to control the reaction chamber temperature at 850℃-950℃, the pressure at 150torr-250 torr, NH3 as the N (nitrogen) source, TMGa as the Ga (gallium) source, SiH4 as the N-type dopant, and control the thickness of the deposited barrier layer to be 150nm-250nm, and the Si doping concentration to be 1×10 17 atoms / cm 3 -1×10 19 atoms / cm 3 , the band gap is 3.39ev-5.0ev.

[0050] Specifically, the deposition process of the well layer in the superlattice structure layer is to control the reaction chamber temperature at 850℃-950℃, the pressure at 150torr-250 torr, NH3 as the N (nitrogen) source, TEGa as the Ga (gallium) source, and TMIn as the In (indium) source, and control the thickness of the deposited well layer to be 2nm-10nm and the band gap width to be 2.25ev-3.39ev.

[0051] On the other hand, a light emitting diode provided in an embodiment of the present invention includes the above-mentioned epitaxial wafer.

[0052] In summary, the embodiment of the present invention provides a composite layer, including a transition layer and a plurality of superlattice structure layers stacked on the transition layer, wherein the superlattice structure layer includes a barrier layer and a well layer that are periodically and alternately grown; wherein the transition layer and the barrier layer are both Si-doped nitride layers, the well layer is an undoped nitride layer, the thickness ratio of the transition layer to the barrier layer is greater than 10:1, the Si doping concentration ratio of the transition layer to the barrier layer is greater than 3:1, and along the direction from one end close to the transition layer to the other end, the Si doping concentration of the barrier layer in different superlattice structure layers decreases layer by layer, and the band gap width of the well layer decreases layer by layer. By utilizing the fact that the thickness of the transition layer in the composite layer is much greater than that of the barrier layer in the superlattice structure layer, the stress accumulated in the epitaxial growth can be fully released, thereby improving the carrier recombination mechanism. rate; the transition layer in the composite layer has a Si doping concentration much greater than that of the barrier layer in the superlattice structure layer. Along the direction from one end close to the transition layer to the other end, the Si doping concentration of the barrier layer in different superlattice structure layers decreases layer by layer, and the band gap width of the well layer decreases layer by layer. On the one hand, it can improve the current diffusion capacity of the LED chip, prevent a large amount of charge from being instantly loaded on the two poles of the chip during electrostatic discharge, and prevent the chip from being broken down due to the charge generating a local large current, thereby improving the anti-static ability of the LED chip and reducing the thyristor effect caused by the low Si doping concentration. On the other hand, it can reduce the migration rate of electrons, reduce the number of electrons overflowing from the active layer, and reduce the probability of non-radiative recombination in the LED structure, ultimately improving the luminous efficiency.

[0053] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the relevant embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0054] Example 1

[0055] A first embodiment of the present invention provides a method for preparing an epitaxial wafer, comprising:

[0056] A sapphire substrate is provided, and an AlGaN layer with a thickness of 1 nm, a GaN layer with a thickness of 10 nm, a non-doped AlGaN layer with a thickness of 1.2 μm, and an N-type GaN layer with a thickness of 2 μm are grown on the sapphire substrate in sequence; then a composite layer, an active layer, a GaN layer with a thickness of 18 nm and a Mg doping concentration of 1×10 20 atoms / cm 3 P-type GaN layer;

[0057] The active layer is composed of 10 cycles of alternating GaN barrier layers with a thickness of 10 nm and InGaN well layers with a thickness of 3 nm.

[0058] The composite layer is composed of a transition layer and a plurality of superlattice structure layers deposited thereon. Specifically, the transition layer has a thickness of 200 nm and a Si doping concentration of 8×10 18 atoms / cm 3 The GaN layer has two superlattice structure layers, the first superlattice structure layer has a thickness of 10 nm, and the Si doping concentration is 2×10 18 atoms / cm 3 The GaN barrier layer and the InGaN well layer with a thickness of 5nm and a band gap of 3.2ev are alternately grown for 4 periods. The second superlattice structure layer is 8nm thick and has a Si doping concentration of 4×10 17 atoms / cm 3 The GaN barrier layer with a thickness of 4nm and a bandgap width of 3.0eV is alternately grown in 6 cycles.

[0059] Among them, the ratio of the thickness of the transition layer to the thickness of the barrier layer in the first superlattice structure layer is 20:1, the ratio of the thickness of the transition layer to the thickness of the barrier layer in the second superlattice structure layer is 25:1, the ratio of the Si doping concentration of the transition layer to the Si doping concentration of the barrier layer in the first superlattice structure layer is 4:1, and the ratio of the Si doping concentration of the transition layer to the Si doping concentration of the barrier layer in the second superlattice structure layer is 20:1.

[0060] Comparative Example 1

[0061] The first comparative example of the present invention also proposes a method for preparing an epitaxial wafer. The difference between the method for preparing an epitaxial wafer in this comparative example and the method for preparing an epitaxial wafer in Example 1 is that:

[0062] The ratio of the thickness of the transition layer to the thickness of the barrier layer in the first superlattice structure layer is 1:1.

[0063] Comparative Example 2

[0064] Comparative Example 2 of the present invention also proposes a method for preparing an epitaxial wafer. The difference between the epitaxial wafer preparation method in this comparative example and the epitaxial wafer preparation method in Example 1 is that:

[0065] The ratio of the Si doping concentration of the transition layer to the Si doping concentration of the barrier layer in the first superlattice structure layer is 1:1.

[0066] Comparative Example 3

[0067] Comparative Example 3 of the present invention also proposes a method for preparing an epitaxial wafer. The difference between the epitaxial wafer preparation method in this comparative example and the epitaxial wafer preparation method in Example 1 is that:

[0068] The Si doping concentration of the barrier layer in the first superlattice structure layer is consistent with the Si doping concentration of the barrier layer in the second superlattice structure layer, that is, the Si doping concentration of the barrier layers in different superlattice structure layers is consistent from one end close to the transition layer to the other end.

[0069] Comparative Example 4

[0070] Comparative Example 4 of the present invention also proposes a method for preparing an epitaxial wafer. The difference between the epitaxial wafer preparation method in this comparative example and the epitaxial wafer preparation method in Example 1 is that:

[0071] The bandgap width of the well layer in the first superlattice structure layer is consistent with the bandgap width of the well layer in the second superlattice structure layer, that is, the bandgap widths of the well layers in different superlattice structure layers are consistent along the direction from one end close to the transition layer to the other end.

[0072] Comparative Example 5

[0073] Comparative Example 5 of the present invention also proposes a method for preparing an epitaxial wafer. The difference between the epitaxial wafer preparation method in this comparative example and the epitaxial wafer preparation method in Example 1 is that:

[0074] The composite layer does not include a transition layer, but only includes a plurality of superlattice structure layers.

[0075] Comparative Example 6

[0076] Comparative Example 6 of the present invention also proposes a method for preparing an epitaxial wafer. The difference between the epitaxial wafer preparation method in this comparative example and the epitaxial wafer preparation method in Example 1 is that:

[0077] The composite layer does not include a plurality of superlattice structure layers, but only includes a transition layer.

[0078] Please refer to Table 1 below, which shows the parameters corresponding to the above-mentioned Example 1 and Comparative Examples 1 to 6 of the present invention.

[0079] Table 1

[0080]

[0081] Performance tests were performed on the LED chips prepared with corresponding parameters in Example 1 and Comparative Examples 1 to 6, and the test data are shown in Table 2 below.

[0082] Table 2

[0083]

[0084] Combining Table 1 and Table 2, it can be clearly seen that the transition layer in the composite layer has a thickness much greater than that of the barrier layer in the superlattice structure layer, which can fully release the stress accumulated during epitaxial growth and improve the probability of carrier recombination; the transition layer in the composite layer has a Si doping concentration much greater than that of the barrier layer in the superlattice structure layer. From one end close to the transition layer to the other end, the Si doping concentration of the barrier layer in different superlattice structure layers decreases layer by layer, and the band gap width of the well layer decreases layer by layer. On the one hand, it can improve the current diffusion capacity of the LED chip and prevent a large amount of charge from being instantly loaded on the two poles of the chip during electrostatic discharge, which causes the chip to be broken down by generating a local large current. It improves the anti-static ability of the LED chip and can also reduce the thyristor effect caused by the low Si doping concentration. On the other hand, it can reduce the migration rate of electrons, reduce the number of electrons overflowing from the active layer, and reduce the probability of non-radiative recombination in the LED structure, ultimately improving the luminous efficiency.

[0085] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A composite layer, applied to an epitaxial wafer, comprising a substrate, a buffer layer, an undoped gallium nitride layer, an N-type gallium nitride layer, an active layer, and a P-type gallium nitride layer sequentially stacked on the substrate, characterized in that: The composite layer is arranged between the N-type gallium nitride layer and the active layer, the composite layer includes a transition layer and a plurality of superlattice structure layers stacked on the transition layer, the superlattice structure layer includes a barrier layer and a well layer that are periodically and alternately grown; Among them, the transition layer and the barrier layer are both Si-doped nitride layers, the well layer is an undoped nitride layer, the thickness ratio of the transition layer to the barrier layer is greater than 10:1, and the Si doping concentration ratio of the transition layer to the barrier layer is greater than 3:

1. Along the direction from one end close to the transition layer to the other end, the Si doping concentration of the barrier layer in different superlattice structure layers decreases layer by layer, and the band gap width of the well layer decreases layer by layer.

2. The composite layer according to claim 1, characterized in that The thickness of the transition layer is 150nm-250nm, the thickness of the barrier layer is 5nm-20nm, and the thickness of the well layer is 2nm-10nm.

3. The composite layer according to claim 1, characterized in that The Si doping concentration of the transition layer and the barrier layer is 1×10 17 atoms / cm 3 -1×10 19 atoms / cm 3 .

4. The composite layer according to claim 1, characterized in that The band gap width of the barrier layer is 3.39ev-5.0ev, and the band gap width of the well layer is 2.25ev-3.39ev. 5 . The composite layer according to claim 1 , wherein the number of the superlattice structure layers is 2-5, and the growth period of the superlattice structure layers is 3-8.

6. A method for preparing a composite layer, characterized in that: For preparing the composite layer according to any one of claims 1 to 5, the method comprises: Growth transition layer; Periodically and alternately growing barrier layers and well layers on the transition layer to grow a plurality of superlattice structure layers on the transition layer; Among them, the transition layer and the barrier layer are both Si-doped nitride layers, the well layer is an undoped nitride layer, the thickness ratio of the transition layer to the barrier layer is greater than 10:1, and the Si doping concentration ratio of the transition layer to the barrier layer is greater than 3:

1. Along the direction from one end close to the transition layer to the other end, the Si doping concentration of the barrier layer in different superlattice structure layers decreases layer by layer, and the band gap width of the well layer decreases layer by layer.

7. The method for preparing a composite layer according to claim 6, characterized in that: The growth temperature of the transition layer is 850° C.-950° C., and the growth pressure of the transition layer is 150 torr-250 torr.

8. The method for preparing a composite layer according to claim 6, characterized in that: The growth temperature of the superlattice structure layer is 850° C.-950° C., and the growth pressure of the transition layer is 150 torr-250 torr.

9. A light emitting diode, characterized in that: The epitaxial wafer comprises: A substrate, a buffer layer, an undoped gallium nitride layer, an N-type gallium nitride layer, a composite layer, an active layer, and a P-type gallium nitride layer sequentially stacked on the substrate; Wherein, the composite layer is the composite layer according to any one of claims 1 to 5.

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