Level shift circuit for high-frequency GaN gate driver chips

Abstract

The present invention relates to a level shift circuit suitable for a high-frequency GaN gate driver chip, and belongs to the technical field of power management in integrated circuits. The circuit uses four PMOS tubes to cut off the noise and two NMOS tubes to discharge the charge, by adding an additional path from a floating power rail VDDH to the ground to simulate the influence of noise caused by the sudden change of the floating power rail voltage in the level shift circuit, thereby ensuring a very good anti-noise capability and increasing the stability of the circuit. Therefore, the level shift circuit of the present invention can be used on a higher frequency GaN gate driver chip to ensure the stable operation of the chip.

Description

Technical Field

[0001] The invention belongs to the technical field of power management in integrated circuits and relates to a level shift circuit suitable for a high-frequency GaN gate drive chip. Background Art

[0002] Since the on-off output point voltage of the power tube of the half-bridge topology works in a floating state, the power supply voltage of the high-voltage side drive circuit will also work in a floating state. Generally speaking, an external bootstrap capacitor is often used to obtain the floating power supply of the high-voltage side drive circuit. Since the power supply of the high-voltage side drive circuit is floating, when the floating power supply voltage changes, the LDMOS has a large parasitic capacitance from the drain to the ground, and the potential of the drain cannot closely follow the change of the floating voltage, which will produce a certain voltage drop, thereby forming dV / dt noise. Once the voltage drop reaches the threshold voltage of the subsequent circuit, it is very likely to cause the drive circuit to trigger incorrectly or even burn the circuit. Compared with traditional Si-based devices, the switching frequency of GaN devices is at the MHZ level, the turn-on and turn-off time is extremely fast, and the dv / dt noise generated by the floating power rail is greater, so the level shift circuit required requires higher noise immunity and lower delay.

[0003] Existing technologies achieve extremely high noise immunity by isolating the noise transmission path, such as Figure 1 However, the charge accumulation at the isolation may affect the output of the circuit after the isolation ends, and the isolation device needs to take a long time to return to normal operation to reduce the current of the released charge. Therefore, when the frequency is too high, the time to return to normal operation is short, which will cause unstable signal transmission or even non-reversal. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a level shift circuit suitable for a high-frequency GaN gate driver chip. The circuit structure does not affect the normal signal transmission of the circuit, can effectively block high-frequency, high dv / dt noise, and discharge noise, and ensure output stability.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A level shift circuit suitable for high-frequency GaN gate driver chips adds an additional path from a floating power rail VDDH to the ground to simulate the influence of noise caused by a sudden change in the floating power rail voltage in the level shift circuit. Four PMOS tubes are used to block noise and two NMOS tubes are used to discharge charge, thereby ensuring excellent noise resistance and increasing the stability of the circuit.

[0007] The circuit specifically includes first to eleventh PMOS transistors MP1 to MP11, first to eleventh NMOS transistors MN1 to MN11, first to third resistors R1 to R3, first to third NLDMOS transistors LD1 to LD3, and first to fifth inverters INV1 to INV5;

[0008] The gates of the first NLDMOS transistor LD1 and the second NLDMOS transistor LD2 are respectively connected to the low voltage power supply VDD, and the sources thereof are respectively connected to the drains of the first NMOS transistor MN1 and the second NMOS transistor MN2, and the drains thereof are respectively connected to the drains of the first PMOS transistor MP1 and the sixth PMOS transistor MP6; the gate and source of the third NLDMOS transistor LD3 are grounded, and the drain thereof is connected to the drain of the eleventh PMOS transistor MP11;

[0009] The gates of the first NMOS tube MN1 and the second NMOS tube MN2 are respectively connected to the output of the low-voltage narrow pulse signal, the sources thereof are grounded, and the drains thereof are respectively connected to the sources of the first NLDMOS tube LD1 and the second NLDMOS tube LD2; the gate and source of the third NMOS tube MN3 are connected to the floating ground VSW, and the drain thereof is connected to the drain of the first NLDMOS tube LD1; the source of the fourth NMOS tube MN4 is connected to the floating ground VSW, the gate and the drain thereof are short-circuited and then connected to the drain of the seventh PMOS tube MP7; the gate of the fifth NMOS tube MN5 is connected to the gate of the fourth NMOS tube MN4, the source thereof is connected to the floating ground VSW, and the drain thereof is connected to the drain of the ninth PMOS tube MP9; the gate of the sixth NMOS tube MN6 is connected to the gate of the seventh NMOS tube MN7. The gate of the seventh NMOS tube MN7 is connected to the floating ground VSW, and the drain of the seventh NMOS tube MN7 is connected to the drain of the tenth PMOS tube MP10; the gate and the drain of the seventh NMOS tube MN7 are short-circuited and then connected to the drain of the tenth PMOS tube MP10, and the source of the seventh NMOS tube MN7 is connected to the floating ground VSW; the gate and the source of the eighth NMOS tube MN8 are connected to the floating ground VSW, and the drain of the eighth NMOS tube MN8 is connected to the drain of the second NLDMOS tube LD2; the gate and the source of the ninth NMOS tube MN9 are connected to the floating ground VSW, and the drain of the ninth NMOS tube MN9 is connected to the drain of the third NLDMOS tube LD3; the gates of the tenth NMOS tube MN10 and the eleventh NMOS tube MN11 are connected to the output end of the fifth inverter INV5, the sources of the seventh NMOS tube MN7 are connected to the floating ground VSW, and the drains of the seventh NMOS tube MP7 and the tenth PMOS tube MP10 are connected to the sources of the seventh PMOS tube MP7 and the tenth PMOS tube MP10 respectively;

[0010] The gate and drain of the first PMOS tube MP1 are short-circuited, connected to the drain of the first NLDMOS tube LD1, and its source is connected to the floating power rail VDDH; the gate of the second PMOS tube MP2 is connected to the gate of the first PMOS tube MP1, its source is connected to the floating power rail VDDH, and its drain is connected to the source of the seventh PMOS tube MP7; the gate of the third PMOS tube MP3 is connected to the gate of the first PMOS tube MP1, its source is connected to the floating power rail VDDH, and its drain is connected to the source of the eighth PMOS tube MP8; the source of the fourth PMOS tube MP4 is connected to the floating power rail VDDH, its gate is connected to the gate of the sixth PMOS tube MP6, and its drain is connected to the ninth PMOS tube MP9. The source of the fifth PMOS tube MP5 is connected to the floating power rail VDDH, the gate thereof is connected to the gate of the sixth PMOS tube MP6, and the drain thereof is connected to the source of the tenth PMOS tube MP10; the gate and the drain of the sixth PMOS tube MP6 are short-circuited, connected to the drain of the second NLDMOS tube LD2, and the source thereof is connected to the floating power rail VDDH; the gates of the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9, and the tenth PMOS tube MP10 are connected to the output end of the fifth inverter INV5; the source of the eleventh PMOS tube MP11 is connected to the floating power rail VDDH, the gate and the drain thereof are short-circuited, and connected to the drain of the third NLDMOS tube LD3;

[0011] The first resistor R1, the second resistor R2 and the third resistor R3 have their upper ends connected to the floating power rail VDDH, and their lower ends connected to the drains of the first PMOS transistor MP1, the sixth PMOS transistor MP6 and the eleventh PMOS transistor MP11 respectively;

[0012] The first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4 and the fifth inverter INV5 are all connected between the floating power rail VDDH and the floating ground VSW; the input of the first inverter INV1 is connected to the drain of the fifth NMOS tube MN5, and its output is connected to the drain of the sixth NMOS tube MN6; the input of the second inverter INV2 is connected to the output of the first inverter INV1, and its output is connected to the input of the first inverter INV1; the input of the third inverter INV3 is connected to the input of the first inverter INV1, and its output is connected to OUT+; the input of the fourth inverter INV4 is connected to the output of the first inverter INV1, and the output is connected to OUT-; the input of the fifth inverter INV5 is connected to the drain of the ninth NMOS tube MN9.

[0013] Furthermore, when noise comes, the level shift circuit reacts in time and uses the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9 and the tenth PMOS tube MP10 to block the noise, and uses the tenth NMOS tube MN10 and the eleventh NMOS tube MN11 to discharge the charge stored in the isolation point, thereby ensuring the stability of the circuit operation.

[0014] Further, when positive dVSW / dt comes, the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9 and the tenth PMOS tube MP10 are turned off, so that the noise cannot be transmitted to the output end; when the noise ends and the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9 and the tenth PMOS tube MP10 are turned on, the charges affecting the circuit output stored in the source of the seventh PMOS tube MP7 and the eighth PMOS tube MP8 are also discharged by the tenth NMOS tube MN10 and the eleventh NMOS tube MN11, and will not affect the output end, thereby ensuring the stability of the circuit operation; when negative dVSW / dt comes, the diode of the first PMOS tube MP1 and the first resistor R1, the diode of the sixth PMOS tube MP6 and the second resistor R2 discharge the charges on the first NLDMOS tube LD1 and the second NLDMOS tube LD2, and clamp the voltage to prevent the risk of breakdown; at this time, the first PMOS tube MP1 and the sixth PMOS tube MP6 are not turned on and will not affect the output.

[0015] Some small floats on the power rail, such as the small rise of the VSW node when the dead zone negative voltage in the half-bridge chip is turned on when the lower tube is turned on, can divert the discharge path to ensure the stability of the output.

[0016] The beneficial effect of the present invention is that the present invention uses two additional NMOS tubes to discharge the charge accumulation generated by the PMOS tube blocking the noise transmitted to the output end, thereby avoiding the problem that the peak pulse generated at the key node of the signal transmission path at high frequency may affect the output waveform. The circuit of the present invention has strong anti-noise ability and can effectively eliminate the influence of noise on the output, and has low delay and good stability. Therefore, it can be used on higher frequency GaN gate drive chips to ensure the stable operation of the chip.

[0017] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0019] Figure 1 Circuit diagrams used for prior art;

[0020] Figure 2 The level shift circuit diagram of the present invention is applicable to the high-frequency GaN gate driver chip;

[0021] Figure 3 The position of the level shift circuit of the present invention in the half-bridge driver chip architecture;

[0022] Figure 4 This is a working waveform diagram without NMOS tubes MN10 and MN11;

[0023] Figure 5 It is a working waveform diagram of the level shift circuit of the present invention;

[0024] Figure 6 This is the simulation waveform of the overall driver chip. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0026] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0027] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0028] See also Figure 2 to Figure 6 , the level shift circuit provided by the present invention is as follows Figure 2As shown, it is composed of a first PMOS tube MP1 to an eleventh PMOS tube MP11, a first NMOS tube MN1 to an eleventh NMOS tube MN11, a first resistor R1, a second resistor R2, a third resistor R3, a first NLDMOS tube LD1 to a third NLDMOS tube LD3, and a first inverter INV1 to a fifth inverter INV5. Figure 2 In the example, VDDH is the floating power rail voltage and VSW is the floating ground.

[0029] Apply this circuit to GaN half-bridge drive system. Figure 3 As shown. When the upper tube of the half-bridge structure is turned on, the voltage of the floating ground VSW will be raised quickly. Since the high-voltage area of ​​the GaN half-bridge driver chip is powered by a bootstrap capacitor, the voltage of the floating power rail VDDH will also be raised. However, the parasitic capacitance of the NLDMOS drain to the ground is very large, resulting in the failure of its drain voltage to follow the change of the floating power rail in time, forming a voltage drop and turning on MP2, MP3, MP4, and MP5, transferring noise to the output, causing logic function disorder.

[0030] In the present invention, an additional path from the floating power supply VDDH to the ground is introduced. The on-resistance of MP11 is much larger than that of MP1 and MP7. And there are two additional NMOS tubes. When positive dVSW / dt comes, the potential of node G3 changes more slowly than that of nodes G1 and G2. When the potential of nodes G1 and G2 drops relative to the floating power rail to turn on MP2, MP3, MP4, and MP5, node G3 has already triggered the inverter to output a high level, turning off MP7, MP8, MP9, and MP10, so that the noise cannot be transmitted to the output end. If there is no MN10 and MN11, the waveform is as follows Figure 4 As shown. After the noise ends, a spike pulse will appear at nodes F1 and F2. In order to prevent the pulse from affecting the output of the circuit, the gate voltage of MP7, MP8, MP9, and MP10 needs to drop slowly, prolonging the time for discharging the stored charge, so as to control the spike below the level reversal point. Therefore, when the frequency is too fast, the stored charge may not be completely discharged, and the next control signal of the circuit has arrived. At this time, the gate voltage of MP7, MP8, MP9, and MP10 is too high, and the current is small, which may cause the output to fail to flip. In this case, by introducing two additional NMOS tubes MN10 and MN11, when MP7, MP8, MP9, and MP10 are turned off, MN10 and MN11 will be turned on, thereby discharging the charge stored at the source end of MP7 and MP10. The working waveform is shown as follows Figure 5 As shown, the output is stable. In addition, controlling the conduction of LD1 and LD2 through MN1 and MN2 will speed up the signal transmission speed and further reduce the circuit delay. The simulation diagram in the half-bridge driver chip architecture is as follows Figure 6As shown, it can be seen that the chip output is stable and the BUCK circuit output is stable.

[0031] In summary, the circuit of the present invention uses two additional NMOS tubes to discharge the charge accumulation generated by the PMOS tube blocking the noise transmitted to the output end, avoiding the problem that the spike pulse generated at the key node on the signal transmission path at high frequency may affect the output waveform. Therefore, the level shift circuit can be used on higher frequency GaN gate driver chips to ensure the stable operation of the chip.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A level shift circuit suitable for a high-frequency GaN gate driver chip, characterized in that: The circuit includes: a first PMOS tube MP1 to an eleventh PMOS tube MP11, a first NMOS tube MN1 to an eleventh NMOS tube MN11, a first resistor R1 to a third resistor R3, a first NLDMOS tube LD1 to a third NLDMOS tube LD3, and a first inverter INV1 to a fifth inverter INV5; The gates of the first NLDMOS transistor LD1 and the second NLDMOS transistor LD2 are respectively connected to the low voltage power supply VDD, and the sources thereof are respectively connected to the drains of the first NMOS transistor MN1 and the second NMOS transistor MN2, and the drains thereof are respectively connected to the drains of the first PMOS transistor MP1 and the sixth PMOS transistor MP6; the gate and source of the third NLDMOS transistor LD3 are grounded, and the drain thereof is connected to the drain of the eleventh PMOS transistor MP11; The gates of the first NMOS tube MN1 and the second NMOS tube MN2 are respectively connected to the output of the low-voltage narrow pulse signal, the sources thereof are grounded, and the drains thereof are respectively connected to the sources of the first NLDMOS tube LD1 and the second NLDMOS tube LD2; the gate and source of the third NMOS tube MN3 are connected to the floating ground VSW, and the drain thereof is connected to the drain of the first NLDMOS tube LD1; the source of the fourth NMOS tube MN4 is connected to the floating ground VSW, the gate and the drain thereof are short-circuited and then connected to the drain of the seventh PMOS tube MP7; the gate of the fifth NMOS tube MN5 is connected to the gate of the fourth NMOS tube MN4, the source thereof is connected to the floating ground VSW, and the drain thereof is connected to the drain of the ninth PMOS tube MP9; the gate of the sixth NMOS tube MN6 is connected to the gate of the seventh NMOS tube MN7. The gate of the seventh NMOS tube MN7 is connected to the floating ground VSW, and the drain of the seventh NMOS tube MN7 is connected to the drain of the tenth PMOS tube MP10; the gate and the drain of the seventh NMOS tube MN7 are short-circuited and then connected to the drain of the tenth PMOS tube MP10, and the source of the seventh NMOS tube MN7 is connected to the floating ground VSW; the gate and the source of the eighth NMOS tube MN8 are connected to the floating ground VSW, and the drain of the eighth NMOS tube MN8 is connected to the drain of the second NLDMOS tube LD2; the gate and the source of the ninth NMOS tube MN9 are connected to the floating ground VSW, and the drain of the ninth NMOS tube MN9 is connected to the drain of the third NLDMOS tube LD3; the gates of the tenth NMOS tube MN10 and the eleventh NMOS tube MN11 are connected to the output end of the fifth inverter INV5, the sources of the seventh NMOS tube MN7 are connected to the floating ground VSW, and the drains of the seventh NMOS tube MP7 and the tenth PMOS tube MP10 are connected to the sources of the seventh PMOS tube MP7 and the tenth PMOS tube MP10 respectively; The gate and drain of the first PMOS tube MP1 are short-circuited, connected to the drain of the first NLDMOS tube LD1, and its source is connected to the floating power rail VDDH; the gate of the second PMOS tube MP2 is connected to the gate of the first PMOS tube MP1, its source is connected to the floating power rail VDDH, and its drain is connected to the source of the seventh PMOS tube MP7; the gate of the third PMOS tube MP3 is connected to the gate of the first PMOS tube MP1, its source is connected to the floating power rail VDDH, and its drain is connected to the source of the eighth PMOS tube MP8; the source of the fourth PMOS tube MP4 is connected to the floating power rail VDDH, its gate is connected to the gate of the sixth PMOS tube MP6, and its drain is connected to the ninth PMOS tube MP9. The source of the fifth PMOS tube MP5 is connected to the floating power rail VDDH, the gate thereof is connected to the gate of the sixth PMOS tube MP6, and the drain thereof is connected to the source of the tenth PMOS tube MP10; the gate and the drain of the sixth PMOS tube MP6 are short-circuited, connected to the drain of the second NLDMOS tube LD2, and the source thereof is connected to the floating power rail VDDH; the gates of the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9, and the tenth PMOS tube MP10 are connected to the output end of the fifth inverter INV5; the source of the eleventh PMOS tube MP11 is connected to the floating power rail VDDH, the gate and the drain thereof are short-circuited, and connected to the drain of the third NLDMOS tube LD3; The first resistor R1, the second resistor R2 and the third resistor R3 have their upper ends connected to the floating power rail VDDH, and their lower ends connected to the drains of the first PMOS transistor MP1, the sixth PMOS transistor MP6 and the eleventh PMOS transistor MP11 respectively; The first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4 and the fifth inverter INV5 are all connected between the floating power rail VDDH and the floating ground VSW; the input of the first inverter INV1 is connected to the drain of the fifth NMOS tube MN5, and its output is connected to the drain of the sixth NMOS tube MN6; the input of the second inverter INV2 is connected to the output of the first inverter INV1, and its output is connected to the input of the first inverter INV1; the input of the third inverter INV3 is connected to the input of the first inverter INV1, and its output is connected to OUT+; the input of the fourth inverter INV4 is connected to the output of the first inverter INV1, and the output is connected to OUT-; the input of the fifth inverter INV5 is connected to the drain of the ninth NMOS tube MN9.

2. The level shift circuit according to claim 1, characterized in that: When noise comes, the level shift circuit reacts in time and uses the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9 and the tenth PMOS tube MP10 to cut off the noise, and uses the tenth NMOS tube MN10 and the eleventh NMOS tube MN11 to discharge the charge stored at the cutoff point, so as to ensure the stability of the circuit operation. Specifically, when positive dVSW / dt comes, the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9 and the tenth PMOS tube MP10 are turned off, so that the noise cannot be transmitted to the output end; when the noise ends and the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9 and the tenth PMOS tube MP10 are turned on, the charge affecting the circuit output stored in the source of the seventh PMOS tube MP7 and the tenth PMOS tube MP10 is also discharged by the tenth NMOS tube MN10 and the eleventh NMOS tube MN11, and will not affect the output end, so as to ensure the stability of the circuit operation.

3. The level shift circuit according to claim 1 or 2, characterized in that: When negative dVSW / dt comes, the diode of the first PMOS tube MP1 and the first resistor R1, the diode of the sixth PMOS tube MP6 and the second resistor R2 discharge the charges on the first NLDMOS tube LD1 and the second NLDMOS tube LD2, and clamp the voltage to prevent the risk of breakdown; at this time, the first PMOS tube MP1 and the sixth PMOS tube MP6 are not turned on and will not affect the output.

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