A universal test system for the radio frequency industry

Abstract

The invention discloses a universal test system for radio frequency industry, relates to the field of radio frequency test technology, a data board includes a system power supply and a plurality of preset peripheral interfaces; a core board includes a main chip, an interface circuit connected between the core board and the data board, a main chip peripheral circuit, a power configuration circuit and a power early warning circuit; a test board includes an ADC input circuit, a DAC output circuit, and an interface circuit connected between the test board and the core board; a three-layer structure design is adopted, which is sequentially a test board, a core board and a data board from top to bottom, the test board is connected to the core board through a first connecting component, the core board is connected to the data board through a second connecting component, and the test board is connected to the data board through a third connecting component. The test system of the present invention not only reduces the layout area occupied by the entire test system, but also facilitates the unified power management of the test system, and also solves the problem that the test cannot be completed or the test fails due to power anomaly.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency testing technology, and in particular to a universal testing system for the radio frequency industry. Background Art

[0002] Most of the existing RF (radio frequency) performance test processing for the radio frequency industry uses the AXRF47 development board. The development board consists of an ACRF47 core board and a carrier board, and the core board and the carrier board are connected using a high-speed inter-board connector. The ACRF47 core board uses Xilinx's ZU47DR FPGA main chip, which can provide a comprehensive RF signal chain to meet the needs of wireless, cable TV access, test and measurement, early warning / radar and other high-performance RF applications; the carrier board expands the core board with a rich peripheral interface, including M.2 SSD interface, USB3.0 interface, Gigabit Ethernet interface, JTAG / UART interface, TF card interface, sfp interface and qsfp interface; and the high-speed inter-board connector plays the role of connecting the core board and the carrier board, and the bottom plate of the high-speed board connector is equipped with a system power supply and a buck regulator, which is responsible for providing working power to the core board, while the carrier board is powered by multiple multi-channel power chips.

[0003] However, existing development boards have the following disadvantages: 1) The core board and the carrier board are connected through a high-speed board connector, resulting in a large layout area occupied by the entire development board; 2) The entire development board lacks unified power management, the core board is powered by a high-speed board connector, and the carrier board is powered by multiple circuit chips; 3) There is a lack of effective monitoring of the power supply in the development board. For example, during the test of a signal or program, if the power input voltage or output voltage exceeds the set range, even if the signal or program is normal, the test will ultimately fail to complete. Summary of the invention

[0004] In order to solve the deficiencies of the prior art, the present invention provides a universal test system for the radio frequency industry, the test system comprising:

[0005] Data board: includes system power supply and multiple preset peripheral interfaces;

[0006] Core board: including the main chip, the interface circuit connecting the core board and the data board, the peripheral circuit designed around the main chip, the power configuration circuit and the power warning circuit designed around the system power supply;

[0007] Test board: including an ADC input single-ended signal conversion differential signal circuit, a DAC output differential signal conversion single-ended signal circuit, and an interface circuit connecting the test board with the core board;

[0008] The test system adopts a three-layer structure design, which includes the test board, the core board and the data board from top to bottom. The test board is connected to the core board via a first connection component, the core board is connected to the data board via a second connection component, and the test board is connected to the data board via a third connection component.

[0009] The present invention is realized through the following technical scheme: the scheme includes a test board, a core board and a data board, the test board includes an ADC input single-ended signal conversion differential signal circuit, a DAC output differential signal conversion single-ended signal circuit, and an interface circuit connecting the test board and the core board, the core board includes a main chip, an interface circuit connecting the core board and the data board, a peripheral circuit designed around the main chip, a power configuration circuit and a power warning circuit designed around a system power supply, the data board includes a system power supply and multiple peripheral interfaces, the scheme reduces the layout area occupied by the entire test system by adopting a three-layer structure design, and at the same time, a system power supply is designed on the data board, the system power supply is responsible for supplying power to the entire test system, which is convenient for the test system to uniformly manage power, and a power warning circuit is correspondingly arranged on the core board, the power supply of the entire test system is effectively monitored by the power warning circuit, and the problem of test failure or test failure due to power supply abnormality is solved.

[0010] As an optional technical solution,

[0011] The system power supply includes a power input circuit, a transistor switch control circuit, a voltage stabilizing filter circuit and an LED light indication circuit;

[0012] The power input circuit includes: a J2 chip, a resistor R1, a resistor R2 and a capacitor C1, wherein pins 1, 4 and 2 of the J2 chip are all connected to a voltage source VCC12P, pins 5, 3 and 6 of the J2 chip are all grounded, one end of the resistor R1, one end of the capacitor C1 and one end of the resistor R2 are all connected to the voltage source VCC12P, and the other end of the capacitor C1 is connected to the other end of the resistor R2;

[0013] The transistor switch control circuit includes: a switch chip Q1, a transistor Q2, a resistor R3 and a switch SW1, wherein the No. 1 pin of the switch SW1 is connected to the other end of the resistor R1, the No. 2 pin of the switch SW1 is connected to the gate of the transistor Q2, the No. 3 pin, the SH1 pin and the SH2 pin of the switch SW1 are all grounded, the source of the transistor Q2 is grounded, the drain of the transistor Q2 is connected to one end of the resistor R3, the other end of the resistor R3 and the other end of the resistor R2 are both connected to the No. 4 pin of the switch chip Q1, and the No. 5 pin of the switch SW1 is connected to the gate of the transistor Q2. The No. 1, No. 2 and No. 3 pins of the switch chip Q1 are all connected to one end of the resistor R2, the No. 5, No. 6, No. 7 and No. 8 pins of the switch chip Q1 are all connected to the voltage stabilizing filter circuit, the No. 1, No. 2 and No. 3 pins of the switch chip Q1 are all connected to the source of the corresponding transistor inside the switch chip Q1, the No. 4 pin of the switch chip Q1 is connected to the gate of the corresponding transistor inside the switch chip Q1, and the No. 5, No. 6, No. 7 and No. 8 pins of the switch chip Q1 are all connected to the drain of the corresponding transistor inside the switch chip Q1;

[0014] The voltage stabilizing filter circuit includes: a chip U1, a capacitor C2, a capacitor C3, a power output test point J1 and a power output interface J3, one end of the capacitor C2 is connected to pin No. 4 of the switch chip Q1, pins No. 5, No. 6, No. 7 and No. 8 of the switch chip Q1 are all connected to the other end of the capacitor C2, the other end of the capacitor C2 and pin No. 1 of the chip U1 are all connected to one end of the capacitor C3, the other end of the capacitor C3 and pin No. 3 of the chip U1 are all grounded, pins No. CG1, No. CG2 and No. CG3 of the chip U1 are all grounded, pin No. CB of the chip U1 is used to connect to the power output test point J1, pins No. 1, No. 2, No. 3 and No. 4 of the power output interface J3 are all connected to the voltage source VCC12SW, and pins No. 5, No. 6, No. 7, No. 8, No. 9 and No. 10 of the power output interface are all grounded;

[0015] The LED light indication circuit includes: a status indicator light DS1, a resistor R4 and a capacitor C4, wherein the positive electrode of the status indicator light DS1 is connected to the CB pin of the chip U1, the negative electrode of the status indicator light DS1 is connected to one end of the resistor R4, the other end of the resistor R4 and the negative electrode of the capacitor C4 are both grounded, and the positive electrode of the capacitor C4 is connected to the power output test point J1 to output the voltage source VCC12SW;

[0016] The system power supply further includes a jumper wire J34, one end of the jumper wire J34 is connected to pin No. 4 of the switch chip Q1, and the other end of the jumper wire J34 is used to connect to a preset circuit.

[0017] As an optional technical solution, the power warning circuit includes 3 IRPS5401 power chips, 3 IR38060 power chips, 1 IR38064 power chip, a main chip U1-48 and a level conversion chip U81;

[0018] The level conversion chip U81 is configured as follows: pin 20, pin 18 and pin 17 are respectively connected to three IR38060 power chips, pin 16 is connected to an IR38064 power chip, pins 15, 14 and 13 are respectively connected to three IRPS5401 power chips, pin 12 is vacant, pin 11 is grounded, pin 19 is connected to the PMIC1VCC node, one end of capacitor C822 is connected to the PMIC1VCC node, the other end of the capacitor C822 is grounded, the PMIC1VCC node is respectively connected to one end of resistors R592, R593, R594, R595, R596, R597 and R598, the other ends of the resistors R592, R593 and R594 are respectively connected to three IR38060 power chips, and the resistors R5 The other end of 95 is connected to the IR38064 power chip, the other ends of the resistors R596, R597 and R598 are respectively connected to three IRPS5401 power chips, pin 10 is connected to one end of the resistor R591, the other end of the resistor R591 is connected to the voltage source VCC1V8, pin 9 is vacant, pin 2 is connected to the voltage source VCC1V8, one end of the capacitor C823 is connected to the voltage source VCC1V8, one end of the capacitor C823 is grounded, pins 1, 3 and 4 are separated for outputting power warning signals of the three IR38060 power chips after level conversion, pin 5 is used to output the power warning signal of the IR38064 power chip after level conversion, and pins 6, 7 and 8 are respectively used to output the power warning signals of the three IRPS5401 power chips after level conversion;

[0019] The main chip U1-48 is configured as follows: pin J12 is connected to pin 1 of the level conversion chip U81, pin K12 is connected to pin 3 of the level conversion chip U81, pin H11 is connected to pin 4 of the level conversion chip U81, pin J11 is connected to pin 5 of the level conversion chip U81, pin K10 is connected to pin 6 of the level conversion chip U81, pin K11 is connected to pin 7 of the level conversion chip U81, and pin H9 is connected to pin 8 of the level conversion chip U81.

[0020] As an optional technical solution, the power supply early warning circuit performs early warning including:

[0021] Power warning signals are generated by 3 IRPS5401 power chips, 3 IR38060 power chips and 1 IR38064 power chip;

[0022] The power warning signal is input to the main chip U1-48 after being converted by the level conversion chip U81;

[0023] The main chip U1-48 analyzes and processes the received power warning signal. When the power input voltage exceeds or is lower than the first set range, the input voltage abnormality warning is triggered; when the power output voltage exceeds or is lower than the second set range, the output voltage abnormality warning is triggered; when the current is abnormal, it is fed back to trigger the current abnormality warning; when the power chip temperature is too high, the overheating warning is triggered.

[0024] As an optional technical solution, the test system further includes:

[0025] When the test system is used for signal acquisition, the test board is used to connect to a preset signal source through a power divider, and the preset signal source is used to output an ADC single-ended signal; the peripheral interface on the data board is used to connect to a computer and a logic analyzer respectively, and the computer is configured with Vitis software and Vivado software, and the Vitis software is used to configure the acquisition program to the core board, and the core board is used to acquire signals through the acquisition program and output the signal acquisition results to the logic analyzer, and the Vivado software is used to view the signal acquisition results of the logic analyzer.

[0026] As an optional technical solution, the test system further includes:

[0027] When the test system is used for program testing, the peripheral interface on the data board is used to connect to a computer; the computer is used to burn the program to be tested into the main chip of the core board, and after the burning is completed, a control signal is sent to the main chip of the core board through a preset program; the main chip is used to receive the control signal sent by the preset program to parse and obtain a parsing result, and based on the parsing result, the program to be tested is tested to obtain a test result; the display window of the preset program in the computer is used to display the test result of the program to be tested.

[0028] As an optional technical solution, the first connecting component includes a first socket and a plurality of first studs, the second connecting component includes a second socket and a plurality of second studs, the third connecting component includes a plurality of third studs, the test board is connected to the core board through the first socket and the plurality of first studs, the core board is connected to the data board through the second socket and the plurality of second studs, and the test board is connected to the data board through the plurality of third studs.

[0029] As an optional technical solution, all peripheral circuits include Dual QSPI circuit, PL-side DDR4 circuit, UART circuit, system clock circuit, PS-side DDR4 circuit, system status indicator circuit and system I2C0 circuit.

[0030] As an optional technical solution, multiple peripheral preset interfaces include: PL-side serial port, PS-side serial port, USB3.0 interface, SD card storage interface, network port interface and optical fiber interface.

[0031] As an optional technology, the model of the main chip is XCZU27DR-FFVE-1156-2-I.

[0032] One or more technical solutions provided by the present invention have at least the following technical effects or advantages:

[0033] The present invention provides a universal test system for the radio frequency industry. By adopting a three-layer structural design, the layout area occupied by the entire test system is reduced. At the same time, a system power supply is designed on the data board. The system power supply is responsible for supplying power to the entire test system, which is convenient for the test system to uniformly manage power. A power early warning circuit is correspondingly arranged on the core board. The power supply of the entire test system is effectively monitored by the power early warning circuit, so as to solve the problem that the test cannot be completed or the test fails due to power abnormality.

[0034] The present invention designs a system power supply, which has the following advantages: simple and efficient MOSFET switch design: using N-channel MOSFET (SI7157DP) as the main power switch, can effectively control the on and off of the 12V power supply, and MOSFET has higher efficiency and faster response time than traditional mechanical relays. Better power supply noise suppression: multiple decoupling capacitors (C1, C2, C3) are used in the circuit, which can effectively filter out high-frequency noise and transient voltage spikes in the power supply, thereby improving the stability of the power supply and ensuring the normal operation of the load. Low power consumption control: by using BSS138 small MOSFET (Q2) to control the main switch (Q1), low power consumption control can be achieved. Q2 only needs a small gate drive current to control the main switch of large current, and the power consumption is extremely low. Load status indication: LED (DS1) is used as an indicator light, which can intuitively reflect the working status of the circuit, and is convenient for debugging and maintenance. Flexible manual control: the circuit realizes manual control of the MOSFET switch (Q2) through the SW1 button, and the power supply can be easily turned on and off. Protection and filtering: The large-capacity capacitor (C4) provides excellent filtering to ensure smooth power supply to subsequent loads (such as LEDs), especially for devices or modules that are sensitive to power supply noise.

[0035] The present invention designs a power warning circuit, which generates a power warning signal through multiple power chips, then performs level conversion through a level conversion chip, and finally performs analysis and processing through a main chip, and performs corresponding power warning for different types of power anomalies. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of the present invention, and do not constitute a limitation on the embodiments of the present invention;

[0037] Figure 1 This is a schematic diagram of the composition of a universal test system for the radio frequency industry in the present invention;

[0038] Figure 2 is a circuit diagram of a system power supply in the present invention;

[0039] Figure 3 It is a schematic diagram of the power supply early warning circuit in the present invention;

[0040] Figure 4 This is a schematic diagram of the structure of a universal test system for the radio frequency industry in the present invention;

[0041] Among them, 1-first stud, 2-first socket, 3-second stud, 4-second socket, 5-third stud. DETAILED DESCRIPTION

[0042] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0043] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those within the scope of this description. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0044] Example

[0045] Please refer to Figure 1~Figure 4 , Figure 1 This is a schematic diagram of the composition of a universal test system for the radio frequency industry in the present invention; Figure 2 is a circuit diagram of a system power supply in the present invention; Figure 3 It is a schematic diagram of the power supply early warning circuit in the present invention; Figure 4 The present invention is a schematic diagram of a universal test system structure for the radio frequency industry.

[0046] A general test system for the radio frequency industry includes:

[0047] Data board: includes system power supply and multiple preset peripheral interfaces;

[0048] Core board: including the main chip, the interface circuit connecting the core board and the data board, the peripheral circuit designed around the main chip, the power configuration circuit and the power warning circuit designed around the system power supply;

[0049] Test board: including an ADC input single-ended signal conversion differential signal circuit, a DAC output differential signal conversion single-ended signal circuit, and an interface circuit connecting the test board with the core board;

[0050] The test system adopts a three-layer structure design, which includes the test board, the core board and the data board from top to bottom. The test board is connected to the core board via a first connection component, the core board is connected to the data board via a second connection component, and the test board is connected to the data board via a third connection component.

[0051] The specific embodiments of the present invention are as follows:

[0052] For the data board: multiple preset peripheral interfaces include PL-side serial port, PS-side serial port, USB3.0 interface, SD card storage interface, network port interface and optical fiber interface.

[0053] The system power supply includes a power input circuit, a transistor switch control circuit, a voltage stabilizing filter circuit and an LED light indication circuit;

[0054] The power input circuit includes: a J2 chip, a resistor R1, a resistor R2 and a capacitor C1, wherein pins 1, 4 and 2 of the J2 chip are all connected to a voltage source VCC12P, pins 5, 3 and 6 of the J2 chip are all grounded, one end of the resistor R1, one end of the capacitor C1 and one end of the resistor R2 are all connected to the voltage source VCC12P, and the other end of the capacitor C1 is connected to the other end of the resistor R2;

[0055] The transistor switch control circuit includes: a switch chip Q1, a transistor Q2, a resistor R3 and a switch SW1, wherein the No. 1 pin of the switch SW1 is connected to the other end of the resistor R1, the No. 2 pin of the switch SW1 is connected to the gate of the transistor Q2, the No. 3 pin, the SH1 pin and the SH2 pin of the switch SW1 are all grounded, the source of the transistor Q2 is grounded, the drain of the transistor Q2 is connected to one end of the resistor R3, the other end of the resistor R3 and the other end of the resistor R2 are both connected to the No. 4 pin of the switch chip Q1, and the No. 5 pin of the switch SW1 is connected to the gate of the transistor Q2. The No. 1, No. 2 and No. 3 pins of the switch chip Q1 are all connected to one end of the resistor R2, the No. 5, No. 6, No. 7 and No. 8 pins of the switch chip Q1 are all connected to the voltage stabilizing filter circuit, the No. 1, No. 2 and No. 3 pins of the switch chip Q1 are all connected to the source of the corresponding transistor inside the switch chip Q1, the No. 4 pin of the switch chip Q1 is connected to the gate of the corresponding transistor inside the switch chip Q1, and the No. 5, No. 6, No. 7 and No. 8 pins of the switch chip Q1 are all connected to the drain of the corresponding transistor inside the switch chip Q1;

[0056] The voltage stabilizing filter circuit includes: a chip U1, a capacitor C2, a capacitor C3, a power output test point J1 and a power output interface J3, one end of the capacitor C2 is connected to pin No. 4 of the switch chip Q1, pins No. 5, No. 6, No. 7 and No. 8 of the switch chip Q1 are all connected to the other end of the capacitor C2, the other end of the capacitor C2 and pin No. 1 of the chip U1 are all connected to one end of the capacitor C3, the other end of the capacitor C3 and pin No. 3 of the chip U1 are all grounded, pins No. CG1, No. CG2 and No. CG3 of the chip U1 are all grounded, pin No. CB of the chip U1 is used to connect to the power output test point J1, pins No. 1, No. 2, No. 3 and No. 4 of the power output interface J3 are all connected to the voltage source VCC12SW, and pins No. 5, No. 6, No. 7, No. 8, No. 9 and No. 10 of the power output interface are all grounded;

[0057] The LED light indication circuit includes: a status indicator light DS1, a resistor R4 and a capacitor C4, wherein the positive electrode of the status indicator light DS1 is connected to the CB pin of the chip U1, the negative electrode of the status indicator light DS1 is connected to one end of the resistor R4, the other end of the resistor R4 and the negative electrode of the capacitor C4 are both grounded, and the positive electrode of the capacitor C4 is connected to the power output test point J1 to output the voltage source VCC12SW;

[0058] The system power supply further includes a jumper wire J34, one end of the jumper wire J34 is connected to pin No. 4 of the switch chip Q1, and the other end of the jumper wire J34 is used to connect to a preset circuit.

[0059] Among them, the J2 chip is a power input interface, providing a 12V DC power supply, pins 1, 2 and 4 lead out 12V voltage, and pins 3, 5 and 6 are grounded; resistors R1 and R2 form a voltage divider network, the purpose of which is to control the opening condition of the switch chip Q1; capacitor C1 is a decoupling capacitor at the input end, the purpose of which is to filter out the noise and ripple of the input voltage; the switch chip Q1 is used to control the on and off of the power supply, and resistor R2 provides a gate bias voltage for the switch chip Q1; transistor Q2 is a small signal N-channel MOS tube, which is used to control the gate voltage of the switch chip Q1. When transistor Q2 is turned on, it will lower the gate voltage of the switch chip Q1, so that the switch chip Q1 is turned off, thereby turning off the main power supply; resistor R3 is used to limit the current of the gate of transistor Q2 to prevent transistor Q2 from being broken down; switch SW1 is the main power switch, which controls the on and off of the main power supply by controlling whether transistor Q2 is turned on; chip U 1 is a voltage regulator chip for stepping down, which is responsible for stabilizing the input 12V voltage and outputting it for use by the subsequent circuit; capacitor C2 is the input capacitor of the voltage regulator filter circuit, and capacitor C3 is the output capacitor of the voltage regulator filter circuit, which is used to further filter out noise and provide a stable output voltage; J1 is the power output test point, which is used to test the output voltage, and J3 is the power output interface, which is used to provide the stabilized voltage to the entire test system; DS1 is the status indicator light, when the entire system power supply can output voltage normally, the indicator light DS1 will light up, indicating that the system power supply is working normally; resistor R4 is a current limiting resistor connected in series with the status indicator light DS1, ensuring that the current of the status indicator light DS1 is within a safe range; capacitor C4 is a large-capacity capacitor at the output end, which is used to provide stable power output and absorb transient voltage spikes; J34 is an optional jumper, when connected, it can control the preset circuit (bypass or other auxiliary circuit).

[0060] For the core board: the model of the main chip is XCZU27DR-FFVE-1156-2-I. The peripheral circuits designed around the main chip include Dual QSPI circuit, PL-end DDR4 circuit, UART circuit, system clock circuit, PS-end DDR4 circuit, system status indicator circuit and system I2C0 circuit; the interface circuit connecting the core board and the data board is used for data transmission between the core board and the data board; the system power supply supplies power to the entire test system through the power configuration circuit.

[0061] The power warning circuit includes: 3 IRPS5401 power chips, 3 IR38060 power chips, 1 IR38064 power chip, main chip U1-48 and level conversion chip U81;

[0062] The level conversion chip U81 is configured as follows: pin 20, pin 18 and pin 17 are respectively connected to three IR38060 power chips, pin 16 is connected to an IR38064 power chip, pins 15, 14 and 13 are respectively connected to three IRPS5401 power chips, pin 12 is vacant, pin 11 is grounded, pin 19 is connected to the PMIC1VCC node, one end of capacitor C822 is connected to the PMIC1VCC node, the other end of the capacitor C822 is grounded, the PMIC1VCC node is respectively connected to one end of resistors R592, R593, R594, R595, R596, R597 and R598, the other ends of the resistors R592, R593 and R594 are respectively connected to three IR38060 power chips, and the resistors R5 The other end of 95 is connected to the IR38064 power chip, the other ends of the resistors R596, R597 and R598 are respectively connected to three IRPS5401 power chips, pin 10 is connected to one end of the resistor R591, the other end of the resistor R591 is connected to the voltage source VCC1V8, pin 9 is vacant, pin 2 is connected to the voltage source VCC1V8, one end of the capacitor C823 is connected to the voltage source VCC1V8, one end of the capacitor C823 is grounded, pins 1, 3 and 4 are separated for outputting power warning signals of the three IR38060 power chips after level conversion, pin 5 is used to output the power warning signal of the IR38064 power chip after level conversion, and pins 6, 7 and 8 are respectively used to output the power warning signals of the three IRPS5401 power chips after level conversion;

[0063] The main chip U1-48 is configured as follows: pin J12 is connected to pin 1 of the level conversion chip U81, pin K12 is connected to pin 3 of the level conversion chip U81, pin H11 is connected to pin 4 of the level conversion chip U81, pin J11 is connected to pin 5 of the level conversion chip U81, pin K10 is connected to pin 6 of the level conversion chip U81, pin K11 is connected to pin 7 of the level conversion chip U81, and pin H9 is connected to pin 8 of the level conversion chip U81.

[0064] The power supply early warning circuit performs early warning including:

[0065] Power warning signals are generated by 3 IRPS5401 power chips, 3 IR38060 power chips and 1 IR38064 power chip;

[0066] The power warning signal is input to the main chip U1-48 after being converted by the level conversion chip U81;

[0067] The main chip U1-48 analyzes and processes the received power warning signal. When the power input voltage exceeds or is lower than the first set range, the input voltage abnormality warning is triggered; when the power output voltage exceeds or is lower than the second set range, the output voltage abnormality warning is triggered; when the current is abnormal, it is fed back to trigger the current abnormality warning; when the power chip temperature is too high, the overheating warning is triggered.

[0068] Among them, the main chip U1-48 is a sub-module of the main chip and is responsible for processing the power warning signal.

[0069] For the test board: the ADC input single-ended signal to differential signal circuit is used to convert the input ADC single-ended signal into a differential signal, the DAC output differential signal circuit to single-ended signal circuit is used to convert the output DAC differential signal into a single-ended signal, and the interface circuit connecting the test board and the core board is used for signal transmission between the test board and the core board. Furthermore, the test board also provides 4-way single-ended signal to differential signal circuit to solve the problem of too many ADC input signals.

[0070] Furthermore, the first connecting component includes a first socket 2 and a plurality of first studs 1, the second connecting component includes a second socket 4 and a plurality of second studs 3, the third connecting component includes a plurality of third studs 5, the test board is connected to the core board through the first socket 2 and the plurality of first studs 1, the core board is connected to the data board through the second socket 4 and the plurality of second studs 3, and the test board is connected to the data board through the plurality of third studs 5.

[0071] Furthermore, the test system further comprises:

[0072] When the test system is used for signal acquisition, the test board is used to connect to a preset signal source through a power divider, and the preset signal source is used to output an ADC single-ended signal; the peripheral interface on the data board is used to connect to a computer and a logic analyzer respectively, and the computer is configured with Vitis software and Vivado software, and the Vitis software is used to configure the acquisition program to the core board, and the core board is used to acquire signals through the acquisition program and output the signal acquisition results to the logic analyzer, and the Vivado software is used to view the signal acquisition results of the logic analyzer.

[0073] The steps of using the test system to collect signals include:

[0074] Starting a preset signal source, and setting the frequency and power of the signal output by the preset signal source;

[0075] The preset signal source is connected to the ADC input single-ended signal to differential signal circuit of the test board through a power divider;

[0076] Connecting the computer and the logic analyzer respectively through the peripheral interfaces on the data board;

[0077] Turn on the system power supply and configure the acquisition program to the core board through the Vitis software in the computer;

[0078] After the core board is started normally, the Vivado software in the computer is opened to check the signal acquisition results of the logic analyzer.

[0079] Among them, start the preset signal source, set the signal output frequency to 970MHz, the output power to 5dBm, connect to the SMA connector of the test board through the power divider, input the ADC input signal to the single-ended signal to differential signal circuit through the SMA connector for signal conversion, and input the converted signal to the core board; connect the computer and logic analyzer through the peripheral interface on the data board, turn on the system power, configure the acquisition program to the main chip of the core board through the Vitis software in the computer, after the core board starts normally, open the Vivado software in the computer to view the signal acquisition results of the logic analyzer.

[0080] Furthermore, the test system further comprises:

[0081] When the test system is used for program testing, the peripheral interface on the data board is used to connect to a computer; the computer is used to burn the program to be tested into the main chip of the core board, and after the burning is completed, a control signal is sent to the main chip of the core board through a preset program; the main chip is used to receive the control signal sent by the preset program to parse and obtain a parsing result, and based on the parsing result, the program to be tested is tested to obtain a test result; the display window of the preset program in the computer is used to display the test result of the program to be tested.

[0082] The steps of using the test system to perform program testing include:

[0083] Connecting to a computer via a peripheral interface on the data board;

[0084] Burn the program to be tested in the computer into the main chip of the core board;

[0085] After the burning is completed, a control signal is sent to the main chip of the core board through a preset program in the computer;

[0086] The main chip receives the control signal and performs analysis to obtain an analysis result;

[0087] Based on the analysis result, the main chip tests the program to be tested to obtain a test result;

[0088] The test results are returned to a display window of a preset program in the computer for display.

[0089] Among them, a computer is connected through the peripheral interface on the data board, and the program to be tested in the computer is burned into the main chip of the core board. After the burning of the program to be tested is completed, a control signal is sent to the main chip of the core board through a preset program in the computer. Common tools for program testing can be used for the preset program, and the present invention does not make specific limitations; the main chip receives and parses the control signal, and uses the parsed control signal to test the program to be tested to obtain a test result, and then returns the test result to the display window of the computer or other external display device for display.

[0090] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0091] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A universal test system for the radio frequency industry, characterized in that: The test system comprises: Data board: includes system power supply and multiple preset peripheral interfaces; Core board: including the main chip, the interface circuit connecting the core board and the data board, the peripheral circuit designed around the main chip, the power configuration circuit and the power warning circuit designed around the system power supply; Test board: including an ADC input single-ended signal conversion differential signal circuit, a DAC output differential signal conversion single-ended signal circuit, and an interface circuit connecting the test board with the core board; The test system adopts a three-layer structure design, which includes the test board, the core board and the data board from top to bottom. The test board is connected to the core board through a first connection component, the core board is connected to the data board through a second connection component, and the test board is connected to the data board through a third connection component; The test system further comprises: When the test system is used for signal acquisition, the test board is used to connect to a preset signal source through a power divider, and the preset signal source is used to output an ADC single-ended signal; the peripheral interface on the data board is used to connect a computer and a logic analyzer respectively, and the computer is configured with Vitis software and Vivado software, and the Vitis software is used to configure an acquisition program to the core board, and the core board is used to acquire signals through the acquisition program and output signal acquisition results to the logic analyzer, and the Vivado software is used to view the signal acquisition results of the logic analyzer; When the test system is used for program testing, the peripheral interface on the data board is used to connect to a computer; the computer is used to burn the program to be tested into the main chip of the core board, and after the burning is completed, a control signal is sent to the main chip of the core board through a preset program; the main chip is used to receive the control signal sent by the preset program to parse and obtain a parsing result, and based on the parsing result, the program to be tested is tested to obtain a test result; the display window of the preset program in the computer is used to display the test result of the program to be tested.

2. A universal test system for the radio frequency industry according to claim 1, characterized in that: The system power supply includes a power input circuit, a transistor switch control circuit, a voltage stabilizing filter circuit and an LED light indication circuit; The power input circuit includes: a J2 chip, a resistor R1, a resistor R2 and a capacitor C1, wherein pins 1, 4 and 2 of the J2 chip are all connected to a voltage source VCC12P, pins 5, 3 and 6 of the J2 chip are all grounded, one end of the resistor R1, one end of the capacitor C1 and one end of the resistor R2 are all connected to the voltage source VCC12P, and the other end of the capacitor C1 is connected to the other end of the resistor R2; The transistor switch control circuit includes: a switch chip Q1, a transistor Q2, a resistor R3 and a switch SW1, wherein the No. 1 pin of the switch SW1 is connected to the other end of the resistor R1, the No. 2 pin of the switch SW1 is connected to the gate of the transistor Q2, the No. 3 pin, the SH1 pin and the SH2 pin of the switch SW1 are all grounded, the source of the transistor Q2 is grounded, the drain of the transistor Q2 is connected to one end of the resistor R3, the other end of the resistor R3 and the other end of the resistor R2 are both connected to the No. 4 pin of the switch chip Q1, and the No. 5 pin of the switch SW1 is connected to the gate of the transistor Q2. The No. 1, No. 2 and No. 3 pins of the switch chip Q1 are all connected to one end of the resistor R2, the No. 5, No. 6, No. 7 and No. 8 pins of the switch chip Q1 are all connected to the voltage stabilizing filter circuit, the No. 1, No. 2 and No. 3 pins of the switch chip Q1 are all connected to the source of the corresponding transistor inside the switch chip Q1, the No. 4 pin of the switch chip Q1 is connected to the gate of the corresponding transistor inside the switch chip Q1, and the No. 5, No. 6, No. 7 and No. 8 pins of the switch chip Q1 are all connected to the drain of the corresponding transistor inside the switch chip Q1; The voltage stabilizing filter circuit includes: a chip U1, a capacitor C2, a capacitor C3, a power output test point J1 and a power output interface J3, one end of the capacitor C2 is connected to pin No. 4 of the switch chip Q1, pins No. 5, No. 6, No. 7 and No. 8 of the switch chip Q1 are all connected to the other end of the capacitor C2, the other end of the capacitor C2 and pin No. 1 of the chip U1 are all connected to one end of the capacitor C3, the other end of the capacitor C3 and pin No. 3 of the chip U1 are all grounded, pins No. CG1, No. CG2 and No. CG3 of the chip U1 are all grounded, pin No. CB of the chip U1 is used to connect to the power output test point J1, pins No. 1, No. 2, No. 3 and No. 4 of the power output interface J3 are all connected to the voltage source VCC12SW, and pins No. 5, No. 6, No. 7, No. 8, No. 9 and No. 10 of the power output interface are all grounded; The LED light indication circuit comprises: a status indicator light DS1, a resistor R4 and a capacitor C4, wherein the positive electrode of the status indicator light DS1 is connected to the CB pin of the chip U1, the negative electrode of the status indicator light DS1 is connected to one end of the resistor R4, the other end of the resistor R4 and the negative electrode of the capacitor C4 are both grounded, and the positive electrode of the capacitor C4 is connected to the power output test point J1 to output the voltage source VCC12SW; The system power supply further includes a jumper wire J34, one end of the jumper wire J34 is connected to pin No. 4 of the switch chip Q1, and the other end of the jumper wire J34 is used to connect to a preset circuit.

3. A universal test system for the radio frequency industry according to claim 1, characterized in that: The power warning circuit includes 3 IRPS5401 power chips, 3 IR38060 power chips, 1 IR38064 power chip, a main chip U1-48 and a level conversion chip U81; The level conversion chip U81 is configured as follows: pin 20, pin 18 and pin 17 are respectively connected to three IR38060 power chips, pin 16 is connected to an IR38064 power chip, pins 15, 14 and 13 are respectively connected to three IRPS5401 power chips, pin 12 is vacant, pin 11 is grounded, pin 19 is connected to the PMIC1VCC node, one end of capacitor C822 is connected to the PMIC1VCC node, the other end of the capacitor C822 is grounded, the PMIC1VCC node is respectively connected to one end of resistors R592, R593, R594, R595, R596, R597 and R598, the other ends of the resistors R592, R593 and R594 are respectively connected to three IR38060 power chips, and the resistors R5 The other end of 95 is connected to the IR38064 power chip, the other ends of the resistors R596, R597 and R598 are respectively connected to three IRPS5401 power chips, pin 10 is connected to one end of the resistor R591, the other end of the resistor R591 is connected to the voltage source VCC1V8, pin 9 is vacant, pin 2 is connected to the voltage source VCC1V8, one end of the capacitor C823 is connected to the voltage source VCC1V8, one end of the capacitor C823 is grounded, pins 1, 3 and 4 are separated for outputting power warning signals of the three IR38060 power chips after level conversion, pin 5 is used to output the power warning signal of the IR38064 power chip after level conversion, and pins 6, 7 and 8 are respectively used to output the power warning signals of the three IRPS5401 power chips after level conversion; The main chip U1-48 is configured as follows: pin J12 is connected to pin 1 of the level conversion chip U81, pin K12 is connected to pin 3 of the level conversion chip U81, pin H11 is connected to pin 4 of the level conversion chip U81, pin J11 is connected to pin 5 of the level conversion chip U81, pin K10 is connected to pin 6 of the level conversion chip U81, pin K11 is connected to pin 7 of the level conversion chip U81, and pin H9 is connected to pin 8 of the level conversion chip U81.

4. A universal test system for the radio frequency industry according to claim 3, characterized in that: The power supply early warning circuit performs early warning including: Power warning signals are generated by 3 IRPS5401 power chips, 3 IR38060 power chips and 1 IR38064 power chip; The power warning signal is input to the main chip U1-48 after being converted by the level conversion chip U81; The main chip U1-48 analyzes and processes the received power warning signal. When the power input voltage exceeds or is lower than the first set range, the input voltage abnormality warning is triggered; when the power output voltage exceeds or is lower than the second set range, the output voltage abnormality warning is triggered; when the current is abnormal, it is fed back to trigger the current abnormality warning; when the power chip temperature is too high, the overheating warning is triggered.

5. A universal test system for the radio frequency industry according to claim 1, characterized in that: The first connecting component includes a first socket and a plurality of first studs, the second connecting component includes a second socket and a plurality of second studs, the third connecting component includes a plurality of third studs, the test board is connected to the core board via the first socket and the plurality of first studs, the core board is connected to the data board via the second socket and the plurality of second studs, and the test board is connected to the data board via the plurality of third studs.

6. A universal test system for the radio frequency industry according to claim 1, characterized in that: All peripheral circuits include Dual QSPI circuit, PL-side DDR4 circuit, UART circuit, system clock circuit, PS-side DDR4 circuit, system status indicator circuit and system I2C0 circuit.

7. According to the universal test system for the radio frequency industry as claimed in claim 1, the plurality of peripheral preset interfaces include: PL serial port, PS serial port, USB3.0 interface, SD card storage interface, network port and optical fiber interface.

8. A universal test system for the radio frequency industry according to claim 1, characterized in that: The model of the main chip is XCZU27DR-FFVE-1156-2-I.

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