Method, system, device and medium for real-time monitoring of internal processes of embedded chips

Abstract

The present application discloses a method and system, device, and medium for real-time monitoring of the internal process of an embedded chip; it relates to the field of chip internal monitoring technology. The method includes: when the operation process is carried out inside the embedded chip, the embedded chip uses a unique identifier to mark each operation step in order according to the execution sequence of the operation steps in the operation process; the unique identifier is packaged and processed, and the obtained process identification data packet is transmitted to the signal parser; the signal parser receives the process identification data packet, restores the operation steps according to the preset mapping table and the process identification data packet, and displays the operation steps according to the execution sequence; wherein the preset mapping table is used to indicate the correspondence between the unique identifier and the operation step. It can monitor the internal operation of the embedded chip in real time and visualize the internal operation, intuitively view the internal operation of the embedded chip, and directly and conveniently locate the fault when a fault occurs, thereby improving the fault diagnosis efficiency of complex processes.

Description

Technical Field

[0001] The present application relates to the field of chip internal monitoring technology, and in particular to a method, system, device, and medium for real-time monitoring of the internal process of an embedded chip. Background Art

[0002] With the rapid development of information technology, embedded systems have penetrated into every aspect of our lives. As an important component of embedded systems, the performance and reliability of embedded chips directly affect the operation of the entire system. As a high-performance embedded flash memory solution, embedded chips have been widely used in mobile devices, embedded systems and other fields with their advantages such as high capacity, high-speed reading and writing, and low power consumption. However, with the continuous advancement of technology and the diversification of application scenarios, the internal working mechanism of embedded chips has become increasingly complex. This makes it extremely difficult to locate the problem and take effective measures to repair it in practical applications once the embedded chip fails or its performance degrades. And because the working status inside the embedded chip is difficult to directly observe, this further increases the difficulty of fault diagnosis.

[0003] Traditional methods for fault detection and performance evaluation of embedded chips usually rely on manual experience and simple test tools. Traditional methods are inadequate when dealing with the complex internal workflow of embedded chips. In addition, the existing technology only calculates the life information of NAND FLASH by monitoring the amount of I / O erase and write data, and can only infer the working conditions of the embedded chip from the outside; it is difficult to effectively monitor the internal behavior of the embedded chip. Therefore, how to effectively monitor the internal behavior of the embedded chip has become a problem that needs to be solved urgently. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method, system, device, and medium for real-time monitoring of the internal process of an embedded chip, which can monitor the internal operation of the embedded chip in real time and visualize the internal operation, intuitively view the internal operation of the embedded chip, and directly and conveniently locate the fault when a fault occurs, thereby improving the fault diagnosis efficiency of complex processes.

[0005] In a first aspect, an embodiment of the present application provides a method for real-time monitoring of an internal process of an embedded chip, which is applied to a system for real-time monitoring of an internal process of an embedded chip, the system comprising: an embedded chip and a signal analyzer that are sequentially communicatively connected;

[0006] The method comprises:

[0007] When the operation process is performed inside the embedded chip, the embedded chip uses a unique identifier to mark each operation step in order according to the execution sequence of the operation steps in the operation process; the unique identifier is packaged and the obtained process identification data packet is transmitted to the signal parser;

[0008] The signal parser receives the process identification data packet, restores the operation steps according to a preset mapping table and the process identification data packet, and displays the operation steps according to the execution sequence; wherein the preset mapping table is used to indicate the correspondence between the unique identifier and the operation steps.

[0009] According to some embodiments of the present application, the GPIO interface of the embedded chip is connected to the signal input end of the signal analyzer, and the GPIO interface is multiplexed as a signal output port;

[0010] The step of packaging the unique identifier and transmitting the obtained process identification data packet to the signal parser includes:

[0011] Performing a cyclic redundancy check on the generated unique identifier to obtain a first check code of the unique identifier;

[0012] Perform data packet generation processing according to the unique identifier and the first check code to obtain the process identification data packet; the process identification data packet includes a data frame;

[0013] The process identification data packet is transmitted to a signal parser through the signal output port.

[0014] According to some embodiments of the present application, the step of performing data packet generation processing according to the unique identifier and the first check code to obtain the process identification data packet includes:

[0015] According to a preset frame format, frame data generation processing is performed on the flag value of the unique identifier and the first check code to obtain a data frame; wherein the preset frame format includes: a start bit, a data bit, a CRC check code and an end bit;

[0016] The data frame is packaged to obtain the process identification data packet.

[0017] According to some embodiments of the present application, the step of restoring the operation steps according to the preset mapping table and the process identification data packet includes:

[0018] The signal parser obtains the data frame from the received process identification data packet;

[0019] Parsing the data frame to obtain the flag value of the unique identifier and the first check code;

[0020] Performing a flag value verification process according to the flag value of the unique identifier and the first verification code to obtain a flag value verification result;

[0021] When the flag value verification result is that the flag value of the unique identifier is transmitted correctly, the operation steps corresponding to the flag value of the unique identifier are determined according to the preset mapping table.

[0022] According to some embodiments of the present application, performing flag value verification processing according to the flag value of the unique identifier and the first verification code to obtain a flag value verification result includes:

[0023] Performing a cyclic redundancy check on the flag value of the unique identifier to obtain a second check code of the unique identifier;

[0024] When the first check code is consistent with the second check code, determining the flag value check result is: the flag value of the unique identifier is transmitted correctly;

[0025] When the first check code is inconsistent with the second check code, it is determined that the flag value check result is: a flag value transmission error of the unique identifier.

[0026] According to some embodiments of the present application, when the operation process is a data reading process, the unique identifier includes a first flag, a second flag, a third flag, a fourth flag, and a fifth flag, all of which have different flag values;

[0027] When the operation flow is a data reading flow, the embedded chip uses a unique identifier to mark each of the operation steps in order according to the execution timing of the operation steps in the operation flow, including:

[0028] When executing the first step of receiving a read data command, generating the first flag to mark the first step;

[0029] When the second step of acquiring the data to be read by the vehicle transport function is executed in response to the read data command, the second flag is generated to mark the second step;

[0030] When executing the third step of caching the to-be-read data into the storage unit, generating the third flag to mark the third step;

[0031] When the fourth step of transmitting the to-be-read data to the host through the DMA unit is executed, generating the fourth flag to mark the fourth step;

[0032] When the fifth step of finishing the transmission of the to-be-read data is executed, the fifth flag is generated to mark the fifth step.

[0033] According to some embodiments of the present application, when the operation process is a data writing process, the unique identifier includes a sixth flag, a seventh flag, an eighth flag, a ninth flag, and a tenth flag, all of which have different flag values;

[0034] When the operation process is a data writing process, the embedded chip uses a unique identifier to mark each of the operation steps in order according to the execution sequence of the operation steps in the operation process, including:

[0035] When executing the sixth step of receiving the write data command, generating the sixth flag to mark the sixth step;

[0036] When the seventh step of receiving the data to be written is executed in response to the write data command, the seventh flag is generated to mark the seventh step;

[0037] When the eighth step of caching the to-be-written data into the storage unit is executed, generating the eighth flag to mark the eighth step;

[0038] When the ninth step of writing the data to be written by the vehicle transport function is executed, the ninth flag is generated to mark the ninth step;

[0039] When the tenth step of finishing writing the data to be written is executed, the tenth flag is generated to mark the tenth step.

[0040] In a second aspect, an embodiment of the present application provides a system for real-time monitoring of an internal process of an embedded chip, the system comprising: an embedded chip and a signal analyzer that are sequentially communicatively connected;

[0041] The embedded chip is used to: when the operation process is performed inside the embedded chip, use a unique identifier to mark each operation step in order according to the execution sequence of the operation steps in the operation process; package the unique identifier and transmit the obtained process identification data packet to the signal parser;

[0042] The signal parser is used to: receive the process identification data packet, restore the operation steps according to a preset mapping table and the process identification data packet, and display the operation steps according to the execution sequence; wherein the preset mapping table is used to indicate the correspondence between the unique identifier and the operation steps.

[0043] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for real-time monitoring of the internal process of an embedded chip as described in the first aspect is implemented.

[0044] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to implement the method for real-time monitoring of the internal process of an embedded chip as described in the first aspect when executed by a processor.

[0045] The embodiment of the present application includes: a system for real-time monitoring of the internal process of an embedded chip includes: an embedded chip and a signal parser that are sequentially connected in communication; when the system for real-time monitoring of the internal process of an embedded chip is used to monitor the internal process of the embedded chip, first, when the operation process is performed inside the embedded chip, the embedded chip uses a unique identifier to mark each operation step in order according to the execution sequence of the operation steps in the operation process; the unique identifier is packaged and processed, and the obtained process identification data packet is transmitted to the signal parser; the internal operation of the embedded chip can be monitored in real time, and a reliable reference can be provided for the subsequent visualization of the internal operation of the embedded chip; the signal parser receives the process identification data packet, restores the operation steps according to the preset mapping table and the process identification data packet, and displays the operation steps according to the execution sequence; wherein the preset mapping table is used to indicate the correspondence between the unique identifier and the operation step; thereby, the internal operation of the embedded chip can be intuitively viewed, which is convenient for directly and conveniently locating the fault and improving the fault diagnosis efficiency of the complex process. That is to say, the present application can monitor the internal operation of the embedded chip in real time and visualize the internal operation, intuitively view the internal operation of the embedded chip, and directly and conveniently locate the fault when executing the fault, thereby improving the fault diagnosis efficiency of the complex process.

[0046] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a schematic diagram of the overall structure of a system for real-time monitoring of the internal process of an embedded chip provided by an embodiment of the present application;

[0048] Figure 2 It is a schematic diagram of the internal structure of an embedded chip provided by an embodiment of the present application;

[0049] Figure 3 It is a flowchart of a method for real-time monitoring of an internal process of an embedded chip provided by an embodiment of the present application;

[0050] Figure 4 It is a schematic diagram of a processing process of reading a data flow in a system for real-time monitoring of an internal process of an embedded chip provided by an embodiment of the present application;

[0051] Figure 5 It is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0053] It should be understood that in the description of the present application, the orientation descriptions, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0054] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0056] First, some terms used in this application are explained:

[0057] EMMC (Embedded MultiMediaCard) is an embedded multimedia card. EMMC uses a unified MMC standard interface to package high-density NAND-Flash (a type of Flash memory, which uses a nonlinear macro unit mode inside, providing a cheap and effective solution for the implementation of solid-state large-capacity memory) memory and MMC-Controller (multimedia controller) into a BGA (Ball Grid Array, solder ball array package) chip.

[0058] DMA (Direct Memory Access) is a functional module provided by some computer bus architectures that enables data to be sent directly from an attached device (such as a disk drive) to the computer motherboard's memory.

[0059] GPIO (General Purpose Input / Output) interface is used for digital signal interaction between embedded systems and external devices.

[0060] The present application provides a method for real-time monitoring of the internal process of an embedded chip, a device for real-time monitoring of the internal process of an embedded chip, an electronic device and a computer-readable storage medium, and relates to the field of chip internal monitoring technology. The method includes: when the operation process is carried out inside the embedded chip, the embedded chip uses a unique identifier to mark each operation step in order according to the execution sequence of the operation steps in the operation process; the unique identifier is packaged and processed, and the obtained process identification data packet is transmitted to the signal parser; the signal parser receives the process identification data packet, restores the operation steps according to the preset mapping table and the process identification data packet, and displays the operation steps according to the execution sequence; wherein the preset mapping table is used to indicate the correspondence between the unique identifier and the operation step. It can monitor the internal operation of the embedded chip in real time and visualize the internal operation, intuitively view the internal operation of the embedded chip, and directly and conveniently locate the fault when the execution fails, thereby improving the fault diagnosis efficiency of complex processes.

[0061] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0062] like Figure 1 As shown, the system for real-time monitoring of the internal process of the embedded chip includes: an embedded chip and a signal analyzer which are sequentially connected in communication.

[0063] Among them, the embedded chip is used to: when the operation process is carried out inside the embedded chip, each operation step is marked in order with a unique identifier according to the execution sequence of the operation steps in the operation process; the unique identifier is packaged and the obtained process identification data packet is transmitted to the signal parser. It can monitor the internal operation of the embedded chip in real time and provide a reliable reference for the subsequent visualization of the internal operation of the embedded chip.

[0064] The signal analyzer is used to: receive the process identification data packet, restore the operation steps according to the preset mapping table and the process identification data packet, and display the operation steps according to the execution sequence; wherein the preset mapping table is used to indicate the correspondence between the unique identifier and the operation steps. This enables intuitive viewing of the internal operation of the embedded chip, facilitates direct and convenient fault location, and improves the fault diagnosis efficiency of complex processes.

[0065] It is understandable that the embedded chip provided in the embodiment of the present application refers to any micro embedded chip with input and output capabilities. Specifically, the embedded chip may be an EMMC chip or other types of chips.

[0066] Specifically, the GPIO interface of the embedded chip is connected to the signal input end of the signal analyzer, and the GPIO interface is multiplexed as a signal output port.

[0067] Specifically, a private communication protocol is used for data transmission between the embedded chip and the signal analyzer, ensuring the accuracy and security of the transmitted information.

[0068] like Figure 2 As shown, the embedded chip also includes: a marking module and a data transmission module which are sequentially connected in communication. Specifically, the signal analyzer also includes a signal processing module and a display module which are sequentially connected in communication.

[0069] Specifically, the marking module is used to: when the operation process is carried out inside the embedded chip, each operation step is marked in order using a unique identifier according to the execution timing of the operation steps in the operation process. The operation steps of the internal operation process of the embedded chip can be monitored in real time and marked step by step, laying the foundation for the subsequent restoration of each operation step based on the unique identifier in the external signal parser. Specifically, the marking module uses a special unique identifier to mark each operation step of the internal operation process of the embedded chip. In one embodiment, the length of the unique identifier set at the key process node of the embedded chip is 4 bytes.

[0070] The data transmission module is used to: after the marking module completes the marking, when it is necessary to analyze the internal behavior of the embedded chip, send the identifier data to the external signal parser in real time. Specifically, the unique identifier is packaged and the obtained process identification data packet is transmitted to the signal parser through the signal output port. In this way, the unique identifier is transmitted to the signal parser more quickly, so that each operation step can be restored in time based on the unique identifier in the signal parser, and the fault diagnosis efficiency of complex processes is improved. Specifically, the data transmission module can transmit the unique identifier generated by the marking module to the external signal parser through the signal line.

[0071] The signal processing module is used to: receive a process identification data packet, and restore the operation steps according to a preset mapping table and the process identification data packet. Specifically, after performing a CRC check on the data frame of the received process identification data packet, when the flag value check result shows that the flag value of the unique identifier is correctly transmitted, the flag value of the unique identifier is extracted, and the internal workflow is displayed on the display module according to the preset meaning.

[0072] The display module is used to: after restoring the operation steps according to the preset mapping table and the process identification data packet, display the operation steps according to the execution sequence, so that the operator can intuitively view the execution sequence and execution status of the internal process of the embedded chip. Specifically, the display module includes a screen.

[0073] It is understandable that traditional fault detection and performance evaluation methods usually rely on manual experience and simple test tools, which are inadequate when dealing with complex internal workflows. This application uses the embedded chip's tag module for real-time monitoring and visualizes the embedded chip's internal workflow through a signal analyzer, simplifying the process of analyzing internal execution problems of the embedded chip.

[0074] It is understandable that the system for real-time monitoring of the internal process of the embedded chip provided by the embodiment of the present application, by correspondingly setting a unique identifier for each key node of the internal workflow of the embedded chip, different unique identifiers are used to identify different workflows and / or different stages in the process. When the internal work of the embedded chip runs to the corresponding stage, the embedded chip outputs the data signal of the corresponding unique identifier to the outside through the GPIO interface. By using a signal parser outside the embedded chip, the received data signal is parsed, and the corresponding relationship between the unique identifier and the operation steps is converted into operation steps, and the operation steps are displayed on the screen in an intuitive and readable manner. And a private communication protocol is used when transmitting signals between the embedded chip and the signal parser to ensure the accuracy of data transmission.

[0075] Therefore, through the system for real-time monitoring of the internal process of an embedded chip provided by the embodiment of the present application, the embedded chip and the signal analyzer cooperate with each other to execute the method of real-time monitoring of the internal process of the embedded chip, which can monitor the internal operation of the embedded chip in real time and visualize the internal operation, intuitively view the internal operation status of the embedded chip, and directly and conveniently locate the fault when an execution fault occurs, thereby improving the fault diagnosis efficiency of complex processes.

[0076] Those skilled in the art will appreciate that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0077] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0078] Those skilled in the art will appreciate that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0079] Based on the above system structure, various embodiments of the method for real-time monitoring of the internal process of an embedded chip of the present application are proposed below.

[0080] First, as Figure 3 As shown, the method for real-time monitoring of the internal process of an embedded chip can be applied to Figure 1 The system for real-time monitoring of the internal process of an embedded chip shown includes: an embedded chip and a signal analyzer that are sequentially connected in communication. The method for real-time monitoring of the internal process of an embedded chip may include but is not limited to steps S110 to S120.

[0081] Step S110: When the operation process is performed inside the embedded chip, the embedded chip uses a unique identifier to mark each operation step in order according to the execution sequence of the operation steps in the operation process; the unique identifier is packaged and the obtained process identification data packet is transmitted to the signal parser.

[0082] Step S120: The signal analyzer receives the process identification data packet, restores the operation steps according to the preset mapping table and the process identification data packet, and displays the operation steps according to the execution sequence; wherein the preset mapping table is used to indicate the correspondence between the unique identifier and the operation steps.

[0083] It is understandable that the prior art only calculates the life information of NAND FLASH by monitoring the amount of I / O erase and write data, and can only infer the working condition of the embedded chip from the outside. The present application goes a step further on this basis, and can not only monitor the erase and write data, but also monitor the internal process of the embedded chip, so as to provide real-time feedback on whether the embedded chip is working abnormally.

[0084] When the internal process of the embedded chip is monitored through steps S110 to S120, first, when the operation process is carried out inside the embedded chip, the embedded chip uses a unique identifier to mark each operation step in order according to the execution sequence of the operation steps in the operation process; the unique identifier is packaged and processed, and the obtained process identification data packet is transmitted to the signal parser; it can monitor the internal operation of the embedded chip in real time, and provide a reliable reference for the subsequent visualization of the internal operation of the embedded chip; the signal parser receives the process identification data packet, restores the operation steps according to the preset mapping table and the process identification data packet, and displays the operation steps according to the execution sequence; wherein the preset mapping table is used to indicate the correspondence between the unique identifier and the operation step; thereby, the internal operation of the embedded chip can be intuitively viewed, which is convenient for directly and conveniently locating faults and improving the fault diagnosis efficiency of complex processes. Therefore, the present application can monitor the internal operation of the embedded chip in real time and visualize the internal operation, intuitively view the internal operation of the embedded chip, and directly and conveniently locate the fault when executing a fault, thereby improving the fault diagnosis efficiency of complex processes.

[0085] It should be noted that the operation process inside the embedded chip includes but is not limited to: a data reading process and a data writing process.

[0086] According to some embodiments of the present application, when the operation process is a data reading process, the unique identifier includes a first flag, a second flag, a third flag, a fourth flag, and a fifth flag whose flag values ​​are all different. When the operation process is a data reading process, step S110 is further described. Among them, the embedded chip uses a unique identifier to mark each operation step in order according to the execution timing of the operation steps in the operation process, including but not limited to steps S210 to S250.

[0087] Step S210: When executing the first step of receiving a read data command, a first flag is generated to mark the first step.

[0088] Step S220: When the second step of acquiring the data to be read through the vehicle transport function is executed in response to the read data command, a second flag is generated to mark the second step.

[0089] Step S230: when the third step of caching the to-be-read data in the storage unit is executed, a third flag is generated to mark the third step.

[0090] Step S240: when the fourth step of transmitting the to-be-read data to the host through the DMA unit is executed, a fourth flag is generated to mark the fourth step.

[0091] Step S250: When the fifth step of completing the transmission of the data to be read is executed, a fifth flag is generated to mark the fifth step.

[0092] It should be noted that the first flag, the second flag, the third flag, the fourth flag and the fifth flag are all unique identifiers with a length of 4 bytes.

[0093] It should be noted that the flag values ​​of the first flag, the second flag, the third flag, the fourth flag, and the fifth flag can be successively increasing or decreasing; they can also be customized; but the values ​​are different from each other. Therefore, this application does not make specific restrictions on the flag values ​​of the first flag, the second flag, the third flag, the fourth flag, and the fifth flag.

[0094] Through steps S210 to S250, the data reading process inside the embedded chip can be monitored in real time, and each operation step in the data reading process is marked with a unique identifier, so that the data reading process inside the embedded chip can be restored and displayed based on the unique identifier in an external signal parser.

[0095] Specifically, an example is given to illustrate the specific process of real-time monitoring and marking of the data reading process provided by the embodiment of the present application. First, when the embedded chip receives the data reading command sent by the host, the marking module generates a 1001 mark; then, when the embedded chip calls the vehicle transport function to prepare the host's data to be read, the marking module generates a 1002 mark; then, when the data is prepared to the storage unit through the vehicle transport function, the marking module generates a 1003 mark; then, when the embedded chip uses the DMA module to transfer data to the outside, the marking module generates a 1004 mark; finally, when the data to be read is transmitted, the marking module system generates a 1005 mark.

[0096] According to some embodiments of the present application, when the operation process is a data writing process, the unique identifier includes a sixth flag, a seventh flag, an eighth flag, a ninth flag, and a tenth flag whose flag values ​​are all different; when the operation process is a data writing process, step S110 is further described. The embedded chip uses a unique identifier to mark each operation step in order according to the execution timing of the operation steps in the operation process, including but not limited to steps S310 to S350.

[0097] Step S310: When the sixth step of receiving the write data command is executed, a sixth flag is generated to mark the sixth step.

[0098] Step S320: When the seventh step of receiving the data to be written is executed in response to the write data command, a seventh flag is generated to mark the seventh step.

[0099] Step S330: when the eighth step of caching the data to be written into the storage unit is executed, an eighth flag is generated to mark the eighth step.

[0100] Step S340: When the ninth step of writing the data to be written through the vehicle transport function is executed, a ninth flag is generated to mark the ninth step.

[0101] Step S350: When the tenth step of writing the data to be written is finished, a tenth flag is generated to mark the tenth step.

[0102] It should be noted that the sixth flag, the seventh flag, the eighth flag, the ninth flag and the tenth flag are all unique identifiers with a length of 4 bytes.

[0103] It should be noted that the flag values ​​of the sixth flag, the seventh flag, the eighth flag, the ninth flag, and the tenth flag can be successively increasing or decreasing; they can also be customized; but the values ​​are different from each other. Therefore, this application does not make specific restrictions on the flag values ​​of the sixth flag, the seventh flag, the eighth flag, the ninth flag, and the tenth flag.

[0104] Through steps S310 to S350, the data writing process inside the embedded chip can be monitored in real time, and each operation step in the data writing process can be marked with a unique identifier, so that the data writing process inside the embedded chip can be restored and displayed based on the unique identifier in an external signal parser.

[0105] Specifically, an example is given to illustrate the specific process of real-time monitoring and marking of the data writing process provided by the embodiment of the present application. First, when the embedded chip receives the data writing command sent by the host, the marking module generates a 2001 mark; then, when the embedded chip stores the received data to be written into the storage unit, the marking module generates a 2002 mark; then, when the embedded chip calls the vehicle transport function to write the incoming data to be written from the host, the marking module generates a 2003 mark; then, when the data to be written is written, the marking module generates a 2004 mark; finally, when the data to be written is written, the marking module generates a 2005 mark.

[0106] It should be noted that the present application only gives an example of how to monitor and mark the read data flow and write data flow in an embedded chip in real time. Referring to the same processing method as above, the present application can monitor more complex internal operation processes in an embedded chip in real time.

[0107] In one embodiment, the unique identifier is also used to mark: the current hardware status of the embedded chip, such as voltage value, temperature value, etc.

[0108] According to some embodiments of the present application, the GPIO interface of the embedded chip is connected to the signal input end of the signal parser, and the GPIO interface is multiplexed as a signal output port. Further explanation of step S110, wherein the unique identifier is packaged and the obtained process identification data packet is transmitted to the signal parser, including but not limited to steps S410 to S430.

[0109] Step S410: Perform a cyclic redundancy check on the generated unique identifier to obtain a first check code of the unique identifier.

[0110] Step S420: performing data packet generation processing according to the unique identifier and the first check code to obtain a process identification data packet; the process identification data packet includes a data frame.

[0111] Step S430: Transmitting the process identification data packet to the signal analyzer through the signal output port.

[0112] Specifically, the cyclic redundancy check algorithm CRC3 is used in the cyclic redundancy check process in step S410 to detect whether errors occur during data transmission.

[0113] To further illustrate step S410, specifically, after each operation step is sequentially marked with a unique identifier, a CRC3 calculation is performed on the flag value of each unique identifier based on a cyclic redundancy check such as CRC3 through a data transmission module to obtain a first check code occupying 3 bytes; this first check code will be attached to the flag value of the corresponding unique identifier and transmitted together.

[0114] After the first check code of the unique identifier is calculated through step S410, step S420 is executed. According to some embodiments of the present application, step S420 is further described. Step S420: data packet generation processing is performed according to the unique identifier and the first check code to obtain a process identification data packet, including but not limited to: according to the preset frame format, the flag value of the unique identifier and the first check code are processed to generate frame data to obtain a data frame; wherein the preset frame format includes: a start bit, a data bit, a CRC check code and an end bit; the data frame is packaged to obtain a process identification data packet. Specifically, in the preset frame format, the data transmission module sets the start bit to 0 to identify the beginning of receiving data; and sets the end bit to 1 to identify the end of receiving data.

[0115] To further illustrate step S430, the GPIO interface of the embedded chip is multiplexed as a signal output port to output a process identification data packet, thereby saving hardware costs and improving the utilization rate of the GPIO interface.

[0116] The embodiment of the present application packages the unique identifier and the first check code into a process identification data packet based on a preset frame format through steps S410 to S430, so as to correctly and quickly transmit the process identification data packet from the embedded chip to the signal parser, thereby improving the efficiency and reliability of data transmission.

[0117] According to some embodiments of the present application, step S120 is further described, wherein the data packet restoration operation steps are performed according to a preset mapping table and a process identifier, including but not limited to steps S510 to S540.

[0118] Step S510: The signal analyzer obtains a data frame from the received process identification data packet.

[0119] Step S520: Parse the data frame to obtain the flag value and the first check code of the unique identifier.

[0120] Step S530: Perform flag value verification processing according to the flag value of the unique identifier and the first verification code to obtain a flag value verification result.

[0121] Step S540: When the flag value verification result shows that the flag value of the unique identifier is transmitted correctly, the operation steps corresponding to the flag value of the unique identifier are determined according to the preset mapping table.

[0122] It can be understood that, through steps S510 and S520, each received process identification data packet is parsed based on the preset frame format, and the flag value of each unique identifier and the corresponding first verification code can be obtained; so as to facilitate the subsequent verification of whether the data transmission is incorrect.

[0123] According to some embodiments of the present application, step S530 is further described. Step S530: performing flag value verification processing according to the flag value of the unique identifier and the first check code to obtain a flag value verification result, including but not limited to: performing cyclic redundancy check processing on the flag value of the unique identifier to obtain a second check code of the unique identifier; when the first check code is consistent with the second check code, determining that the flag value verification result is: the flag value of the unique identifier is transmitted correctly; when the first check code is inconsistent with the second check code, determining that the flag value verification result is: the flag value of the unique identifier is transmitted incorrectly.

[0124] Specifically, when the CRC3 cyclic redundancy check algorithm is used in the cyclic redundancy check process in step S410, the CRC3 cyclic redundancy check algorithm is also used in the cyclic redundancy check process in step S530. In step 530, CRC3 calculation is performed on the flag value of each unique identifier based on the CRC3 cyclic redundancy check to obtain a second check code occupying 3 bytes, which provides a reliable reference for determining whether the flag value of the unique identifier is transmitted incorrectly.

[0125] Through step S540, when the flag value is transmitted correctly, the operation steps corresponding to the flag value of the unique identifier are determined according to the preset mapping table, and then the operation steps are displayed on the display module to intuitively view the internal operation status of the embedded chip.

[0126] Through steps S510 to S540, the data frame of the process identification data packet is received and processed by the signal parser, and a CRC check is first performed. After ensuring that the data transmission is correct, the flag values ​​extracted from the data frame are arranged in the order of execution of the corresponding steps. The operation steps corresponding to each flag value are determined more quickly through a preset mapping table, so that the operation steps can be displayed according to the actual execution timing of the operation steps and displayed on the display module, thereby achieving the effect of real-time monitoring of the internal operation process of the embedded chip.

[0127] Combination Figure 4 , taking an example, a schematic diagram of the data processing flow of the system for real-time monitoring of the internal process of the embedded chip according to an embodiment of the present application is described when the internal operation process of the embedded chip is a data reading process.

[0128] First, in the marking module of the embedded chip, when the first step is executed, a first mark is generated to mark the first step; when the second step is executed, a second mark is generated to mark the second step; when the third step is executed, a third mark is generated to mark the third step; when the fourth step is executed, a fourth mark is generated to mark the fourth step; when the fifth step is executed, a fifth mark is generated to mark the fifth step.

[0129] Next, the data transmission module performs cyclic redundancy check processing and data packet generation processing based on each unique identifier to obtain each corresponding process identification data packet; and transmits the process identification data packet to the signal analyzer.

[0130] Then, the signal processing module of the signal parser performs signal analysis processing and cyclic redundancy check processing on each process identification data packet, and obtains the first flag, the second flag, the third flag, the fourth flag and the fifth flag in sequence; and restores the first step, the second step, the third step, the fourth step and the fifth step based on the preset mapping table.

[0131] Finally, based on the actual execution order of the operation steps, they are displayed in the display module from top to bottom as: the first step, the second step, the third step, the fourth step and the fifth step.

[0132] It can be understood that the present application monitors and visualizes the internal operation process of the embedded chip in real time. When an abnormality occurs in the internal operation process of the embedded chip, the specific steps where the problem occurs can be quickly located; and the fault diagnosis efficiency of the complex internal processes of the embedded chip can be significantly improved.

[0133] like Figure 5 As shown, Figure 5 Schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. The present invention also provides an electronic device, including:

[0134] The processor 501 may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0135] The memory 502 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 502 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 502, and the processor 501 calls and executes the method for real-time monitoring of the internal process of an embedded chip in the embodiment of this application;

[0136] Input / output interface 503, used to implement information input and output;

[0137] Communication interface 504, used to realize communication interaction between the present apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0138] A bus 505 that transmits information between various components of the device (e.g., the processor 501, the memory 502, the input / output interface 503, and the communication interface 504);

[0139] The processor 501 , the memory 502 , the input / output interface 503 and the communication interface 504 are connected to each other in communication within the device via a bus 505 .

[0140] The embodiment of the present application also provides a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by a processor, the method for real-time monitoring of the internal process of an embedded chip is implemented.

[0141] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0142] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0143] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims

1. A method for real-time monitoring of the internal process of an embedded chip, characterized in that: A system for real-time monitoring of the internal process of an embedded chip, the system comprising: an embedded chip and a signal analyzer connected in sequence for communication; The method comprises: When the operation process is performed inside the embedded chip, the embedded chip uses a unique identifier to mark each operation step in order according to the execution sequence of the operation steps in the operation process; the unique identifier is packaged and the obtained process identification data packet is transmitted to the signal parser; The signal parser receives the process identification data packet, restores the operation steps according to the preset mapping table and the process identification data packet, and displays the operation steps according to the execution sequence; wherein the preset mapping table is used to indicate the correspondence between the unique identifier and the operation steps; Wherein, the GPIO interface of the embedded chip is connected to the signal input end of the signal analyzer, and the GPIO interface is multiplexed as a signal output port; The step of packaging the unique identifier and transmitting the obtained process identification data packet to the signal parser includes: Performing a cyclic redundancy check on the generated unique identifier to obtain a first check code of the unique identifier; Perform data packet generation processing according to the unique identifier and the first check code to obtain the process identification data packet; the process identification data packet includes a data frame; The process identification data packet is transmitted to a signal parser through the signal output port.

2. The method for real-time monitoring of the internal process of an embedded chip according to claim 1, characterized in that: The step of performing data packet generation processing according to the unique identifier and the first check code to obtain the process identification data packet includes: According to a preset frame format, frame data generation processing is performed on the flag value of the unique identifier and the first check code to obtain a data frame; wherein the preset frame format includes: a start bit, a data bit, a CRC check code and an end bit; The data frame is packaged to obtain the process identification data packet.

3. The method for real-time monitoring of the internal process of an embedded chip according to claim 1, characterized in that: The step of restoring the operation steps according to the preset mapping table and the process identification data packet includes: The signal parser obtains the data frame from the received process identification data packet; Parsing the data frame to obtain the flag value of the unique identifier and the first check code; Performing a flag value verification process according to the flag value of the unique identifier and the first verification code to obtain a flag value verification result; When the flag value verification result is that the flag value of the unique identifier is transmitted correctly, the operation steps corresponding to the flag value of the unique identifier are determined according to the preset mapping table.

4. The method for real-time monitoring of the internal process of an embedded chip according to claim 3, characterized in that: The performing flag value verification processing according to the flag value of the unique identifier and the first verification code to obtain a flag value verification result includes: Performing a cyclic redundancy check on the flag value of the unique identifier to obtain a second check code of the unique identifier; When the first check code is consistent with the second check code, determining the flag value check result is: the flag value of the unique identifier is transmitted correctly; When the first check code is inconsistent with the second check code, it is determined that the flag value check result is: a flag value transmission error of the unique identifier.

5. The method for real-time monitoring of the internal process of an embedded chip according to claim 1, characterized in that: When the operation process is a data reading process, the unique identifier includes a first flag, a second flag, a third flag, a fourth flag, and a fifth flag, all of which have different flag values; When the operation flow is a data reading flow, the embedded chip uses a unique identifier to mark each of the operation steps in order according to the execution timing of the operation steps in the operation flow, including: When executing the first step of receiving a read data command, generating the first flag to mark the first step; When the second step of acquiring the data to be read by the vehicle transport function is executed in response to the read data command, the second flag is generated to mark the second step; When executing the third step of caching the to-be-read data into the storage unit, generating the third flag to mark the third step; When the fourth step of transmitting the to-be-read data to the host through the DMA unit is executed, generating the fourth flag to mark the fourth step; When the fifth step of finishing the transmission of the to-be-read data is executed, the fifth flag is generated to mark the fifth step.

6. The method for real-time monitoring of the internal process of an embedded chip according to claim 1, characterized in that: When the operation process is a data writing process, the unique identifier includes a sixth flag, a seventh flag, an eighth flag, a ninth flag, and a tenth flag, all of which have different flag values; When the operation process is a data writing process, the embedded chip uses a unique identifier to mark each of the operation steps in order according to the execution sequence of the operation steps in the operation process, including: When executing the sixth step of receiving the write data command, generating the sixth flag to mark the sixth step; When the seventh step of receiving the data to be written is executed in response to the write data command, the seventh flag is generated to mark the seventh step; When the eighth step of caching the to-be-written data into the storage unit is executed, generating the eighth flag to mark the eighth step; When the ninth step of writing the data to be written by the vehicle transport function is executed, the ninth flag is generated to mark the ninth step; When the tenth step of finishing writing the data to be written is executed, the tenth flag is generated to mark the tenth step.

7. A system for real-time monitoring of the internal process of an embedded chip, characterized in that: The system comprises: an embedded chip and a signal analyzer which are communicatively connected in sequence; The embedded chip is used to: when the operation process is performed inside the embedded chip, use a unique identifier to mark each operation step in order according to the execution sequence of the operation steps in the operation process; package the unique identifier and transmit the obtained process identification data packet to the signal parser; The signal parser is used to: receive the process identification data packet, restore the operation steps according to the preset mapping table and the process identification data packet, and display the operation steps according to the execution sequence; wherein the preset mapping table is used to indicate the corresponding relationship between the unique identifier and the operation steps; Wherein, the GPIO interface of the embedded chip is connected to the signal input end of the signal analyzer, and the GPIO interface is multiplexed as a signal output port; The packaging process of the unique identifier and transmitting the obtained process identification data packet to the signal parser includes: performing cyclic redundancy check processing on the generated unique identifier to obtain a first check code of the unique identifier; performing data packet generation processing based on the unique identifier and the first check code to obtain the process identification data packet; the process identification data packet includes a data frame; and transmitting the process identification data packet to the signal parser through the signal output port.

8. An electronic device, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method for real-time monitoring of the internal process of an embedded chip as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for real-time monitoring of an internal process of an embedded chip as claimed in any one of claims 1 to 6.

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