A memory, a memory device and a memory operation method

Abstract

The embodiments of the present disclosure provide a memory, a storage device and a method for operating the memory, wherein the memory comprises: a plurality of data storage blocks and a check code storage block; a data check circuit configured to respectively obtain storage data and corresponding first check codes from the plurality of data storage blocks and the check code storage block, and determine whether to perform a data check operation in response to a received mode selection signal; the data check circuit is further configured to, when the mode selection signal indicates that the memory is in an on-chip check mode, perform data check on the storage data according to the first check code, and output the data-checked storage data as first read-out data, and when the mode selection signal indicates that the memory is in an off-chip check mode, directly output the storage data and the first check code as second read-out data.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a memory, a storage device, and a method for operating the memory. Background Art

[0002] With the rapid development of computer technology, the requirements for memory capacity and speed are constantly increasing. However, as memory capacity increases, the possibility of data errors also increases. In order to improve the reliability of data processing, ECC (Error Detection and Correction) verification technology is widely used in dynamic random access memory (DRAM). ECC verification detects and corrects a certain number of errors by encoding data, thereby reducing the failure rate of storage systems.

[0003] However, the implementation of the mainstream ECC verification scheme in storage devices on the market currently requires additional hardware circuit and algorithm support, which increases the production cost of DRAM storage devices. Summary of the invention

[0004] The embodiments of the present disclosure provide a memory, a storage device, and a method for operating the memory. In the first aspect, the embodiments of the present disclosure provide a memory, comprising: a plurality of data storage blocks and a check code storage block; a data check circuit, configured to obtain storage data and corresponding first check codes from the plurality of data storage blocks and the check code storage block, respectively, and determine whether to perform a data check operation in response to a received mode selection signal; the data check circuit is also configured to, when the mode selection signal indicates that the memory is in an on-chip check mode, perform data check on the storage data according to the first check code, and output the data-checked storage data as first read-out data, and when the mode selection signal indicates that the memory is in an off-chip check mode, directly output the storage data and the first check code as second read-out data; wherein the first check code in the second read-out data is used by an external memory controller to perform a data check operation on the storage data.

[0005] In some embodiments, the memory further includes: an input / output circuit configured to receive the mode selection signal, and when the mode selection signal indicates that the memory is in an on-chip verification mode, serialize the received first read data according to a first burst length to generate a plurality of first output data strings output to a plurality of data ports; and when the mode selection signal indicates that the memory is in an off-chip verification mode, serialize the received second read data according to a second burst length to generate a plurality of second output data strings output to a plurality of the data ports; wherein the first burst length is less than the second burst length.

[0006] In some embodiments, the first output data string includes a portion of the stored data output in series, and the second output data string includes a portion of the stored data output in series and a portion of the first check code.

[0007] In some embodiments, the input / output circuit is further configured to receive an extended function indication signal. When the mode selection signal indicates that the memory is in an off-chip verification mode and the extended function indication signal indicates that the memory has an extended function turned on, the received second read data and first extended data are serialized according to a third burst length to generate multiple third output data strings output to multiple data ports; wherein the third output data string includes a portion of the stored data, a portion of the first verification code and a portion of the first extended data that are serially output.

[0008] In some embodiments, the input / output circuit is further configured to, when the mode selection signal indicates that the memory is in the on-chip verification mode, generate first write data output to the data verification circuit after parallel processing of a first input data string of a first burst length received from each of the data ports, and to generate second write data output to the data verification circuit after parallel processing of a second input data string of a second burst length received from each of the data ports when the mode selection signal indicates that the memory is in the off-chip verification mode; wherein the first write data includes data to be stored, the second write data includes the data to be stored and a corresponding second verification code, the first input data string includes a serially input portion of the data to be stored, and the second input data string includes a serially input portion of the data to be stored and a portion of the second verification code.

[0009] In some embodiments, the data verification circuit is further configured to, when the mode selection signal indicates that the memory is in the on-chip verification mode, encode the data to be stored in the received first write data to generate a corresponding third verification code, and store the data to be stored and the third verification code in the multiple data storage blocks and the verification code storage blocks, respectively, and when the mode selection signal indicates that the memory is in the off-chip verification mode, store the data to be stored and the second verification code in the received second write data in the multiple data storage blocks and the verification code storage blocks, respectively.

[0010] In some embodiments, the input / output circuit is further configured to receive an extended function indication signal, and when the mode selection signal indicates that the memory is in an off-chip verification mode and the extended function indication signal indicates that the memory has an extended function turned on, the third input data string of the third burst length received from each of the data ports is processed in parallel to generate third write data output to the data verification circuit; wherein the third write data includes the data to be stored, the corresponding second verification code and the second extended data, and the third input data string includes part of the data to be stored, part of the second verification code and part of the second extended data input in series.

[0011] In some embodiments, the memory further includes: a data transmission circuit connected between the data verification circuit and the input / output circuit, the data transmission circuit being configured to transmit the first read data or the second read data from the data verification circuit to the input / output circuit, and to transmit the first write data or the second write data from the input / output circuit to the data verification circuit.

[0012] In some embodiments, the input / output circuit includes a data conversion circuit, and the data conversion circuit includes a plurality of data conversion sub-circuits corresponding to the plurality of data ports one by one; each of the data conversion sub-circuits includes a serializer and a deserializer; the serializer is coupled to the data transmission circuit and the corresponding data port, respectively, and is configured to, when the mode selection signal indicates that the memory is in the on-chip verification mode, serialize part of the storage data received from the data transmission circuit according to the first burst length, and generate the first output data string output to the corresponding data port; and when the mode selection signal indicates that the memory is in the off-chip verification mode, serialize part of the storage data received from the data transmission circuit according to the first burst length, and generate the first output data string output to the corresponding data port. The parallelizer is coupled to the data transmission circuit and the corresponding data port, respectively, and is configured to parallelize the first input data string received from the corresponding data port when the mode selection signal indicates that the memory is in the on-chip verification mode, and generate part of the first write data output to the data transmission circuit; and to parallelize the second input data string received from the corresponding data port when the mode selection signal indicates that the memory is in the off-chip verification mode, and generate part of the second write data output to the data transmission circuit.

[0013] In some embodiments, the input / output circuit also includes: a first-in-first-out register and a data driver; the first-in-first-out register is coupled between the data transmission circuit and the data conversion circuit, and is configured to receive and cache the first read data or the second read data from the data transmission circuit during a read operation performed by the memory, and to receive and cache the first write data or the second write data after parallel processing from the data conversion circuit during a write operation performed by the memory; the data driver is coupled between the data conversion circuit and the plurality of data ports, and is configured to receive the plurality of the first output data strings or the plurality of the second output data strings after serial processing from the data conversion circuit during a read operation performed by the memory, and drive the outputs to the plurality of the data ports, and to receive the corresponding plurality of the first input data strings or the plurality of the second input data strings through the plurality of the data ports during a write operation performed by the memory, and drive the outputs to the data conversion circuit.

[0014] In some embodiments, the data transmission circuit includes: a storage data transmission bus and a check code transmission bus; the storage data transmission bus is configured to transmit the storage data or the data to be stored; the check code transmission bus is configured to receive the mode selection signal and transmit the first check code or the second check code when the mode selection signal indicates that the memory is in an off-chip check mode, and is disabled when the mode selection signal indicates that the memory is in an on-chip check mode.

[0015] In some embodiments, the data transmission circuit also includes: an extended data bus; the extended data bus is configured to receive the mode selection signal and the extended function indication signal, and transmit the first extended data or the second extended data when the mode selection signal indicates that the memory is in an off-chip verification mode and the extended function indication signal indicates that the memory is in an extended function on state, otherwise the extended data bus is disabled.

[0016] In a second aspect, an embodiment of the present disclosure provides a storage device, comprising at least one storage channel, each of the storage channels comprising a plurality of memories as described in the first aspect.

[0017] In a third aspect, an embodiment of the present disclosure provides an operating method for a memory, wherein the memory includes multiple data storage blocks and a check code storage block, and the operating method includes: respectively acquiring storage data and corresponding first check codes from the multiple data storage blocks and the check code storage blocks; determining a check mode of the memory in response to a mode selection signal; when the mode selection signal indicates that the memory is in an on-chip check mode, performing data verification on the storage data according to the first check code, and outputting the verified storage data as first read-out data; or when the mode selection signal indicates that the memory is in an off-chip check mode, directly outputting the storage data and the first check code as second read-out data; wherein the first check code in the second read-out data is used by an external memory controller to perform a data verification operation on the storage data.

[0018] In some embodiments, the operating method also includes: serializing the first read data or the second read data and outputting the data from the memory through multiple data ports; wherein, when the memory is in the on-chip verification mode, the first read data is serialized according to a first burst length to generate multiple first output data strings output through multiple data ports; when the memory is in the off-chip verification mode, the second read data is serialized according to a second burst length to generate multiple second output data strings output through multiple data ports; the first burst length is less than the second burst length.

[0019] In some embodiments, after directly outputting the stored data and the first check code as second read data, the operating method also includes: determining whether an extended function of the memory is turned on; if the memory is in the off-chip check mode and the extended function is turned on, serializing the second read data and the first extended data according to a third burst length to generate multiple third output data strings output through multiple data ports; wherein the third output data string includes a portion of the stored data, a portion of the first check code, and a portion of the first extended data output in series.

[0020] In a fourth aspect, an embodiment of the present disclosure provides an operating method for a memory, the operating method comprising: determining a verification mode of the memory in response to a mode selection signal; when the mode selection signal indicates that the memory is in an on-chip verification mode, parallelizing a first input data string of a first burst length received from each data port to generate first write data; when the mode selection signal indicates that the memory is in an off-chip verification mode, parallelizing a second input data string of a second burst length received from each of the data ports to generate second write data; wherein the second burst length is greater than the first burst length, the first write data includes data to be stored, the second write data includes the data to be stored and a corresponding second verification code, the first input data string includes a serially input portion of the data to be stored, and the second input data string includes a serially input portion of the data to be stored and a portion of the second verification code.

[0021] In some embodiments, the memory includes multiple data storage blocks and verification code storage blocks, and the operating method also includes: when the memory is in the on-chip verification mode, encoding the data to be stored in the received first write data to generate a corresponding third verification code, and storing the data to be stored and the third verification code in the multiple data storage blocks and the verification code storage blocks respectively; when the memory is in the off-chip verification mode, storing the data to be stored in the received second write data and the second verification code in the multiple data storage blocks and the verification code storage blocks respectively.

[0022] In some embodiments, when the mode selection signal indicates that the memory is in the off-chip check mode, the operating method further includes: determining whether an extended function of the memory is turned on; if the memory is in the off-chip check mode and the extended function is turned on, parallelizing a third input data string of a third burst length received from each of the data ports to generate third write data; wherein the third write data includes the data to be stored, the corresponding second check code and second extended data, and the third input data string includes a serially input portion of the data to be stored, a portion of the second check code and a portion of the second extended data.

[0023] The embodiment of the present disclosure sets a data verification circuit that can select an on-chip verification mode and an off-chip verification mode in the memory, and can flexibly configure the verification mode to improve the utilization rate of on-chip storage resources and increase the diversity of data protection schemes, wherein, when the error risk of the storage cell array of the memory chip is higher, the on-chip verification mode can be configured to use the on-chip stored verification code to detect and correct the data errors that occur during the data storage process on the memory chip, and when the error risk of the data transmission link in the storage system is higher, the off-chip verification mode can be configured to send the on-chip stored verification code and the storage data directly to the external memory controller, so that the memory controller can use the verification code to detect and correct the data errors that occur in the complete data transmission link of the storage system. In this way, the memory provided by the embodiment of the present disclosure can be compatible with the data verification function executed on the memory chip and the off-chip data verification function executed by the controller by using the same verification code storage block, thereby improving the utilization rate of the on-chip verification code storage block resources and saving the additional storage resource consumption caused by adopting other ECC schemes for error detection and correction of the entire data transmission link. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1A-1B A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0026] Figure 2A-2H A schematic diagram of the structure of another memory provided by an embodiment of the present disclosure;

[0027] Figure 3A-3D A schematic diagram of the configuration of the input data string / output data string used in the embodiment of the present disclosure;

[0028] Figure 4A-4B A schematic diagram of the structure of another memory provided by an embodiment of the present disclosure;

[0029] Figure 5 A schematic diagram of the structure of an input / output circuit provided in an embodiment of the present disclosure;

[0030] Figure 6 A schematic diagram of the structure of a data conversion circuit provided by an embodiment of the present disclosure;

[0031] Figure 7A-7D A schematic diagram of the structure of a data conversion subcircuit and a data transmission circuit provided by an embodiment of the present disclosure;

[0032] Figure 8A-B A signal timing diagram corresponding to the data conversion sub-circuit provided in an embodiment of the present disclosure;

[0033] Fig. 9 A schematic diagram of the structure of a storage device provided in an embodiment of the present disclosure;

[0034] Fig.10 A schematic diagram of a flow chart of a method for operating a memory provided by an embodiment of the present disclosure;

[0035] Fig.11 Another flowchart of a method for operating a memory provided by an embodiment of the present disclosure;

[0036] Fig.12 A flowchart of another memory operation method provided by an embodiment of the present disclosure;

[0037] Fig.13 Another flowchart of another memory operation method provided by the embodiment of the present disclosure; DETAILED DESCRIPTION

[0038] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0039] The terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar or similar objects or entities, and are not necessarily meant to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way are interchangeable under appropriate circumstances, for example, they can be implemented in an order other than those given in the diagrams or descriptions of the embodiments of the present disclosure.

[0040] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0041] It should be noted that the brief description of terms in the present disclosure is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of the present disclosure. Unless otherwise specified, these terms should be understood according to their common and usual meanings. In addition, the terms "including" and "having" and any variations thereof are intended to cover but not exclude inclusion. For example, a product or device containing a series of components is not necessarily limited to those components clearly listed, but may include other components that are not clearly listed or inherent to these products or devices.

[0042] In the related art, in order to improve the integrity of data and the reliability of the system, an error checking and correction (ECC) function is added to the memory. There are many ECC implementation methods used in current memory products, such as: On-Die ECC (on-chip ECC), Link ECC (link ECC), Side Band ECC (bypass ECC), etc. Although the above methods can provide data protection in the memory system, each method has its potential disadvantages: On-Die ECC requires the integration of ECC logic circuits inside the memory chip and the configuration of a storage array for verification data, which will increase the area of ​​the memory chip and additional costs, but On-Die ECC cannot provide any protection for data errors occurring on the data transmission link (the transmission link between the memory and the control and the data transmission path inside the memory), and needs to be combined with other ECC methods (such as: Link ECC and Side Band ECC) to achieve data protection for the entire data transmission link; Link ECC requires additional ECC processing on the data transmission link, which may increase the delay of data transmission and affect the overall performance of the system, and link ECC does not provide any protection for data errors occurring on the storage array; Side Band The ECC implementation solution requires adding additional memory particles to store ECC data, which will significantly increase the cost of storage system products.

[0043] In response to the above problems of the ECC scheme in the existing memory, an embodiment of the present disclosure provides a memory, including: multiple data storage blocks and check code storage blocks; a data check circuit, configured to respectively obtain storage data and corresponding first check codes from the multiple data storage blocks and the check code storage blocks, and determine whether to perform a data check operation in response to a received mode selection signal; the data check circuit is also configured to, when the mode selection signal indicates that the memory is in an on-chip check mode, perform data check on the storage data according to the first check code, and output the data-checked storage data as first read-out data, and when the mode selection signal indicates that the memory is in an off-chip check mode, directly output the storage data and the first check code as second read-out data; wherein the first check code in the second read-out data is used by an external memory controller to perform a data check operation on the storage data. In this way, by setting a data verification circuit that can select an on-chip verification mode and an off-chip verification mode in the memory, the verification mode can be flexibly configured to improve the utilization rate of on-chip storage resources and increase the diversity of data protection schemes, wherein, when the error risk of the storage cell array of the memory chip is higher, the on-chip verification mode can be configured to use the on-chip stored verification code to detect and correct data errors occurring in the data storage process on the memory chip, and when the error risk of the data transmission link in the storage system is higher, the off-chip verification mode can be configured to send the on-chip stored verification code and the stored data directly to the external memory controller, so that the memory controller can use the verification code to implement error detection and correction of data errors occurring in the complete data transmission link of the storage system. In this way, the memory provided by the embodiment of the present disclosure can be compatible with the data verification function executed on the memory chip and the off-chip data verification function executed by the controller by using the same verification code storage block, so that the on-chip verification code storage block resources can be used more efficiently, and the additional storage resource consumption caused by adopting other ECC schemes (for example: side band ECC) for error detection and correction of the entire data transmission link can be saved.

[0044] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0045] In one embodiment of the present disclosure, reference Figure 1A-1B , which shows a schematic diagram of the structure of a memory 100 provided by an embodiment of the present disclosure. Figure 1A-1BAs shown, the memory 100 includes: a plurality of data storage blocks 11 and a check code storage block 12; a data check circuit 20, configured to respectively obtain storage data DATA and a corresponding first check code ECC1 from the plurality of data storage blocks 11 and the check code storage block 12, and determine whether to perform a data check operation in response to a received mode selection signal; the data check circuit 20 is further configured to, when the mode selection signal indicates that the memory 100 is in an on-chip check mode, perform data check on the storage data DATA according to the first check code ECC1, and output the stored data DATA after data check as first read-out data R_Data1, and when the mode selection signal indicates that the memory 100 is in an off-chip check mode, directly output the storage data DATA and the first check code ECC1 as second read-out data R_Data2; wherein the first check code ECC1 in the second read-out data R_Data2 is used by an external memory controller to perform a data check operation on the storage data DATA (such as Figure 1B as shown).

[0046] When the mode selection signal is at a first level, it indicates that the memory 100 is in an on-chip verification mode, and when it is at a second level, it indicates that the memory 100 is in an off-chip verification mode. Here, the first level can be a high level (logic "1"), and the corresponding second level is a low level (logic "0"), or the first level can be a low level (logic "0"), and the corresponding second level is a high level (logic "1"), which is not specifically limited here.

[0047] like Figure 1A-1B As shown, the memory 100 includes: a storage area 10 and a peripheral circuit area. Among them, functional circuits such as a data check circuit 20 are all arranged in the peripheral circuit area, and the storage area 10 is used to store data. The storage area 10 may include multiple storage bodies Bank (not shown in the figure), each storage body may include multiple storage segments Section (not shown in the figure) obtained by segmentation in the bit line direction, each storage segment section includes multiple data storage blocks 11 and check code storage blocks 12, each storage segment also includes multiple sense amplifier arrays (not shown in the figure), the sense amplifier arrays are arranged between the storage blocks, and each storage block may include multiple storage cells.

[0048] Continue to refer Figure 1A-1B The memory 100 provided in the embodiment of the present disclosure is provided with a data verification circuit 20 that can select an on-chip verification mode and an off-chip verification mode. By configuring the data verification mode, the data verification circuit 20 can flexibly select how to use and transmit the first verification code ECC1 and the stored data DATA. Specifically, Figure 1AAs shown, when the mode selection signal indicates that the memory 100 is configured as the on-chip verification mode, the first verification code ECC1 is used to provide data protection for the internal data storage process of the memory, that is, the data verification circuit 20 will directly perform error detection and error correction on the stored data DATA according to the first verification code ECC1. At this time, the first verification code ECC1 has been used by the data verification circuit 20 and completes the data verification function, and does not need to be output. The data verification module 20 only outputs the stored data DATA after data verification as the first read-out data R_Data1; as shown in FIG. Figure 1B As shown, when the mode selection signal indicates that the memory 100 is in the off-chip verification mode, the first verification code ECC1 is used to provide data protection for the complete data transmission link of the storage system, that is, the data verification circuit 20 will no longer perform the on-chip data verification operation, but directly output the stored data DATA and the first verification code ECC1 as the second read data R_Data2. At this time, the output first verification code ECC1 will be received by the external memory controller to perform a data verification operation on the completed stored data DATA. In the disclosed embodiment, the memory realizes the use of the same verification code storage block resources to be compatible with the on-chip data verification function and the off-chip data verification function through the flexible configuration of the data verification mode of the data verification circuit, which can improve the utilization rate of the on-chip verification code storage resources, increase the diversity of data protection schemes, and save the extra storage resource consumption caused by the use of the off-chip data verification ECC scheme.

[0049] Among them, the number (bit width) of storage units in the check code storage block 12 and the data storage block 11 can be set to be the same or different. Specifically, according to the encoding method of data verification adopted in the storage system, the data ratio of the storage data DATA and the corresponding first check code ECC1 is determined, and then the number of storage units in the check code storage block 12 is selected. For example: the configuration of the DDR5 memory is data bus width X8, burst length (Burst Length, BL) 16, 8 data storage blocks are set in each data segment, and when the Hamming code is used as the data verification method, the pre-fetched storage data DATA is 8 (mat) * 16 (BL) = 128b, and the first check code that needs to be pre-fetched for the corresponding 128b storage data is 8b. At this time, the bit width of the check code storage block 12 can be set to half of the data storage block 1.

[0050] It should be noted that Figure 1A and Figure 1B The structures of the memories 100 shown are the same, and the present disclosure is only Figure 1A and Figure 1B The data interactions between the component circuits when the memory 100 performs read access operations in different verification modes are respectively shown.

[0051] In some embodiments of the present disclosure, the value of the mode selection signal is determined by the configuration parameters in the mode register of the memory, and the memory controller can modify the configuration parameters in the mode register of the memory through the mode register read / write command.

[0052] In some embodiments of the present disclosure, a plurality of check code storage blocks 12 may be provided in each storage segment of the memory, and the number of first check codes ECC1 may be increased to improve the error correction capability of the memory.

[0053] In some embodiments of the present disclosure, an improvement is made on the basis of the original on-die ECC circuit of the memory, and a selection function of the on-chip verification mode of the memory is added to obtain the data verification circuit of the present disclosure. When the on-chip verification mode is selected, the data verification circuit will enable the original on-die ECC circuit, and perform data verification (i.e., error detection and / or error correction) on the stored data Data according to the first verification code ECC1 obtained in the verification code storage block, and output the verified Data as the first read-out data R_Data1. When the off-chip verification mode is selected, the data verification circuit will disable the data verification function of the original on-die ECC circuit, that is, bypass the original on-die ECC circuit, and the data verification circuit will output the obtained storage data DATA and the first verification code ECC1 as the second read-out data R_Data2.

[0054] refer to Figure 2A-2C , which shows a schematic diagram of the structure of another memory provided by an embodiment of the present disclosure. Figure 2A As shown, the memory 100 further includes: an input / output circuit 40, configured to receive a mode selection signal, and when the mode selection signal indicates that the memory 100 is in an on-chip verification mode, after serializing the received first read data R_Data1 according to a first burst length BL1 (Burst Length 1), generate a plurality of first output data strings Out_s1 (such as 100) output to a plurality of data ports (DQ) 50. Figure 2A As shown), and when the mode selection signal indicates that the memory is in the off-chip verification mode, the received second read data R_Data2 is serialized according to the second burst length BL2 (Burst Length 2) to generate a plurality of second output data strings Out_s2 (as shown) output to the plurality of data ports 50. Figure 2B As shown); wherein, the first burst length BL1 is smaller than the second burst length BL2.

[0055] In the embodiment of the present disclosure, when the memory 100 is in the on-chip check mode and the off-chip check mode respectively, the amount of parallel data received by the input / output circuit 40 is different, and the number of data ports 50 in the memory 100 is pre-set and fixed. Therefore, without adding additional data port resources, after the input / output circuit 40 serializes the received parallel data, the amount of serial data (burst length BL) that needs to be transmitted through each data port 50 is also different. Specifically, take 128b storage data, 8b first check code data and 8 data ports (X8) as an example. In the on-chip check mode, if Figure 2A As shown, the first read data R_Data1 received by the input / output circuit 40 only includes the 128b storage data DATA after error detection and correction. The input / output circuit 40 only needs to serialize the 128b storage data DATA after error detection and correction to obtain 8 first output data strings Out_s1 corresponding to 8 data ports 50. The serial data length of each first output data string Out_s1 is 128 / 8=16, that is, the corresponding first burst length BL1 is 16. In the off-chip check mode, Figure 2B As shown, the second read data R_Data2 received by the input / output circuit 40 includes not only the 128b storage data DATA, but also the 8b first check code ECC1 that needs to be transmitted externally. After the input / output circuit 40 performs serial processing on the second read data R_Data2 (128b Data+8b ECC1), 8 second output data strings Out_s2 corresponding to the 8 data ports 50 are obtained. The serial data length of each second output data string Out_s2 is (128+8) / 8=17, that is, the corresponding second burst length BL2 is 17. Therefore, the memory 100 needs to additionally transmit the 8b first check code ECC1 through the 8 data ports 50 when in the off-chip check mode, that is, each data port 50 needs to additionally transmit 1b of data, and the second burst length BL2 of the second output data string Out_s2 corresponding to the data port 50 is greater than the first burst length BL1 corresponding to the first output data string Out_s1.

[0056] It should be noted that the input / output circuit 40 in the embodiment of the present disclosure is provided with at least two data processing modes with different burst lengths to respectively match the processing requirements of different data received in the two data verification modes (the first read data R_Data1 and the second read data R_Data2 with different data amounts output by the data verification circuit 20).

[0057] In one embodiment of the present disclosure, reference Figure 2A-2B and Figure 3AThe first output data string Out_s1 includes a portion of the stored data DATA output in series, and the second output data string Out_s2 includes a portion of the stored data DATA output in series and a portion of the first check code ECC1.

[0058] It should be noted that the first burst length BL1 is related to the specification of the memory and the data bus bandwidth configuration, while the second burst length BL2 is set according to factors such as the first burst length BL1, the number of first check codes ECC1 that need to be additionally transmitted, and the data bus width. The second burst length BL2 can be set to just meet the transmission requirements of the first check code ECC1 to save the transmission time of serial data, or the second burst length BL2 can be set to be slightly larger than the transmission requirements of the first check code ECC1 to reserve additional positions in the second output data string Out_s2 to meet the transmission requirements of data of other extended functions. Specifically, the X4 / X8 / X16 / X32... configuration of the memory refers to the data bus width, which can also be understood as the number of data ports for parallel input / output of the memory. The burst length BL configuration of the memory refers to the number of data blocks transmitted continuously in one memory access, which can also be understood as the number of data continuously serially input / output for each data port in the memory. The burst length and data bus bandwidth of the memory jointly affect the data transmission efficiency and speed of the memory. Combined with Figure 2A-2C and Figure 3A , the data transmission of DDR5 performing read operation is described, such as Figure 3A As shown, the memory 100 is configured with a data bus width of X8 (ie, the memory 100 has 8 parallel input / output data ports 50), and a single read / write of the memory 100 requires the transmission of 128b of stored data; when the memory 100 is in the on-chip verification mode, as shown Figure 2A As shown, the first burst length BL1 = 128b / 8 (X8) = 16, all bits Out_s1<0:15> in the first output data string Out_s1 transmitted corresponding to each data port are used to transmit storage data; when the memory 100 is in the off-chip data verification mode, such as Figure 2BAs shown, the first check code ECC1 that needs to be additionally transmitted is 8 bits in total, and each data port 50 only needs to transmit 1 bit of data additionally. In theory, the burst length BL can be set to any value greater than or equal to 17, but because DDR5 adopts double-edge data sampling, an odd burst length is not conducive to data transmission between the memory and the controller, and the burst length BL needs to be set to an even number. Therefore, the second burst length BL2 is correspondingly set to 18. At this time, the first 16 bits Out_s2<0:15> of the second output data string Out_s2 corresponding to each data port are used to transmit the storage data DATA, and the 17th bit BL2 <16> Used to transmit the first check code ECC1, the 18th bit BL2 <17> It is used to transmit the extended data RFU corresponding to other extended functions. It should be noted here that for memory products of other specifications, such as DDR4 chips, under the same circumstances, the second burst length BL2 corresponding to the second output data string Out_s2 can be set to 17. At this time, the second output data string Out_s2<0:16> only includes: part of the stored data DATA and part of the first check code ECC1.

[0059] Continue to refer Figure 3C-Figure 3D , which shows a schematic diagram of two input / output data configurations provided by an embodiment of the present disclosure. Among them, when the memory 100 is configured with a data bus width of X4, a single read / write access requires the transmission of 64b of storage data, which is half the storage data transmitted in the X8 configuration. When the memory 100 is in the on-chip verification mode, the first burst length BL1 = 64b / 4 (X4) = 16. Similar to the X8 configuration, all bits Out_s1<0:15> in the first output data string Out_s1 corresponding to each data port are used to transmit storage data; while in the off-chip data verification mode, the storage data (2*64b storage data) of the two read / write accesses corresponds to the same 8b first verification code ECC1 data, that is, the first verification code ECC1 that needs to be additionally transmitted for the two read / write accesses is 8b in total, and the second burst length BL2 is correspondingly set to 18. At this time, there are two specific data configuration methods: the first configuration method, such as Figure 3C As shown, the 17th bit BL2 in the second output data string Out_s2 outputted for the first time is read <16> Used to transmit the 4b first check code ECC1 (ECC<0:3>), the 18th bit BL2 <17> Used to transmit the extended data (CRC<0:3>) corresponding to other extended functions of 4b. The 17th bit BL2 in the second output data string Out_s2 outputted for the second reading <16> Used to transmit another 4b of the first check code ECC1 (ECC<4:7>), the 18th bit BL2 <17> Used to transmit the extended data (CRC<4:7>) corresponding to the other extended functions of another 4B; the second configuration method, such as Figure 3DAs shown, the 17th-18th bit BL2<16:17> in the second output data string Out_s2 read out for the first time is used to transmit the 8b first check code ECC1 (ECC<0:7>), and the 17th-18th bit BL2<16:17> in the second output data string Out_s2 read out for the second time is used to transmit the extended data (CRC<0:7>) corresponding to the other extended functions of 8b. The specific sampling of the X4 data configuration mode can be configured according to the special bit (CA10) in the read command or the parameters in the mode register.

[0060] In one embodiment of the present disclosure, continue to refer to Figure 2C and Figure 3A The input / output circuit 40 is also configured to receive an extended function indication signal. When the mode selection signal indicates that the memory 100 is in an off-chip check mode and the extended function indication signal indicates that the memory 100 turns on the extended function, the received second read data R_Data2 and the first extended data RFU1 are serialized according to the third burst length BL3 to generate multiple third output data strings Out_s3 output to multiple data ports 50; wherein the third output data string Out_s3 includes a portion of the serially output storage data DATA, a portion of the first check code ECC1 and a portion of the first extended data RFU1.

[0061] When the extended function indication signal is at the third level, it indicates that the extended function of the memory 100 is turned on, and when it is at the fourth level, it indicates that the extended function of the memory 100 is not turned on. Here, the third level can be a high level (logic "1"), and the corresponding fourth level is a low level (logic "0"), or the third level can be a low level (logic "0"), and the corresponding fourth level is a high level (logic "1"), which is not specifically limited here.

[0062] It should be noted that if Figure 2D and Figure 3B-Figure 3D As shown, the extended function may be a cyclic redundancy check (CRC) function, and the corresponding first extended data RFU1 may be cyclic redundancy check data CRC_code. Meanwhile, the extended function may also be other functions executed in the memory. The present disclosure only takes the CRC function as an example of the extended function, and does not constitute a limitation on the embodiments of the present disclosure.

[0063] like Figure 2D and Figure 3BAs shown, the input / output circuit 40 uses the second read data R_Data2 and the cyclic redundancy check data CRC_code (i.e., the first extended data), and the first 16 bits Out_s2<0:15> of the third output data string Out_s3 transmitted by each data port are used to transmit the storage data DATA, and the 17th bit BL2 <16> Used to transmit the first check code ECC1, the 18th bit BL2 <17> Used to transmit the cyclic redundancy check (CRC) data CRC_code corresponding to the cyclic redundancy check (CRC) function.

[0064] Here, the third burst length BL3 and the second burst length BL2 may be set to be the same, such as Figure 3A-3D As shown, BL2=BL3=18. At this time, the input / output circuit 40 only needs to implement two burst length data conversion modes, which can simplify the circuit structure of the input / output circuit 40 and is beneficial to reducing power consumption and area; the third burst length BL3 and the second burst length BL2 can also be set to be different. For example: for DDR4 products, BL2 can be set to 17, and BL3 can be set to 18. When the extension function does not need to be turned on, a smaller second burst length BL2 is set, which is beneficial to shorten the data output time.

[0065] It should be noted that when the memory is in the on-chip verification mode or the expansion function of the memory is not turned on, there is no need to output the extended data to the outside through the data port 50, and the input / output circuit 40 does not need to process the extended data. For example: there is no need to receive and serialize the cyclic redundancy check data CRC_code. At this time, the circuit module that processes the extended data in the input / output circuit 40 can be turned off or disabled, which can improve the data processing speed of the input / output circuit 40 and reduce its power consumption.

[0066] In one embodiment of the present disclosure, continue to refer to Figure 2D The memory 100 also includes a CRC check circuit 60, which is configured to obtain storage data DATA from multiple data storage blocks 11, and generate and output cyclic redundancy check data CRC_code corresponding to the storage data DATA when the mode selection signal indicates that the memory 100 is in an off-chip check mode and the extended function indication signal indicates that the memory turns on the extended function.

[0067] In one embodiment of the present disclosure, when the memory 100 is in the on-chip check mode or the extended function is not turned on, since the input / output circuit 40 will not receive and process other data (the first check code ECC1 and the cyclic redundancy check data CRC_code) other than the stored data DATA, at this time, the CRC check circuit 60 can be disabled so that it does not receive and process the stored data DATA, so as to save the internal power consumption of the memory.

[0068] The check code used by the CRC check circuit 60 can be designed according to the position that the extended function data can occupy in the third output data string Out_s3, so that Figure 3B For example, a total of 8 bits in the 8 third output data strings Out_s3 corresponding to the 8 data ports can be configured as cyclic redundancy check data CRC_code, that is, 128b of stored data corresponds to 8b of cyclic redundancy check data, and the ATM-4 HEC ​​encoding method can be used.

[0069] It should be noted that Figure 2A-2D The functions performed by each component circuit and the data interaction between them when the memory 100 performs read access operations in different verification modes are respectively shown.

[0070] Since the multiple data ports 50, input / output circuit 40, data transmission circuit 30 and data verification circuit 20 in the memory 100 provided by the embodiment of the present disclosure can all perform bidirectional data processing and transmission functions, that is, the above-mentioned component circuits in the memory 100 not only support read access operations but also support write access operations. Figure 2E-2H and Figure 3A-3D , the functions performed by each component circuit and the data interaction between them when the memory 100 provided in the embodiment of the present disclosure performs write access operations in different verification modes are described.

[0071] In one embodiment of the present disclosure, Figure 2E-2F As shown, when the memory 100 performs a write operation, the input / output circuit 40 is further configured to, when the mode selection signal indicates that the memory 100 is in the on-chip verification mode, Figure 2E As shown, after the first input data string In_s1 of the first burst length BL1 received from each data port 50 is processed in parallel, the first write data W_Data1 output to the data verification circuit 20 is generated, and when the mode selection signal indicates that the memory 100 is in the off-chip verification mode, as shown Figure 2F As shown, after the second input data string In_s2 of the second burst length BL2 received from each data port 50 is parallelized, the second write data W_Data2 is generated and output to the data verification circuit 20; wherein, the first write data W_Data1 includes the data to be stored data, the second write data W_Data2 includes the data to be stored data and the corresponding second verification code ECC2, the first input data string In_s1 includes part of the serially input data to be stored data, and the second input data string In_s2 includes part of the serially input data to be stored data and part of the second verification code ECC2.

[0072] In one embodiment of the present disclosure, continue to refer to Figure 2E-2F The data verification circuit 20 is also configured to, when the mode selection signal indicates that the memory 100 is in the on-chip verification mode, encode the data to be stored data in the received first write data W_Data1 to generate a corresponding third verification code ECC3, and store the data to be stored data and the third verification code ECC3 in multiple data storage blocks 11 and the verification code storage block 12 respectively; and when the mode selection signal indicates that the memory 100 is in the off-chip verification mode, store the data to be stored data and the second verification code ECC2 in the received second write data W_Data2 in the multiple data storage blocks 11 and the verification code storage block 12 respectively.

[0073] In one embodiment of the present disclosure, continue to refer to Figure 2G-2H The input / output circuit 40 is further configured to receive an extended function indication signal, and when the mode selection signal indicates that the memory 100 is in an off-chip verification mode and the extended function indication signal indicates that the memory 100 turns on the extended function, the third input data string In_s3 of the third burst length BL3 received from each data port 50 is processed in parallel, and then the third write data W_Data3 is generated and output to the data verification circuit 20;

[0074] Among them, the third write data W_Data3 includes the data to be stored data, the corresponding second check code ECC2 and the second extended data RFU2, and the third input data string In_s3 includes part of the data to be stored data, part of the second check code ECC2 and part of the second extended data RFU2 input in series.

[0075] As mentioned above, the third burst length BL3 and the second burst length BL2 may be set to be the same or different.

[0076] It should be noted that when the memory is in the on-chip verification mode or the expansion function of the memory is not turned on, there is no need to receive the external extended data through the data port 50, and the input / output circuit 40 does not need to process the extended data. For example: there is no need to receive and parallelize the cyclic redundancy check data CRC_code. At this time, the circuit module for processing the extended data in the input / output circuit 40 can be turned off or disabled, which can improve the data processing speed of the input / output circuit 40 and reduce its power consumption.

[0077] In one embodiment of the present disclosure, reference Figure 4AThe memory 100 also includes: a data transmission circuit 30, connected between the data verification circuit 20 and the input / output circuit 40, and the data transmission circuit 30 is configured to transmit the first read data R_Data1 or the second read data R_Data2 from the data verification circuit 20 to the input / output circuit 40, and to transmit the first write data W_Data1 or the second write data W_Data2 from the input / output circuit 40 to the data verification circuit 20.

[0078] It should be noted that the data transmission circuit 30 in the memory 100 provided in the embodiment of the present disclosure is only used for bidirectional transmission of internal data, such as drive enhancement, delay, synchronization, level conversion, etc., but does not substantially process the data.

[0079] In one embodiment of the present disclosure, reference Figure 4B The data transmission circuit 30 can also receive an extended function indication signal, and when the extended function indication signal indicates that the memory 100 turns on the extended function, the data transmission circuit 30 is also configured as follows: during a read access operation, the second read data R_Data2 and the cyclic redundancy check data CRC_code are respectively transmitted from the data verification circuit 20 and the CRC verification circuit 60 to the input / output circuit 40; during a write access operation, the data to be stored data and the second check code ECC2 in the third write data W_Data3 are transmitted from the input / output circuit 40 to the data verification circuit 20, and the cyclic redundancy check data CRC_code in the third write data W_Data3 is transmitted from the input / output circuit 40 to the CRC verification circuit 60.

[0080] It should be noted that Figure 4B The cyclic redundancy check function is used as an example to illustrate the extended function. The extended function may also be other functions executed in the memory, which are not specifically limited here.

[0081] In one embodiment of the present disclosure, reference Figure 7A-7BThe data transmission circuit 30 includes: a storage data transmission bus 31 and a check code transmission bus 32; the storage data transmission bus 31 is configured to transmit storage data DATA or data to be stored data; the check code transmission bus 32 is configured to receive a mode selection signal and transmit the first check code ECC1 or the second check code ECC2 when the mode selection signal indicates that the memory 100 is in an off-chip check mode, and is disabled when the mode selection signal indicates that the memory 100 is in an on-chip check mode. Specifically, the storage data transmission bus 31 is used to transfer the storage data DATA in the first read data R_Data1 or the second read data R_Data2 from the data verification circuit 20 to the input / output circuit 40, and to transfer the data to be stored in the first write data W_Data1 or the second write data W_Data2 from the input / output circuit 40 to the data verification circuit 20; the check code transmission bus 32 is used to transfer the first check code ECC1 in the second read data R_Data2 from the data verification circuit 20 to the input / output circuit 40, and to transfer the second check code ECC2 in the second write data W_Data2 from the input / output circuit 40 to the data verification circuit 20.

[0082] Here, when the memory 100 is in the on-chip verification mode, as shown in FIG. Figure 7B As shown, the memory 100 does not need to receive external check codes through the data port 50 or output check codes to the outside through the data port 50, and the check code transmission bus 32 in the memory 100 does not need to transmit check data such as the first check code ECC1 or the second check code ECC2. At this time, the check code transmission bus 32 can be turned off or disabled to achieve the purpose of reducing the power consumption of data transmission in the memory.

[0083] It should be noted that when the memory 100 supports an extended function (herein, the cyclic redundancy check function is used as an example for explanation), that is, when the extended function indication signal received by the data transmission circuit 30 indicates that the memory 100 turns on the extended function, Figure 7C As shown, the storage data transmission bus 31 and the check code transmission bus 32 are also used to transmit the to-be-stored data data and the second check code ECC2 in the third write data W_Data3, respectively.

[0084] In one embodiment of the present disclosure, reference Figure 7C-D The data transmission circuit 30 also includes: an extended data bus 33; the extended data bus 33 is configured to receive a mode selection signal and an extended function indication signal, and transmit the first extended data or the second extended data when the mode selection signal indicates that the memory is in an off-chip verification mode and the extended function indication signal indicates that the memory is in an extended function on state, otherwise the extended data bus is disabled.

[0085] For the memory 100 supporting the extended function, if the memory 100 is in the on-chip verification mode or the extended function of the memory is not enabled, Fig.7D As shown, there is no need to receive external extended data through the data port 50 or output extended data to the outside through the data port 50, the extended data bus 33 does not need to transmit extended data, and the input / output circuit 40 does not need to process the extended data, for example: cyclic redundancy check data CRC_code. At this time, the extended data bus 33 can be turned off or disabled to achieve the purpose of reducing the power consumption of data transmission in the memory 100.

[0086] In one embodiment of the present disclosure, reference Figure 5 , Figure 6 , Figure 7A-7D , Figure 8A-B The input / output circuit 40 includes a data conversion circuit 42, and the data conversion circuit 42 includes a plurality of data conversion sub-circuits 421 corresponding to the plurality of data ports 50 one by one; each data conversion sub-circuit 421 includes a serializer 422 and a parallelizer 423;

[0087] The serializer 422 is coupled to the data transmission circuit 30 and the corresponding data port 50, respectively, and is configured to, when the mode selection signal indicates that the memory 100 is in the on-chip verification mode, Fig. 7A and 8A As shown, after the partial storage data DATA received from the data transmission circuit 30 is serialized according to the first burst length BL1, a first output data string Out_s1 output to the corresponding data port 50 is generated, and when the mode selection signal indicates that the memory is in the off-chip verification mode, as shown Figure 7B and 8B As shown, after the partial storage data DATA and the partial first check code ECC1 received from the data transmission circuit 30 are serialized according to the second burst length BL2, a second output data string Out_s2 output to the corresponding data port 50 is generated;

[0088] The parallelizer 423 is coupled to the data transmission circuit 30 and the corresponding data port 50, respectively, and is configured to, when the mode selection signal indicates that the memory 100 is in the on-chip verification mode, Fig. 7A and 8A As shown, after the first input data string In_s1 received from the corresponding data port 50 is processed in parallel, part of the first write data W_Data1 output to the data transmission circuit 30 is generated, and when the mode selection signal indicates that the memory 100 is in the off-chip verification mode, as shown Figure 7B and 8BAs shown, after the second input data string In_s2 received from the corresponding data port 50 is processed in parallel, a portion of the second write data W_Data2 output to the data transmission circuit 30 is generated.

[0089] Among them, Figure 7B and 8B As shown, the first write data W_Data1 corresponding to each data port 50 output includes part (16b) of the data to be stored data, and the second write data W_Data2 includes part (16b) of the data to be stored data and the corresponding part (1b) of the second check code ECC2.

[0090] In some embodiments, when the memory 100 supports an extended function, the serializer 422 may also be used to receive an extended function indication signal. When the mode selection signal indicates that the memory 100 is in an off-chip verification mode and the extended function indication signal indicates that the memory 100 turns on the extended function, Figure 7C and 8B As shown, after the partial storage data DATA, the partial first check code ECC1 and the partial first extended data RFU1 received from the data transmission circuit 30 are serialized according to the third burst length BL3, a third output data string Out_s3 output to the corresponding data port 50 is generated; the parallelizer 423 can also be used to receive the extended function indication signal, when the mode selection signal indicates that the memory 100 is in the off-chip check mode and the extended function indication signal indicates that the memory 100 turns on the extended function, as shown in FIG. Figure 7C and 8B As shown, after the third input data string In_s3 received from the corresponding data port 50 is processed in parallel, part of the to-be-stored data data, part of the second check code ECC2 and part of the second extended data RFU2 output to the data transmission circuit 30 are generated.

[0091] Here, the third burst length BL3 and the second burst length BL2 are set to be the same for illustration. Figure 8B As shown, BL2=BL3=18; in some other embodiments, the third burst length BL3 and the second burst length BL2 may also be set to be different, for example: for DDR4 products, BL2 may be set to 17 and BL3 may be set to 18, which is not specifically limited in the present disclosure.

[0092] It should be noted that, for the memory 100 supporting the extended function, if the memory 100 is in the on-chip verification mode or the extended function of the memory is not enabled, Fig.7DAs shown, the serializer 422 does not need to receive and process the first extended data RFU1, and the parallelizer 423 does not need to process and output the second extended data RFU2. The extended data is received from the outside through the data port 50 or the extended data is output to the outside through the data port 50. At this time, the extended data bus 33 can be turned off or disabled, and the serializer 422 and the parallelizer 423 can be adjusted not to process the extended data, so as to reduce the data processing time of the serializer 422 and the parallelizer 423, and save the internal power consumption of the memory.

[0093] In some embodiments, continue to refer to Figure 5 The input / output circuit 40 further includes: a first-in first-out register 41 and a data driver 43; the first-in first-out register 41 is coupled between the data transmission circuit 30 and the data conversion circuit 42, and is configured to receive and cache the first read data R_Data1 or the second read data R_Data2 from the data transmission circuit 30 during the memory 100 performs a read operation, and to receive and cache the first write data W_Data1 or the second write data W_Data2 after parallel processing from the data conversion circuit 42 during the memory 100 performs a write operation; the data driver 43 is coupled between the data conversion circuit 42 and a plurality of data ports 50, and is configured to receive a plurality of first output data strings Out_s1 or a plurality of second output data strings Out_s2 after serial processing from the data conversion circuit 42 during the memory 100 performs a read operation, and drive the output to the plurality of data ports 50, and to receive the corresponding plurality of first input data strings In_s1 or a plurality of second input data strings In_s2 through the plurality of data ports 50 during the memory 100 performs a write operation, and drive the output to the data conversion circuit 42.

[0094] It should be noted that when the memory 100 turns on the extended function (the cyclic redundancy check function is used as an example for the extended function here), the first-in first-out register 41 is also used to receive and cache the first extended data or the second extended data (not shown in the figure), for example: the cyclic redundancy check data CRC_code, and the data driver 43 is also used to receive multiple third output data strings Out_s3 after serialization processing and drive the output to multiple data ports 50 and receive the corresponding multiple third input data strings In_s3 through multiple data ports 50 and drive the output to the data conversion circuit 42.

[0095] It should be noted that the memories provided in the above embodiments can be implemented in cooperation with each other. The relevant technical details mentioned in the previous embodiment are still valid in this embodiment, and will not be repeated here to reduce repetition.

[0096] The present disclosure also provides a storage device, referring to Fig. 9The storage device 300 includes at least one storage channel 400, and each storage channel 400 includes a plurality of memories 100 provided in the above embodiments.

[0097] like Fig. 9 As shown, the storage device 300 can be a dual inline memory module (DIMM). Generally speaking, for a DIMM with two storage channels, the left and right sides include 8 memory chips 100 and 2 ECC chips 200. The ECC chips here are side-band ECC chips. Although the side-band ECC chips can detect and correct data errors that occur in the complete data transmission link of the storage system by the memory controller, they bring additional hardware costs and system complexity to the storage device 300. However, based on the memory 100 provided by the embodiment of the present disclosure, the verification mode can be flexibly configured through the data verification circuit. Among them, when the error risk of the data transmission link in the storage system is higher, the off-chip verification mode can be configured to send the verification code and storage data stored on the chip directly to the external memory controller, so that the memory controller can use the verification code stored on the chip to detect and correct data errors that occur in the complete data transmission link of the storage system. At this time, the verification code storage block inside the memory 100 can replace the function of the sideband ECC chip, that is, the memory 100 provided by the present disclosure uses the same verification code storage block, which can be compatible with the data verification function executed on the memory chip and the off-chip data verification function executed by the memory controller, thereby improving the utilization rate of the on-chip verification code storage block resources and saving the additional storage resource consumption brought by the storage device 300 when adopting other ECC schemes such as sideband ECC. Fig. 9 As shown, based on the memory 100 provided by the present disclosure, four ECC chips 200 in the storage device 300 can be omitted, greatly reducing the hardware cost and system complexity of the storage device 300.

[0098] The present disclosure also provides a method for operating a memory, wherein the memory includes a plurality of data storage blocks and a check code storage block, referring to Fig.10 , the operation method comprises the following steps:

[0099] Step S11: during a read operation of the memory, respectively acquiring storage data and corresponding first check codes from a plurality of data storage blocks and check code storage blocks;

[0100] Step S12: determining a verification mode of the memory in response to a mode selection signal;

[0101] Specifically, when the mode selection signal indicates that the memory is in the on-chip verification mode, step S121 is executed: data verification is performed on the stored data according to the first verification code, and the stored data after the data verification is output as the first read data; or,

[0102] When the mode selection signal indicates that the memory is in an off-chip verification mode, step S122 is executed: the stored data and the first verification code are directly output as second read data; wherein the first verification code in the second read data is used by an external memory controller to perform a data verification operation on the stored data.

[0103] In some embodiments, in combination Figure 1A-1B and Fig.10 The specific process of step S11 includes: during the read operation of the memory 100, the data verification circuit 20 obtains the storage data DATA and the corresponding first verification code ECC1 from the multiple data storage blocks 11 and the verification code storage block 12 respectively; the specific process of step S12 includes: the data verification circuit 20 determines the verification mode of the memory in response to the received mode selection signal; when the mode selection signal indicates that the memory 100 is in the on-chip verification mode, the data verification circuit 20 performs data verification on the storage data DATA according to the first verification code ECC1, and outputs the stored data DATA after data verification as the first read data R_Data1; when the mode selection signal indicates that the memory 100 is in the off-chip verification mode, the data verification circuit 20 directly outputs the storage data DATA and the first verification code ECC1 as the second read data R_Data2, and the first verification code ECC1 in the second read data R_Data2 is used to be output to the external memory controller, and the memory controller performs an off-chip data verification operation on the storage data DATA.

[0104] Based on this operation method, the memory can flexibly choose how to use and transmit the first check code ECC1 and the stored data DATA according to the check mode during the read operation. When the mode selection signal indicates that the memory is configured as the on-chip check mode, the first check code ECC1 is used to provide data protection for the data storage process inside the memory. The memory will directly perform error detection and correction on the stored data DATA according to the first check code ECC1. At this time, the first check code ECC1 has been used in the memory and has completed the data check function. It does not need to be output. Only the stored data DATA after data check needs to be output as the first read-out data R_Data1; when the mode selection signal indicates that the memory 100 is configured as the off-chip check mode, the first check code ECC1 is used to provide data protection for the complete data transmission link of the storage system. The memory will no longer perform the on-chip data check operation, but directly output the stored data DATA and the first check code ECC1 as the second read-out data R_Data2. At this time, the output first check code ECC1 will be received by the external memory controller to perform a data check operation on the completed storage data DATA. Therefore, the memory operation method provided by the embodiment of the present disclosure realizes the on-chip data verification function and the off-chip data verification function by using the same check code data to be compatible during the read operation, which can improve the utilization rate of the on-chip check code storage resources, increase the diversity of data protection schemes, and save the additional storage resource consumption caused by the use of the off-chip data verification ECC scheme.

[0105] In one embodiment of the present disclosure, continue to refer to Fig.10 After completing step S121 or step S122, the operation method further includes: step S13 (not shown in the figure): after serializing the first read data or the second read data, output it from the memory through multiple data ports; specifically, when the memory is in the on-chip verification mode, after completing step S121, step S131 is executed: after serializing the first read data according to the first burst length, multiple first output data strings output through multiple data ports are generated; when the memory is in the off-chip verification mode, after completing step S122, step S132 is executed: after serializing the second read data according to the second burst length, multiple second output data strings output through multiple data ports are generated; wherein the first burst length is less than the second burst length.

[0106] In some embodiments, in combination Figure 2A-2B and Fig.10The specific process of step S13 includes: the input / output circuit 40 arranged in the memory 100 receives the first read data R_Data1 or the second read data R_Data2 from the data verification circuit 20, and serializes the first read data R_Data1 or the second read data R_Data2, and then outputs it from the memory 100 through the multiple data ports 50; specifically, the input / output circuit 40 receives the mode selection signal, and when the mode selection signal indicates that the memory 100 is in the on-chip verification mode, the input / output circuit 40 serializes the received first read data R_Data1 according to the first burst length BL1, and generates multiple first output data strings Out_s1 output to the multiple data ports 50; when the mode selection signal indicates that the memory 100 is in the off-chip verification mode, the input / output circuit 40 serializes the received second read data R_Data2 according to the second burst length BL2, and generates multiple second output data strings Out_s2 output to the multiple data ports 50, wherein the first burst length BL1 is less than the second burst length BL2.

[0107] In one embodiment of the present disclosure, reference Figure 3A The first output data string Out_s1 includes a portion of the stored data DATA output in series, and the second output data string Out_s2 includes a portion of the stored data DATA output in series and a portion of the first check code ECC1.

[0108] In one embodiment of the present disclosure, Fig.11 As shown, when the memory is in the off-chip verification mode, after completing step S122, step S14 is executed: determining whether the expansion function of the memory is turned on; if the memory is in the off-chip verification mode and the expansion function is not turned on, step S132 is executed after completing step S122: the second read data is serialized according to the second burst length, and a plurality of second output data strings output through a plurality of data ports are generated; if the memory is in the off-chip verification mode and the expansion function is turned on, step S133 is executed after completing step S122: the second read data and the first expansion data are serialized according to the third burst length, and a plurality of third output data strings output through a plurality of data ports are generated; wherein the third output data string includes a portion of the stored data, a portion of the first verification code and a portion of the first expansion data output in series; and when the memory is in the on-chip verification mode, step S131 is directly executed after completing step S121: the first read data is serialized according to the first burst length, and a plurality of first output data strings output through a plurality of data ports are generated.

[0109] In some embodiments, in combination Figure 2A-2D , Figure 3A and Fig.11, step S14 executed after completing step S122 specifically includes: the input / output circuit 40 also receives the extended function indication signal, and determines whether the extended function of the memory is turned on according to the extended function indication signal, when the mode selection signal indicates that the memory 100 is in the off-chip verification mode and the extended function indication signal indicates that the memory is turned on, the input / output circuit 40 serializes the received second read data R_Data2 and the first extended data RFU1 according to the third burst length BL3, and generates a plurality of third output data strings Out_s3 output to the plurality of data ports 50; wherein, as Figure 3A As shown, the third output data string Out_s3 includes a portion of the serially output storage data DATA, a portion of the first check code ECC1 and a portion of the first extended data RFU1. At this time, if the memory is in the off-chip check mode and the extended function is not enabled, the input / output circuit 40 serializes the received second read data R_Data2 according to the second burst length BL2 to generate a plurality of second output data strings Out_s2 output to the plurality of data ports 50.

[0110] Here, the third burst length BL3 and the second burst length BL2 may be set to be the same, such as Figure 3A-3D As shown, BL2=BL3=18, the third burst length BL3 and the second burst length BL2 can also be set to be different, for example: for DDR4 products, BL2 can be set to 17 and BL3 can be set to 18.

[0111] It should be noted that the extended function may be a cyclic redundancy check function, and the corresponding first extended data RFU1 may be cyclic redundancy check data CRC_code. Meanwhile, the extended function may also be other functions executed in the memory.

[0112] It should also be noted that the memory operation methods provided in the above embodiments are all completed during the read access operation that is executed after the memory receives a read command; and the above memory operation methods can all be applied to the memory 100 in the aforementioned embodiments. For details not disclosed in the embodiments of the operation methods, please refer to the description of the aforementioned embodiments of the memory 100 for understanding, and no further details will be given here.

[0113] The present disclosure also provides another memory operation method, wherein the memory includes a plurality of data storage blocks and a check code storage block, referring to Fig.12 , the operation method comprises the following steps:

[0114] Step S21: during the memory performing a write operation, determining a verification mode of the memory in response to a mode selection signal;

[0115] When the mode selection signal indicates that the memory is in the on-chip verification mode, step S221 is executed: after parallel processing of a first input data string of a first burst length received from each data port, first write data is generated;

[0116] When the mode selection signal indicates that the memory is in the off-chip verification mode, executing step S222: generating second write data after parallel processing of a second input data string of a second burst length received from each data port;

[0117] Among them, the second burst length is greater than the first burst length, the first write data includes the data to be stored, the second write data includes the data to be stored and the corresponding second check code, the first input data string includes part of the serially input data to be stored, and the second input data string includes part of the serially input data to be stored and part of the second check code.

[0118] In some embodiments, in combination Figure 2E-2F and Fig.12 The specific process of step S21 includes: during the memory 100 performs a write operation, the input / output circuit 40 determines the memory verification mode according to the received mode selection signal; when the mode selection signal indicates that the memory 100 is in the on-chip verification mode, Figure 2E As shown, the input / output circuit 40 performs parallel processing on the first input data string In_s1 of the first burst length BL1 received from each data port 50, and generates the first write data W_Data1 output to the data verification circuit 20; when the mode selection signal indicates that the memory 100 is in the off-chip verification mode, as shown in FIG. Figure 2F As shown, the input / output circuit 40 parallelizes the second input data string In_s2 of the second burst length BL2 received from each data port 50, and generates second write data W_Data2 output to the data verification circuit 20; wherein the first write data W_Data1 includes the data to be stored data, the second write data W_Data2 includes the data to be stored data and the corresponding second verification code ECC2, the first input data string In_s1 includes part of the serially input data to be stored data, and the second input data string In_s2 includes part of the serially input data to be stored data and part of the second verification code ECC2.

[0119] Based on the above operation method, the memory can flexibly choose what kind of write data to receive and process according to the verification mode during the read operation. When the mode selection signal indicates that the memory is configured as the on-chip verification mode, the memory receives a first input data string including only the data to be stored and processes it to generate the first write data. At this time, the memory needs to generate an internal third verification code ECC3 based on the data to be stored, thereby realizing the on-chip verification of the data. The memory can store the data to be stored and the internally generated third verification code ECC3 into the data storage block and the verification code storage block; when the mode selection signal indicates that the memory 100 is configured as the off-chip verification mode, the memory receives a second input data string including the data to be stored and the second verification code and processes it to generate the second write data. The second verification code ECC2 corresponding to the data to be stored is directly generated and sent by the external memory controller. At this time, the memory does not need to generate an internal third verification code based on the data to be stored. The memory can directly store the data to be stored in the second write data W_Data2 and the externally received second verification code ECC2 into the data storage block and the verification code storage block. Therefore, the operating method of the above-mentioned memory provided by the embodiment of the present disclosure realizes on-chip data verification function and off-chip data verification function based on mode selection signal compatibility during write operation, which can improve the utilization rate of on-chip verification code storage resources, increase the diversity of data protection schemes, and save the additional storage resource consumption caused by the use of off-chip data verification ECC scheme.

[0120] In one embodiment of the present disclosure, continue to refer to Fig.12 The operation method also includes: when the memory is in the on-chip verification mode, completing step S221 and executing step S231 and step S241: encoding the data to be stored in the received first write data to generate a corresponding third verification code; storing the data to be stored and the third verification code in multiple data storage blocks and verification code storage blocks respectively; when the memory is in the off-chip verification mode, completing step S222 and executing step S232: storing the data to be stored and the second verification code in the received second write data in multiple data storage blocks and verification code storage blocks respectively.

[0121] In some embodiments, in combination Figure 2E-2F and Fig.12When the memory 100 is in the on-chip verification mode, the data verification circuit 20 encodes the data to be stored data in the received first write data W_Data1 to generate the corresponding third verification code ECC3, and stores the data to be stored data and the third verification code ECC3 into multiple data storage blocks 11 and verification code storage blocks 12 respectively. When the memory 100 is in the off-chip verification mode, the data verification circuit 20 stores the data to be stored data and the second verification code ECC2 in the received second write data W_Data2 into multiple data storage blocks 11 and verification code storage blocks 12 respectively.

[0122] In one embodiment of the present disclosure, reference Fig.13 , when the mode selection signal indicates that the memory is in the off-chip verification mode, the operation method also includes: step S31: judging whether the extended function of the memory is turned on; if the memory is in the off-chip verification mode and the extended function is not turned on, executing steps S222 and S232 in sequence: generating second write data after parallel processing of the second input data string received from each data port; generating multiple second output data strings output through multiple data ports after serial processing of the second read data according to the second burst length; if the memory is in the off-chip verification mode and the extended function is turned on, executing steps S223 and S233: generating third write data after parallel processing of the third input data string of the third burst length received from each data port; storing the data to be stored and the second check code in the received third write data into multiple data storage blocks and check code storage blocks respectively; wherein the third write data includes the data to be stored, the corresponding second check code and the second extended data, and the third input data string includes part of the data to be stored, part of the second check code and part of the second extended data input in series.

[0123] In some embodiments, in combination Figure 2E-2H , Figure 3A and Fig.13, when it is determined that the memory is in the off-chip verification mode after executing step S21, the executed step S31 specifically includes: the input / output circuit 40 also receives an extended function indication signal, and determines whether the extended function of the memory is turned on according to the extended function indication signal, and when the mode selection signal indicates that the memory 100 is in the off-chip verification mode and the extended function indication signal indicates that the memory turns on the extended function, the third input data string In_s3 of the third burst length BL3 received from each data port 50 is parallelized and processed to generate third write data W_Data3 output to the data verification circuit 20; wherein the third write data W_Data3 includes data to be stored, the corresponding second check code ECC2 and second extended data RFU2, and the third input data string In_s3 includes part of the data to be stored data, part of the second check code ECC2 and part of the second extended data RFU2 input in series. On the contrary, if the memory is in off-chip verification mode and the extension function is not enabled, step S222 is executed, that is, the input / output circuit 40 parallelizes the second input data string In_s2 of the second burst length BL2 received from each data port 50 to generate the second write data W_Data2 output to the data verification circuit 20.

[0124] Here, the third burst length BL3 and the second burst length BL2 may be set to be the same, such as Figure 3A-3D As shown, BL2=BL3=18, the third burst length BL3 and the second burst length BL2 can also be set to be different, for example: for DDR4 products, BL2 can be set to 17 and BL3 can be set to 18.

[0125] It should be noted that the extended function may be a cyclic redundancy check function, and the corresponding first extended data RFU1 may be cyclic redundancy check data CRC_code. Meanwhile, the extended function may also be other functions executed in the memory.

[0126] It should also be noted that the memory operation methods provided in the above embodiments are all completed during the write access operation that is executed after the memory receives a write command; and the above memory operation methods can all be applied to the memory 100 in the aforementioned embodiments. For details not disclosed in the embodiments of the operation methods, please refer to the description of the embodiments of the aforementioned memory 100 for understanding, and no further details will be given here.

[0127] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0128] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0129] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, comprising: A plurality of data storage blocks and a check code storage block; a data verification circuit configured to obtain storage data and corresponding first verification codes from the plurality of data storage blocks and the verification code storage block, respectively, and determine whether to perform a data verification operation in response to a received mode selection signal; The data verification circuit is also configured to, when the mode selection signal indicates that the memory is in an on-chip verification mode, perform data verification on the stored data according to the first verification code, and output the stored data after data verification as first read-out data, and when the mode selection signal indicates that the memory is in an off-chip verification mode, directly output the stored data and the first verification code as second read-out data; wherein the first verification code in the second read-out data is used by an external memory controller to perform a data verification operation on the stored data.

2. The memory according to claim 1, characterized in that: The memory also includes: The input / output circuit is configured to receive the mode selection signal, and when the mode selection signal indicates that the memory is in the on-chip verification mode, the received first read data is serialized according to the first burst length to generate a plurality of first output data strings output to a plurality of data ports; and when the mode selection signal indicates that the memory is in the off-chip verification mode, the received second read data is serialized according to the second burst length to generate a plurality of second output data strings output to the plurality of data ports; wherein the first burst length is less than the second burst length.

3. The memory according to claim 2, characterized in that: The first output data string includes a portion of the stored data output in series, and the second output data string includes a portion of the stored data output in series and a portion of the first check code.

4. The memory according to claim 2, characterized in that: The input / output circuit is further configured to receive an extended function indication signal, and when the mode selection signal indicates that the memory is in an off-chip verification mode and the extended function indication signal indicates that the memory turns on an extended function, the received second read data and first extended data are serialized according to a third burst length to generate a plurality of third output data strings output to the plurality of data ports; The third output data string includes part of the stored data, part of the first check code and part of the first extended data output in series.

5. The memory according to claim 2, characterized in that: The input / output circuit is further configured to, when the mode selection signal indicates that the memory is in the on-chip verification mode, generate first write data output to the data verification circuit after parallel processing of a first input data string of a first burst length received from each of the data ports, and to generate second write data output to the data verification circuit after parallel processing of a second input data string of a second burst length received from each of the data ports when the mode selection signal indicates that the memory is in the off-chip verification mode; wherein the first write data includes data to be stored, the second write data includes the data to be stored and a corresponding second verification code, the first input data string includes a serially input portion of the data to be stored, and the second input data string includes a serially input portion of the data to be stored and a portion of the second verification code.

6. The memory according to claim 5, characterized in that: The data verification circuit is further configured to, when the mode selection signal indicates that the memory is in the on-chip verification mode, encode the data to be stored in the received first write data to generate a corresponding third verification code, and store the data to be stored and the third verification code in the multiple data storage blocks and the verification code storage block, respectively, and when the mode selection signal indicates that the memory is in the off-chip verification mode, store the data to be stored in the received second write data and the second verification code in the multiple data storage blocks and the verification code storage block, respectively.

7. The memory according to claim 5, characterized in that: The input / output circuit is further configured to receive an extended function indication signal, and when the mode selection signal indicates that the memory is in an off-chip verification mode and the extended function indication signal indicates that the memory turns on an extended function, after parallel processing of a third input data string of a third burst length received from each of the data ports, generate third write data output to the data verification circuit; The third write data includes the data to be stored, the corresponding second check code and second extended data, and the third input data string includes part of the data to be stored, part of the second check code and part of the second extended data input in series.

8. The memory according to claim 6, characterized in that: The memory also includes: A data transmission circuit is connected between the data verification circuit and the input / output circuit, and the data transmission circuit is configured to transmit the first read data or the second read data from the data verification circuit to the input / output circuit, and to transmit the first write data or the second write data from the input / output circuit to the data verification circuit.

9. The memory according to claim 8, characterized in that: The input / output circuit includes a data conversion circuit, and the data conversion circuit includes a plurality of data conversion sub-circuits corresponding to the plurality of data ports one by one; each of the data conversion sub-circuits includes a serializer and a parallelizer; The serializer is coupled to the data transmission circuit and the corresponding data port, respectively, and is configured to, when the mode selection signal indicates that the memory is in the on-chip verification mode, serialize part of the storage data received from the data transmission circuit according to the first burst length, and then generate the first output data string output to the corresponding data port; and, when the mode selection signal indicates that the memory is in the off-chip verification mode, serialize part of the storage data and part of the first verification code received from the data transmission circuit according to the second burst length, and then generate the second output data string output to the corresponding data port; The parallelizer is coupled to the data transmission circuit and the corresponding data port, respectively, and is configured to parallelize the first input data string received from the corresponding data port and generate part of the first write data output to the data transmission circuit when the mode selection signal indicates that the memory is in the on-chip verification mode, and to parallelize the second input data string received from the corresponding data port and generate part of the second write data output to the data transmission circuit when the mode selection signal indicates that the memory is in the off-chip verification mode.

10. The memory according to claim 9, characterized in that: The input / output circuit also includes: a first-in first-out register and a data driver; The first-in-first-out register is coupled between the data transmission circuit and the data conversion circuit, and is configured to receive and cache the first read data or the second read data from the data transmission circuit during a read operation of the memory, and to receive and cache the first write data or the second write data after parallel processing from the data conversion circuit during a write operation of the memory; The data driver is coupled between the data conversion circuit and the multiple data ports, and is configured to receive the multiple first output data strings or the multiple second output data strings after serialization from the data conversion circuit during a read operation of the memory, and drive the outputs to the multiple data ports, and to receive the corresponding multiple first input data strings or the multiple second input data strings through the multiple data ports during a write operation of the memory, and drive the outputs to the data conversion circuit.

11. The memory according to claim 8, characterized in that: The data transmission circuit comprises: a storage data transmission bus and a check code transmission bus; The storage data transmission bus is configured to transmit the storage data or the data to be stored; The check code transmission bus is configured to receive the mode selection signal and transmit the first check code or the second check code when the mode selection signal indicates that the memory is in an off-chip check mode, and is disabled when the mode selection signal indicates that the memory is in an on-chip check mode.

12. The memory according to claim 11, characterized in that: The data transmission circuit further comprises: an extended data bus; The extended data bus is configured to receive the mode selection signal and the extended function indication signal, and transmit the first extended data or the second extended data when the mode selection signal indicates that the memory is in an off-chip verification mode and the extended function indication signal indicates that the memory is in an extended function enabled state, otherwise the extended data bus is disabled.

13. A storage device comprising at least one storage channel, each of the storage channels comprising a plurality of memories according to any one of claims 1 to 12.

14. A method for operating a memory, characterized in that: The memory includes a plurality of data storage blocks and a check code storage block, and the operation method includes: Respectively acquiring storage data and corresponding first check codes from the plurality of data storage blocks and the check code storage block; determining a verification mode of the memory in response to a mode selection signal; When the mode selection signal indicates that the memory is in an on-chip verification mode, performing data verification on the stored data according to the first verification code, and outputting the verified stored data as first read data; or When the mode selection signal indicates that the memory is in an off-chip verification mode, directly outputting the stored data and the first verification code as second read data; The first check code in the second read data is used by an external memory controller to perform a data check operation on the stored data.

15. The operating method according to claim 14, characterized in that: The operation method also includes: After serializing the first read data or the second read data, the data is output from the memory through a plurality of data ports; Wherein, when the memory is in the on-chip verification mode, the first read-out data is serialized according to the first burst length to generate a plurality of first output data strings output through the plurality of data ports; when the memory is in the off-chip verification mode, the second read-out data is serialized according to the second burst length to generate a plurality of second output data strings output through the plurality of data ports; the first burst length is smaller than the second burst length.

16. The operating method according to claim 14, characterized in that: After directly outputting the stored data and the first check code as second read data, the operation method further includes: Determining whether the expansion function of the memory is enabled; If the memory is in the off-chip verification mode and the extension function is enabled, the second read data and the first extension data are serialized according to a third burst length to generate a plurality of third output data strings output through a plurality of data ports; The third output data string includes part of the stored data, part of the first check code and part of the first extended data output in series.

17. A method for operating a memory, characterized in that: The operation method comprises: determining a verification mode of the memory in response to a mode selection signal; When the mode selection signal indicates that the memory is in an on-chip verification mode, a first input data string of a first burst length received from each data port is processed in parallel to generate first write data; When the mode selection signal indicates that the memory is in an off-chip verification mode, a second input data string of a second burst length received from each of the data ports is processed in parallel to generate second write data; Among them, the second burst length is greater than the first burst length, the first write data includes data to be stored, the second write data includes the data to be stored and a corresponding second check code, the first input data string includes part of the data to be stored that is serially input, and the second input data string includes part of the data to be stored that is serially input and part of the second check code.

18. The operating method according to claim 17, characterized in that: The memory includes a plurality of data storage blocks and a check code storage block, and the operation method further includes: When the memory is in the on-chip verification mode, encoding the data to be stored in the received first write data to generate a corresponding third verification code, and storing the data to be stored and the third verification code in the multiple data storage blocks and the verification code storage block respectively; When the memory is in the off-chip verification mode, the to-be-stored data and the second verification code in the received second write data are stored in the plurality of data storage blocks and the verification code storage block respectively.

19. The operating method according to claim 17, characterized in that: When the mode selection signal indicates that the memory is in the off-chip verification mode, the operating method further includes: Determining whether the expansion function of the memory is enabled; If the memory is in the off-chip verification mode and the extended function is enabled, a third input data string of a third burst length received from each of the data ports is processed in parallel to generate third write data; The third write data includes the data to be stored, the corresponding second check code and second extended data, and the third input data string includes part of the data to be stored, part of the second check code and part of the second extended data input in series.

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