A single-pole single-throw switch device suitable for wide-band design and its preparation method

Abstract

The present invention discloses a single-pole, single-throw switch device suitable for wideband design and a method for preparing the same. The device comprises: a semiconductor substrate and an ohmic metal, a gate metal, and multiple portions of interconnecting metal prepared on the semiconductor substrate; the ohmic metal comprises multiple reconstruction regions arranged in sequence, wherein a gate groove is provided between adjacent reconstruction regions; the gate metal comprises a first gate bar, a second gate bar, and a third gate bar; the first gate bar and the second gate bar are respectively located at the gate grooves inside two target reconstruction regions and are interconnected by the interconnecting metal of the first portion; the third gate bar is interspersed and arranged at the gate grooves between each non-target reconstruction region and is integrally connected; each non-target reconstruction region is divided into two groups, wherein adjacent non-target reconstruction regions are located in different groups, and the two groups of non-target reconstruction regions are interconnected in the same group by the interconnecting metal of the second portion and the third portion, respectively. The present invention improves the isolation performance of the switch device at high frequencies.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and in particular relates to a single-pole single-throw switch device suitable for wide-band design and a preparation method thereof. Background Art

[0002] The RF front-end begins at the antenna, passes through modules such as the RF switch and power amplifier, and ends at the modem. As RF module performance improves, the RF performance of components in the circuit deteriorates significantly. For RF switch components, parasitic capacitance becomes increasingly important as frequency increases, significantly degrading isolation. Therefore, high-performance switches are crucial for implementing wireless communication transceiver systems.

[0003] Switching devices require a balanced consideration of parameters such as insertion loss, isolation, and power handling. Currently, HEMTs are becoming the mainstream switching device, receiving extensive research and application. However, while existing HEMT switching devices offer minimal insertion loss, their isolation deteriorates significantly at high frequencies, hindering the design and research of broadband RF circuits. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a single-pole single-throw switch device suitable for wide-band design and a preparation method thereof.

[0005] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] A single-pole single-throw switch device suitable for wide-band design comprises: a semiconductor substrate, and an ohmic metal, a gate metal and a plurality of interconnecting metals prepared on the semiconductor substrate;

[0007] The ohmic metal comprises a plurality of reconstruction regions arranged in sequence, wherein gate grooves are provided between adjacent reconstruction regions;

[0008] The gate metal includes a first gate bar, a second gate bar and a third gate bar; the first gate bar and the second gate bar are respectively located at the gate groove inside the two target reconstruction areas; the two target reconstruction areas are the two outermost reconstruction areas among the multiple reconstruction areas; the first gate bar and the second gate bar are interconnected through the interconnection metal of the first part; the third gate bar is interspersed and arranged at the gate groove between each non-target reconstruction area and connected as a whole; the non-target reconstruction area is the reconstruction area of ​​the multiple reconstruction areas other than the two target reconstruction areas; the non-target reconstruction areas are divided into two groups, wherein adjacent non-target reconstruction areas are located in different groups, and the two groups of non-target reconstruction areas are interconnected in the same group through the interconnection metal of the second part and the third part respectively.

[0009] In one embodiment, the single-pole single-throw switch device further comprises: a first gate thin film resistor and a second gate thin film resistor fabricated on the semiconductor substrate;

[0010] Among them, one end of the first gate thin film resistor is connected to the third gate strip through the interconnection metal of the fourth part, and the other end is connected to the interconnection metal of the fifth part; one end of the second gate thin film resistor is connected to the interconnection metal of the first part, and the other end is connected to the interconnection metal of the sixth part.

[0011] In one embodiment, the two target reconstruction regions are further connected to the interconnection metal of the seventh portion and the eighth portion, respectively.

[0012] In one embodiment, the active region of the single-pole single-throw switch device is located in the region where the ohmic metal is located, and the active region includes a series partition and two parallel partitions;

[0013] Among them, a parallel partition is formed in the area composed of each target reconstruction area and its adjacent non-target reconstruction area; a serial partition is formed in the area composed of each non-target reconstruction area; the size of the parallel partition along the target direction is smaller than the size of the serial partition along the target direction; the target direction is the length direction of each of the reconstruction areas.

[0014] In one embodiment, the sizes of the parallel partitions and the serial partitions along the target direction are determined by simulation optimization.

[0015] In one embodiment, a size of the parallel partition along the target direction is 100 μm±50 μm; a size of the serial partition along the target direction is 50 μm±25 μm.

[0016] In one embodiment, the fifth portion of the interconnect metal constitutes the first gate of the single-pole single-throw switch device, the sixth portion of the interconnect metal constitutes the second gate of the single-pole single-throw switch device, the second portion of the interconnect metal constitutes the signal output terminal of the single-pole single-throw switch device, and the third portion of the interconnect metal respectively constitutes the signal input terminals of the single-pole single-throw switch device;

[0017] When a 0V DC voltage is applied to the first gate and a negative DC voltage is applied to the second gate, the signal input terminal and the signal output terminal are connected, so that the single-pole single-throw switch device is turned on; when a negative DC voltage is applied to the first gate and a 0V DC voltage is applied to the second gate, the signal input terminal and the signal output terminal are not connected, so that the single-pole single-throw switch device is turned off.

[0018] The present invention also provides a method for preparing a single-pole single-throw switch device suitable for wide-band design, comprising:

[0019] Step 1: obtaining a semiconductor substrate and depositing an ohmic metal on the semiconductor substrate; the ohmic metal comprises a plurality of reconstructed regions arranged in sequence; wherein gaps are provided between adjacent reconstructed regions;

[0020] Step 2: performing ion implantation around the ohmic metal to form a high resistance region;

[0021] Step 3: depositing a passivation layer on the semiconductor substrate;

[0022] Step 4: etching the passivation layer above each of the reconstructed regions to expose each of the reconstructed regions;

[0023] Step 5: etching the passivation layer at each of the gaps to form a gate groove; the width of the gate groove is smaller than the width of the gap;

[0024] Step 6: Prepare first and second grating strips at the inner grooves of the two target reconstruction areas, respectively, and prepare third grating strips connected as one piece at the grooves between the non-target reconstruction areas; the two target reconstruction areas are the two outermost reconstruction areas of the multiple reconstruction areas; the non-target reconstruction areas are the reconstruction areas of the multiple reconstruction areas other than the two target reconstruction areas; the non-target reconstruction areas are divided into two groups, wherein adjacent non-target reconstruction areas are in different groups;

[0025] Step seven, prepare multiple parts of interconnection metal on the passivation layer; wherein, the first part of the interconnection metal is used to connect the first gate bar and the second gate bar; the second part of the interconnection metal is used to achieve the same group interconnection of one group of non-target reconstruction areas in the two groups, and the third part of the interconnection metal is used to achieve the same group interconnection of the other group of non-target reconstruction areas in the two groups.

[0026] In one embodiment, the preparation method further comprises: preparing a first gate thin film resistor and a second gate thin film resistor on the passivation layer on both sides of the ohmic metal respectively;

[0027] The interconnection metal prepared in step seven also includes: the fourth part, the fifth part and the sixth part of the interconnection metal;

[0028] Among them, one end of the first gate thin film resistor is connected to the third gate bar through the interconnection metal of the fourth part, and the other end is connected to the interconnection metal of the fifth part; one end of the second gate thin film resistor is connected to the interconnection metal of the first part, and the other end is connected to the interconnection metal of the sixth part.

[0029] In one embodiment, in step 2, ion implantation is performed around the ohmic metal to form a high-resistance region, including:

[0030] An active area is selected in the area where the ohmic metal is located; wherein a parallel partition is selected in the area consisting of each target reconstruction area and its adjacent non-target reconstruction area; a series partition is selected in the area consisting of each non-target reconstruction area; the size of the parallel partition along the target direction is smaller than the size of the series partition along the target direction; the target direction is the length direction of each reconstruction area;

[0031] Ion implantation is performed in the region outside the active region to form a high resistance region.

[0032] The single-pole, single-throw switch device suitable for wide-band design provided by the present invention adopts the theory of traveling wave transmission. By reconstructing and dividing the active area where the ohmic metal is located and discretely controlling the gate bars, series tubes and parallel tubes are integrated together on a single-cell element. The isolation performance of the switch device at high frequencies is greatly optimized by using series and parallel branches, and the device has a smaller layout.

[0033] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a three-dimensional structural diagram of a single-pole single-throw switch device suitable for wide-band design provided by an embodiment of the present invention;

[0035] Figure 2 1 is a top view of a single-pole, single-throw switch device suitable for wide-band design provided by an embodiment of the present invention;

[0036] Figure 3 yes Figure 2 The working principle diagram of the single-pole single-throw switch shown;

[0037] Figure 4 1 is a top view of another single-pole single-throw switch device suitable for wide-band design provided by an embodiment of the present invention;

[0038] Figure 5 yes Figure 4 The working principle diagram of the single-pole single-throw switch shown;

[0039] Figure 6 Schematic diagram of controlling the active area by controlling ion implantation in the high-resistance region in an embodiment of the present invention;

[0040] Figure 7 Schematic diagram of a series partition and two parallel partitions included in an active area in an embodiment of the present invention;

[0041] Figure 8 This is a layout of a single-pole, single-throw switch device designed in an embodiment of the present invention;

[0042] Figure 9Shown Figure 8 The switching performance of the designed single-pole single-throw switch device;

[0043] Figure 10(a) to Figure 10(h) This is a flow chart for preparing a single-pole single-throw switch device suitable for wide-band design provided by an embodiment of the present invention;

[0044] Figure 11 It is a schematic diagram of the effect after the gate metal in the embodiment of the present invention is prepared. DETAILED DESCRIPTION

[0045] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0046] In order to improve the isolation performance of the switch device at high frequencies, thereby facilitating the design and research of broadband radio frequency circuits, an embodiment of the present invention provides a single-pole single-throw switch device suitable for broadband design, such as Figure 1 As shown, the device includes: a semiconductor substrate, and an ohmic metal, a gate metal and a plurality of interconnection metal portions prepared on the semiconductor substrate.

[0047] Wherein, the semiconductor substrate is a wafer formed by epitaxial growth. For example, Figure 1 As shown, the semiconductor substrate comprises, from bottom to top: a substrate, a GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, and a SiN passivation layer. Thus, the single-pole, single-throw switch device is a switch device based on a gallium nitride high electron mobility field-effect transistor (GaN HEMT).

[0048] Ohmic metal, gate metal and multiple parts of interconnect metal are prepared on the semiconductor substrate. The specific preparation method will be described later. Figure 2 The ohmic metal includes a plurality of reconstruction regions arranged in sequence, wherein gate trenches are provided between adjacent reconstruction regions.

[0049] The active region of the single-pole, single-throw switch device is located within the region where the ohmic metal is located. This active region includes a series partition and two parallel partitions. Of the multiple reconfiguration regions, the two outermost reconfiguration regions are the two target reconfiguration regions. Each target reconfiguration region and its adjacent non-target reconfiguration region form a parallel partition within the region, and each non-target reconfiguration region form a series partition within the region. It is understood that the non-target reconfiguration region is the reconfiguration region other than the two target reconfiguration regions.

[0050] Continue to see Figure 2The gate metal includes a first gate bar 1, a second gate bar 2 and a third gate bar 3; the first gate bar 1 and the second gate bar 2 are respectively located at the gate grooves inside the two target reconstruction areas; the first gate bar 1 and the second gate bar 2 are interconnected through the interconnection metal of the first part; the third gate bar 3 is interspersed and arranged at the gate grooves between each non-target reconstruction area and connected as a whole; each non-target reconstruction area is divided into two groups, wherein adjacent non-target reconstruction areas are located in different groups, and the two groups of non-target reconstruction areas are interconnected in the same group through the interconnection metal of the second part and the third part, respectively, thereby forming the source and drain of the device.

[0051] Figure 2 In the figure, a represents the interconnect metal of the first part, b represents the interconnect metal of the second part, and c represents the interconnect metal of the third part. Port1 represents the signal input terminal of the single-pole single-throw switch device, and port2 represents the signal output terminal of the single-pole single-throw switch device. These two signal ports correspond to the source and drain of the device, respectively. Gate1 represents the first gate corresponding to the third gate strip, and VTCL1 represents the voltage applied to the first gate. Gate2 represents the second gate corresponding to the second gate strip and the third gate strip connected together, and VTCL2 represents the voltage applied to the second gate.

[0052] based on Figure 1 and Figure 2 The device structure shown, Figure 3 A schematic diagram of the working principle of the single-pole single-throw switch device is shown. Figure 3 In the series, it means based on Figure 1 and Figure 2 The device structure shown forms a series switch between port1 and port2. Shunt represents the series switch based on Figure 1 and Figure 2 The device structure shown forms a parallel switch between port 1 and port 2. When a 0V DC voltage is applied to the first gate and a negative DC voltage (e.g., -40V) is applied to the second gate, the series switch series conducts, the parallel switch shunt does not conduct, and conduction occurs between port 1 and port 2, placing the entire single-pole, single-throw (SPST) switch in a closed state. When a negative DC voltage is applied to the first gate and a 0V DC voltage is applied to the second gate, the series switch series closes and the parallel switch shunt conducts. A portion of the signal input from port 1 is blocked by the series switch series, while the remaining signal is directed to ground by the parallel switch shunt. Consequently, conduction occurs between port 1 and port 2, the entire SPST switch is closed, and isolation is significantly improved.

[0053] The single-pole, single-throw switch device suitable for wide-band design provided in an embodiment of the present invention adopts the theory of traveling wave transmission, reconstructs and divides the active area where the ohmic metal is located, integrates series tubes and parallel tubes together on a unit cell element, and greatly optimizes the isolation performance of the switch device at high frequencies by utilizing series-parallel branches, while having a smaller layout.

[0054] In the existing technology, independent field-effect transistors are used as RF front-end selection switches. Although their insertion loss is very small, the isolation deteriorates seriously at high frequencies, which is not conducive to the design and research of broadband RF circuits. On the other hand, traditional monolithic microwave integrated circuit designs mostly use traveling wave transmission structures to expand the operating frequency band of RF switches. However, the large-scale introduction of microstrip lines increases the difficulty of layout, resulting in the possible increase in the influence of electromagnetic effects between microstrips, and the increase in layout area leads to increased costs.

[0055] In one embodiment, the above-mentioned single-pole single-throw switch device in the embodiment of the present invention further includes: a first gate thin film resistor and a second gate thin film resistor prepared on the semiconductor substrate, such as Figure 4 As shown, one end of the first gate thin film resistor is connected to the third gate strip through the fourth section of interconnect metal, and the other end is connected to the fifth section of interconnect metal. One end of the second gate thin film resistor is connected to the first section of interconnect metal, and the other end is connected to the sixth section of interconnect metal. Furthermore, the two target reconstruction regions can also be connected to the seventh and eighth sections of interconnect metal, respectively, to form the metal ground of the single-pole, single-throw switch device. Figure 4 , d represents the interconnection metal of the fourth portion, e represents the interconnection metal of the fifth portion, f represents the interconnection metal of the sixth portion, g represents the interconnection metal of the seventh portion, and h represents the interconnection metal of the eighth portion.

[0056] Among them, the fifth part of the interconnection metal constitutes the first gate Gate1 of the single-pole single-throw switch device, the sixth part of the interconnection metal constitutes the second gate Gate2 of the single-pole single-throw switch device, the second part of the interconnection metal constitutes the signal output end port2 of the single-pole single-throw switch device, and the third part of the interconnection metal constitutes the signal input end port1 of the single-pole single-throw switch device.

[0057] based on Figure 1 and Figure 4 The device structure shown, Figure 5 A working principle diagram of another single-pole single-throw switch device provided by an embodiment of the present invention is shown. Figure 5 In FIG, R1 represents the first gate thin film resistor, and R2 represents the second gate thin film resistor. These two gate thin film resistors can limit the signal leakage from the gate, thereby increasing the isolation.

[0058] In one embodiment, in the active region of the SPST switch device, the dimension W of the parallel partition along the target direction isshunt Smaller than the size W of the concatenated partition along the target direction series Here, the target direction is the length direction of each reconstruction area. The size of the parallel partition and the series partition along the target direction can be controlled when preparing the high-resistance area of ​​the single-pole single-throw switch device. For details, see Figure 6 and Figure 7 As shown, on the upper surface of the single-pole single-throw switch device, the central area (in the red frame) is the active area, and high-resistance areas can be formed around it through ion implantation. Therefore, by adjusting the ion implantation range of the high-resistance area, the size of the parallel partition and the series partition along the target direction can be controlled.

[0059] In the embodiment of the present invention, the size of the parallel partition along the target direction is smaller than the size of the series partition along the target direction, which helps to improve the switching performance of the single-pole single-throw switch device.

[0060] Preferably, the size of the parallel partition and the series partition along the target direction can be determined by simulation optimization. When the size of the parallel partition and the series partition along the target direction is actually determined by simulation optimization, the size is related to the structure and preparation process of the semiconductor substrate. Therefore, by combining electromagnetic simulation and epitaxial material design, W can be adjusted with high freedom and high adaptability. shunt and W series The value of is used to achieve the optimized design of switch RF performance under wide bandwidth.

[0061] For example, based on Figure 1 The semiconductor substrate shown has a dimension W of the series partition along the target direction. series It can be 100μm±50μm. Correspondingly, the effective gate length of the series partition is n×W series , n is the number of gaps contained in the serial partition, which is the gap between adjacent reconstruction areas; the size W of the parallel partition along the target direction shunt It can be 50μm±25μm. Accordingly, the effective gate length of a single parallel partition is equal to W shunt , the total effective gate length of the two parallel partitions is 2×W series . Figure 8 The layout of the designed single-pole single-throw switch device is shown in Figure 9 As shown in the figure, the horizontal axis represents frequency, the left vertical axis represents insertion loss, and the right vertical axis represents isolation.

[0062] The single-pole, single-throw (SPST) switch device suitable for broadband designs, provided in embodiments of the present invention, employs the theory of traveling-wave transmission. By reconstructing and partitioning the active region where the ohmic metal resides and discretely controlling the gate strips, it integrates series and parallel transistors within a single-cell element. This utilizes series-parallel junctions to significantly optimize the isolation performance of the switch device at high frequencies, while also allowing for a smaller layout. Therefore, the SPST switch device suitable for broadband designs, provided in embodiments of the present invention, solves the problem of low isolation of switching elements in radio frequency circuits at high frequencies and can be widely used in broadband designs.

[0063] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing the above-mentioned single-pole single-throw switch device suitable for wide-band design. Figure 10(a) to Figure 10(h) The process of the preparation method is shown, and the annotations of the specific structures are shown in Figure 1 and Figure 4 , so in Figure 10(a) to Figure 10(h) Not otherwise noted. Figure 10(a) to Figure 10(h) , the preparation method comprises the following steps:

[0064] Step 1: obtain a semiconductor substrate and deposit an ohmic metal on the semiconductor substrate; the ohmic metal includes a plurality of reconstructed regions arranged in sequence; wherein gaps are provided between adjacent reconstructed regions.

[0065] Preferably, the width of the gap may be 2 μm to 5 μm.

[0066] Specifically, a photolithography process is used to form a pattern of multiple reconstructed areas on the surface of the current semiconductor substrate, and then ohmic metal evaporation is performed according to the pattern to deposit ohmic metal on the semiconductor substrate. After the deposition is completed, annealing is performed to complete the preparation of the ohmic metal, as shown in Figure 10(a).

[0067] The photolithography process may utilize SF6 photoresist, such as EPI621 photoresist, but is not limited thereto. Subsequent photolithography operations may refer to this photolithography process. The ohmic metal may comprise a structure of Ti / Al / Ni / Au stacked in sequence, with each layer having a thickness of 20 nm, 160 nm, 55 nm, or 45 nm, but is not limited thereto.

[0068] Step 2: Perform ion implantation around the ohmic metal to form a high-resistance region.

[0069] Specifically, high-energy He ions are injected around the ohmic metal using an injection isolation process, thereby blocking the two-dimensional electron gas conductive channel and forming a high-resistance region. In the region where the ohmic metal is located, the region where high-energy He ions are not injected forms an active region, as shown in FIG10( b ).

[0070] In a preferred implementation, step 2 may specifically include:

[0071] (1) selecting an active region within the region where the ohmic metal is located; wherein a parallel partition is selected within the region consisting of each target reconstruction region and its adjacent non-target reconstruction region; and a series partition is selected within the region consisting of each non-target reconstruction region; the size of the parallel partition along the target direction is smaller than the size of the series partition along the target direction; and the target direction is the length direction of each reconstruction region;

[0072] (2) Ion implantation is performed in areas outside the active area to form a high-resistance region.

[0073] Preferably, in the above step (1), the sizes of the parallel partitions and the serial partitions along the target direction can be determined by simulation optimization.

[0074] Step 3: depositing a passivation layer on the semiconductor substrate.

[0075] Specifically, a passivation layer is grown on the upper surface of the semiconductor substrate using a PECVD process, as shown in FIG10( c ).

[0076] For example, the passivation layer may be a SiN passivation layer, and the thickness thereof may be 120 nm, but is certainly not limited thereto.

[0077] Step 4: Etch the passivation layer above each reconstruction area to expose each reconstruction area.

[0078] Specifically, a pattern corresponding to the multiple reconstructed regions is formed on the surface of the passivation layer using a photolithography process. Subsequently, an F-based etching process is performed using ICP etching to expose the reconstructed regions beneath the pattern, as shown in Figure 10(d). The etching parameters can be determined based on the actual thickness of the passivation layer and are not further described here.

[0079] Step 5: Etching the passivation layer at each gap to form a gate groove; the width of the gate groove is smaller than the width of the gap.

[0080] Here, each gap refers to a gap between adjacent reconstruction regions.

[0081] Specifically, a photolithography process is used to form a photolithographic pattern of a gate groove on the surface of the passivation layer at each gap, and then F-based etching is performed using ICP etching to remove the passivation layer under the pattern, as shown in FIG10( e).

[0082] Step 6. Prepare the first and second gratings respectively at the gate grooves inside the two target reconstruction areas, and prepare the third gratings connected as one piece at the gate grooves between the non-target reconstruction areas; the two target reconstruction areas are the two outermost reconstruction areas among the multiple reconstruction areas; the non-target reconstruction area is the reconstruction area other than the two target reconstruction areas among the multiple reconstruction areas; each non-target reconstruction area is divided into two groups, where adjacent non-target reconstruction areas are in different groups.

[0083] Specifically, the patterns of the gate strips are photoetched on the surface of the passivation layer at the bottom of the gate groove and on both sides of the gate groove, and then the gate metal is evaporated according to the pattern to complete the preparation of the gate metal, as shown in Figure 10(f). Figure 11 shown.

[0084] For example, the gate metal may be a structure formed by sequentially stacking Ti / Au, and the thickness of each layer may be 45 nm or 400 nm, but is not limited thereto.

[0085] Step seven: prepare multiple parts of interconnection metal on the passivation layer; wherein, the first part of the interconnection metal is used to connect the first gate bar and the second gate bar; the second part of the interconnection metal is used to realize the same group interconnection of one group of non-target reconstruction areas in the two groups, and the third part of the interconnection metal is used to realize the same group interconnection of the other group of non-target reconstruction areas in the two groups.

[0086] Specifically, a pattern of interconnect metal is photoetched on the surface of the passivation layer, and then the interconnect metal is evaporated according to the pattern, as shown in FIG10( g ).

[0087] For example, the gate metal may be a structure formed by sequentially stacking Ti / Au, and the thickness of each layer may be 20 nm or 400 nm, but is not limited thereto.

[0088] Preferably, based on Figure 3 In the embodiment shown, the above-mentioned preparation method may further include, between step six and step seven: preparing a first gate thin film resistor and a second gate thin film resistor respectively on the passivation layer on both sides of the ohmic metal.

[0089] Specifically, the patterns of the first gate thin film resistor and the second gate thin film resistor are photoetched on the surface of the passivation layer, and then NiCr alloy is deposited according to the pattern using a sputter device to form the first gate thin film resistor and the second gate thin film resistor, as shown in FIG10(h).

[0090] Accordingly, as shown in Figure 10(g), the interconnect metal prepared in step 7 also includes: fourth, fifth, and sixth portions of interconnect metal; wherein one end of the first gate thin film resistor is connected to the third gate strip via the fourth portion of interconnect metal, and the other end is connected to the fifth portion of interconnect metal; and one end of the second gate thin film resistor is connected to the first portion of interconnect metal, and the other end is connected to the sixth portion of interconnect metal. Furthermore, the interconnect metal prepared in step 7 may also include seventh and eighth portions of interconnect metal; wherein the seventh and eighth portions of interconnect metal respectively connect the two target reconstruction areas.

[0091] The single-pole single-throw switch device prepared by the preparation method provided by the embodiment of the present invention has low insertion loss and high isolation, and the preparation process is simple, thereby achieving a high-performance switch device at a low cost.

[0092] It should be noted that the terms "first," "second," and the like are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0093] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0094] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings and the disclosed content. In the description of the present invention, the word "comprising" does not exclude other components or steps, "one" or "a" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0095] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0096] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0097] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0098] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A single-pole single-throw switch device suitable for wide-band design, characterized in that: include: A semiconductor substrate, and an ohmic metal, a gate metal, and a plurality of interconnection metals prepared on the semiconductor substrate; The ohmic metal comprises a plurality of reconstruction regions arranged in sequence, wherein gate grooves are provided between adjacent reconstruction regions; The gate metal includes a first gate bar, a second gate bar and a third gate bar; the first gate bar and the second gate bar are respectively located at the gate groove inside the two target reconstruction areas; the two target reconstruction areas are the two outermost reconstruction areas among the multiple reconstruction areas; the first gate bar and the second gate bar are interconnected through the interconnection metal of the first part; the third gate bar is interspersed and arranged at the gate groove between each non-target reconstruction area and connected as a whole; the non-target reconstruction area is the reconstruction area of ​​the multiple reconstruction areas other than the two target reconstruction areas; the non-target reconstruction areas are divided into two groups, wherein adjacent non-target reconstruction areas are located in different groups, and the two groups of non-target reconstruction areas are interconnected in the same group through the interconnection metal of the second part and the third part respectively.

2. The single-pole single-throw switch device suitable for wideband design according to claim 1, characterized in that: The single-pole single-throw switch device further includes: a first gate thin film resistor and a second gate thin film resistor prepared on the semiconductor substrate; Among them, one end of the first gate thin film resistor is connected to the third gate strip through the interconnection metal of the fourth part, and the other end is connected to the interconnection metal of the fifth part; one end of the second gate thin film resistor is connected to the interconnection metal of the first part, and the other end is connected to the interconnection metal of the sixth part.

3. The single-pole single-throw switch device suitable for wideband design according to claim 2, characterized in that: The two target reconstruction regions are further connected to the interconnection metals of the seventh portion and the eighth portion, respectively.

4. The single-pole single-throw switch device suitable for wideband design according to claim 1, characterized in that: The active area of ​​the single-pole single-throw switch device is located in the area where the ohmic metal is located, and the active area includes a series partition and two parallel partitions; Among them, a parallel partition is formed in the area composed of each target reconstruction area and its adjacent non-target reconstruction area; a serial partition is formed in the area composed of each non-target reconstruction area; the size of the parallel partition along the target direction is smaller than the size of the serial partition along the target direction; the target direction is the length direction of each of the reconstruction areas.

5. The single-pole single-throw switch device suitable for wide-band design according to claim 4, characterized in that: The sizes of the parallel partition and the serial partition along the target direction are determined through simulation optimization.

6. The single-pole single-throw switch device suitable for wide-band design according to claim 5, characterized in that: The size of the parallel partition along the target direction is 100 μm±50 μm; the size of the serial partition along the target direction is 50 μm±25 μm.

7. The single-pole single-throw switch device suitable for wideband design according to claim 3, characterized in that: The fifth portion of the interconnect metal constitutes a first gate of the single-pole single-throw switch device, the sixth portion of the interconnect metal constitutes a second gate of the single-pole single-throw switch device, the second portion of the interconnect metal constitutes a signal output end of the single-pole single-throw switch device, and the third portion of the interconnect metal respectively constitutes a signal input end of the single-pole single-throw switch device; When a 0V DC voltage is applied to the first gate and a negative DC voltage is applied to the second gate, the signal input terminal and the signal output terminal are connected, so that the single-pole single-throw switch device is turned on; when a negative DC voltage is applied to the first gate and a 0V DC voltage is applied to the second gate, the signal input terminal and the signal output terminal are not connected, so that the single-pole single-throw switch device is turned off.

8. A method for preparing a single-pole single-throw switch device suitable for wide-band design, characterized in that: include: Step 1: obtaining a semiconductor substrate and depositing an ohmic metal on the semiconductor substrate; the ohmic metal comprises a plurality of reconstructed regions arranged in sequence; wherein gaps are provided between adjacent reconstructed regions; Step 2: performing ion implantation around the ohmic metal to form a high resistance region; Step 3: depositing a passivation layer on the semiconductor substrate; Step 4: etching the passivation layer above each of the reconstructed regions to expose each of the reconstructed regions; Step 5: etching the passivation layer at each of the gaps to form a gate groove; the width of the gate groove is smaller than the width of the gap; Step 6: Prepare first and second grating strips at the inner grooves of the two target reconstruction areas, respectively, and prepare third grating strips connected as one piece at the grooves between the non-target reconstruction areas; the two target reconstruction areas are the two outermost reconstruction areas of the multiple reconstruction areas; the non-target reconstruction areas are the reconstruction areas of the multiple reconstruction areas other than the two target reconstruction areas; the non-target reconstruction areas are divided into two groups, wherein adjacent non-target reconstruction areas are in different groups; Step seven, prepare multiple parts of interconnection metal on the passivation layer; wherein, the first part of the interconnection metal is used to connect the first gate bar and the second gate bar; the second part of the interconnection metal is used to achieve the same group interconnection of one group of non-target reconstruction areas in the two groups, and the third part of the interconnection metal is used to achieve the same group interconnection of the other group of non-target reconstruction areas in the two groups.

9. The preparation method according to claim 8, characterized in that Between step 6 and step 7, the preparation method further comprises: preparing a first gate thin film resistor and a second gate thin film resistor on the passivation layer on both sides of the ohmic metal respectively; The interconnection metal prepared in step seven also includes: the fourth part, the fifth part and the sixth part of the interconnection metal; Among them, one end of the first gate thin film resistor is connected to the third gate bar through the interconnection metal of the fourth part, and the other end is connected to the interconnection metal of the fifth part; one end of the second gate thin film resistor is connected to the interconnection metal of the first part, and the other end is connected to the interconnection metal of the sixth part.

10. The preparation method according to claim 8, characterized in that In step 2, ion implantation is performed around the ohmic metal to form a high-resistance region, including: An active area is selected in the area where the ohmic metal is located; wherein a parallel partition is selected in the area consisting of each target reconstruction area and its adjacent non-target reconstruction area; a series partition is selected in the area consisting of each non-target reconstruction area; the size of the parallel partition along the target direction is smaller than the size of the series partition along the target direction; the target direction is the length direction of each reconstruction area; Ion implantation is performed in the region outside the active region to form a high resistance region.

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