Magnetoresistive random access memory and preparation method thereof

Abstract

The present application provides a magnetoresistive random access memory and a preparation method thereof, which relates to the field of semiconductor technology and is used to solve the technical problem of low reliability of data writing and storage. The magnetoresistive random access memory includes: a substrate, a bottom electrode layer arranged on the substrate, and at least two magnetic tunnel junctions arranged on the bottom electrode layer; the bottom electrode layer includes at least two electrode parts connected in sequence, an angle is formed between two adjacent electrode parts, and the two adjacent electrode parts are not collinear; each electrode part has at least one magnetic tunnel junction; when a write current is applied to the bottom electrode layer, one of the at least two magnetic tunnel junctions has a first resistance state, and the other of the at least two magnetic tunnel junctions has a second resistance state, so that the resistance between the at least two magnetic tunnel junctions forms a differential state. The present application can improve the success rate of data writing, thereby improving the reliability of data storage of the magnetoresistive random access memory.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a magnetoresistive random access memory and a method for preparing the same. Background Art

[0002] Magnetic Tunnel Junction (MTJ) is the basic storage unit of Magnetoresistive Random Access Memory (MRAM). The magnetic tunnel junction includes a free layer, a barrier layer and a reference layer stacked in sequence, wherein the magnetization direction of the reference layer remains unchanged, while the magnetization direction of the free layer can be changed by external excitation. When the magnetization direction of the free layer is parallel or anti-parallel to that of the reference layer, the magnetic tunnel junction is in a low resistance state or a high resistance state.

[0003] In the related art, a magnetoresistive random access memory includes at least a pair of magnetic tunnel junctions with opposite resistance states, wherein one of the pair of magnetic tunnel junctions with opposite resistance states is a data unit and the other magnetic tunnel junction is a reference unit. When two write currents in opposite directions are applied to the data unit and the reference unit respectively, one of the two magnetic tunnel junctions is in a low resistance state and the other is in a high resistance state. Subsequently, differential reading is performed to achieve the writing of bit data.

[0004] However, in the related art, whether the bit data can be successfully written depends on whether the data unit and the reference unit are successfully written at the same time. If one of the data unit and the reference unit is not written successfully, the bit data is not written successfully, which leads to the technical problem of low reliability of data writing storage. Summary of the invention

[0005] In view of the above problems, an embodiment of the present application provides a magnetoresistive random access memory and a method for preparing the same, which are used to improve the success rate of bit data writing, thereby improving the reliability of data storage in the magnetoresistive random access memory.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] A first aspect of an embodiment of the present application provides a magnetoresistive random access memory, comprising: a substrate, a bottom electrode layer disposed on the substrate, and at least two magnetic tunnel junctions disposed on the bottom electrode layer;

[0008] The bottom electrode layer comprises at least two electrode parts connected in sequence, an angle is formed between two adjacent electrode parts, and the two adjacent electrode parts are not collinear; each electrode part has at least one magnetic tunnel junction;

[0009] When a write current is applied to the bottom electrode layer, one of the at least two magnetic tunnel junctions has a first resistance state and the other of the at least two magnetic tunnel junctions has a second resistance state, so that the resistance between the at least two magnetic tunnel junctions forms a differential state.

[0010] In some optional embodiments, when the magnetization direction of the reference layer in the magnetic tunnel junction is parallel or antiparallel to the magnetization direction of the free layer, the magnetic tunnel junction has the first resistance state;

[0011] When the magnetization direction of the reference layer and the magnetization direction of the free layer in the magnetic tunnel junction are in a non-parallel state or a non-anti-parallel state, the magnetic tunnel junction has the second resistance state.

[0012] In some optional embodiments, at least one antiferromagnetic layer is provided between at least one of the electrode portions and the magnetic tunnel junction corresponding thereto;

[0013] Wherein, the exchange bias coupling field between the antiferromagnetic layer and the free layer of the magnetic tunnel junction is greater than the coercive field of the free layer.

[0014] In some optional embodiments, two adjacent electrode portions are perpendicular to each other.

[0015] In some optional embodiments, the bottom electrode layer includes a first electrode portion and a second electrode portion, and the first electrode portion and the second electrode portion have the angle between them;

[0016] The magnetic tunnel junction includes a first magnetic tunnel junction and a second magnetic tunnel junction, the first magnetic tunnel junction is arranged on the first electrode portion, and the second magnetic tunnel junction is arranged on the second electrode portion.

[0017] In some optional embodiments, the bottom electrode layer includes at least one first electrode portion and at least two second electrode portions, at least one first electrode portion and at least two second electrode portions are alternately arranged in sequence, there is the angle between adjacent first electrode portions and second electrode portions, and the current directions of adjacent second electrode portions are the same or opposite.

[0018] In some optional embodiments, the outline shape of the magnetic tunnel junction includes any one of a circle, an ellipse or a parallelogram;

[0019] Wherein, when the outline shape of the magnetic tunnel junction is circular, there is at least one antiferromagnetic layer between the magnetic tunnel junction and the corresponding electrode portion;

[0020] When the contour shape of the magnetic tunnel junction is an ellipse or a parallelogram, the major axis direction of the ellipse or parallelogram is perpendicular to the current direction of the magnetic tunnel junction.

[0021] In some optional embodiments, the projection of the bottom electrode layer on the substrate covers the projection of the antiferromagnetic layer on the substrate;

[0022] And / or, the projection of the antiferromagnetic layer on the substrate covers the projection of the corresponding magnetic tunnel junction on the substrate.

[0023] A second aspect of an embodiment of the present application provides a method for preparing a magnetoresistive random access memory, comprising:

[0024] providing a substrate;

[0025] A bottom electrode layer is formed on the substrate; wherein the bottom electrode layer comprises at least two electrode parts connected in sequence, an angle is formed between two adjacent electrode parts, and the two adjacent electrode parts are not collinear;

[0026] At least two magnetic tunnel junctions are formed on the bottom electrode layer; each of the electrode portions has at least one magnetic tunnel junction;

[0027] When a write current is applied to the bottom electrode layer, one of the at least two magnetic tunnel junctions has a first resistance state, and the other of the at least two magnetic tunnel junctions has a second resistance state, so that the resistance between the at least two magnetic tunnel junctions forms a differential state.

[0028] In some optional embodiments, before forming at least two magnetic tunnel junctions on the bottom electrode layer, the method further includes:

[0029] At least one antiferromagnetic layer is formed on at least one of the electrode portions.

[0030] The magnetoresistive random access memory provided by the embodiment of the present application includes a substrate, a bottom electrode layer arranged on the substrate, and at least two magnetic tunnel junctions arranged on the bottom electrode layer; the bottom electrode layer includes at least two electrode parts connected in sequence, an angle is formed between two adjacent electrode parts, and the two adjacent electrode parts are not collinear, at least two magnetic tunnel junctions are arranged on the bottom electrode layer, and each electrode part on the bottom electrode layer has at least one magnetic tunnel junction, when a write current is applied to the bottom electrode layer, the magnetic tunnel junction on one electrode part has a first resistance state (for example, the first resistance state is a low resistance state or a high resistance state), and the magnetic tunnel junction on another electrode part adjacent to the electrode part has a first resistance state (for example, the first resistance state is a low resistance state or a high resistance state). It has a second resistance state (for example, the second resistance state is a median resistance state, that is, the value of the median resistance state is between the low resistance state and the high resistance state). In two adjacent electrode parts, no matter whether the magnetic tunnel junction on one of the electrode parts is in a low resistance state or a high resistance state, the magnetic tunnel junction on the other electrode part is always in a median resistance state, so that the resistance of the magnetic tunnel junctions on the two adjacent electrode parts can always form a differential state. In this way, as long as the magnetic tunnel junction on one electrode part is successfully written, the bit data can be successfully written, thereby improving the success rate of data writing, and then improving the reliability of data writing storage of the magnetoresistive random access memory. In addition, in the related art, the bottom electrode layer under the magnetic tunnel junction used as a data unit in the SOT-MRAM, and the bottom electrode layer under the magnetic tunnel junction used as a reference unit, are usually set separately. The present application sets the bottom electrode layer as at least two electrode parts connected in sequence, which can save the layout area compared with the related art.

[0031] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the magnetoresistive random access memory and the preparation method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic diagram of the structure of a magnetoresistive random access memory provided in an embodiment of the present application;

[0034] Figure 2A cross-sectional schematic diagram of a structure of a bottom electrode layer and a magnetic tunnel junction in a magnetoresistive random access memory provided by an embodiment of the present application;

[0035] Figure 3 A schematic diagram of a structure of a storage unit in a magnetoresistive random access memory provided in an embodiment of the present application;

[0036] Figure 4 for Figure 3 A schematic diagram of a state after a write current is applied to the bottom electrode layer;

[0037] Figure 5 Another schematic diagram of the structure of a storage unit in a magnetoresistive random access memory provided in an embodiment of the present application;

[0038] Figure 6 A partial cross-sectional schematic diagram of a structure of a storage unit in a magnetoresistive random access memory provided by an embodiment of the present application;

[0039] Figure 7 A partial cross-sectional schematic diagram of another structure of a storage unit in a magnetoresistive random access memory provided by an embodiment of the present application;

[0040] Figure 8 A schematic diagram of another structure of a storage unit in a magnetoresistive random access memory provided in an embodiment of the present application;

[0041] Fig. 9 A schematic diagram of another structure of a storage unit in a magnetoresistive random access memory provided in an embodiment of the present application;

[0042] Fig.10 A schematic diagram of another structure of a storage unit in a magnetoresistive random access memory provided in an embodiment of the present application;

[0043] Fig.11 A schematic flow chart of a method for preparing a magnetoresistive random access memory provided in an embodiment of the present application.

[0044] Reference numerals:

[0045] 10- Magnetoresistive random access memory;

[0046] 100 - memory cell; 120 - bottom electrode layer; 121 - electrode portion;

[0047] 121a-first electrode portion; 121b-second electrode portion;

[0048] 130 - magnetic tunnel junction; 130a - first magnetic tunnel junction; 130b - second magnetic tunnel junction;

[0049] 131 - free layer; 132 - barrier layer; 133 - reference layer; 134 - pinned layer; 135 - insertion layer;

[0050] 140-antiferromagnetic layer;

[0051] 150-transistor. DETAILED DESCRIPTION

[0052] According to the different data writing mechanisms, the development of magnetoresistive random access memory has undergone three generations of changes. Among them, the third generation magnetoresistive random access memory - spin-orbit torque magnetoresistive random access memory (Spin-orbit Torque MRAM, SOT-MRAM) has the advantages of non-volatility, high-speed and low-power data writing and high device durability. The basic storage unit structure of SOT-MRAM is to set a heavy metal layer (i.e., bottom electrode layer) at the adjacent position of the MTJ free layer to form a multilayer film structure of heavy metal layer, free layer, barrier layer and reference layer stacked in sequence. When current is applied to the heavy metal layer, the current flowing through the heavy metal layer can generate spin current, which can flip the magnetization direction of the free layer, thereby realizing the writing of bit data.

[0053] In the related art, SOT-MRAM includes at least a pair of magnetic tunnel junctions with opposite resistance states, wherein one of the magnetic tunnel junctions with opposite resistance states is a data unit and the other is a reference unit. When two write currents in opposite directions are applied to the data unit and the reference unit respectively, one of the two magnetic tunnel junctions is in a low resistance state and the other is in a high resistance state, and then a differential method is used for reading to achieve the writing of bit data. Whether the bit data can be successfully written depends on the successful writing of the data unit and the reference unit at the same time. For example, the successful writing of the data unit does not mean that the bit data is successfully written. Because the reference unit may have a large deviation between the current required for writing the reference unit and the current required for writing the data unit due to problems such as process uniformity and process quality, there is a technical problem that the data unit is successfully written but the reference unit is not successfully written, and the bit data is not successfully written, which leads to the low reliability of data writing storage.

[0054] In order to solve the above problems, the present application provides a magnetic tunnel junction and a preparation method thereof, wherein the magnetoresistive random access memory includes a substrate, a bottom electrode layer arranged on the substrate, and at least two magnetic tunnel junctions arranged on the bottom electrode layer; the bottom electrode layer includes at least two electrode portions connected in sequence, an angle is formed between two adjacent electrode portions, and the two adjacent electrode portions are not collinear, at least two magnetic tunnel junctions are arranged on the bottom electrode layer, and each electrode portion on the bottom electrode layer has at least one magnetic tunnel junction, when a write current is applied to the bottom electrode layer, the magnetic tunnel junction on one electrode portion has a first resistance state (for example, the first resistance state is a low resistance state or a high resistance state), the magnetic tunnel junction on another electrode portion adjacent to the electrode portion has a second resistance state (for example, the second resistance state is a median resistance state, that is, the value of the median resistance state is between the low resistance state and the high resistance state), and the adjacent In the two electrode parts, no matter whether the magnetic tunnel junction on one of the electrode parts is in a low resistance state or a high resistance state, the magnetic tunnel junction on the other electrode part is always in a median resistance state, so that the resistance of the magnetic tunnel junctions on the two adjacent electrode parts can always form a differential state. In this way, as long as the magnetic tunnel junction on one electrode part is successfully written, the bit data can be successfully written, thereby improving the success rate of data writing, and then improving the reliability of data writing storage in the magnetoresistive random access memory; in addition, in the related art, the bottom electrode layer under the magnetic tunnel junction used as a data unit in the SOT-MRAM, and the bottom electrode layer under the magnetic tunnel junction used as a reference unit, are usually set separately. The present application sets the bottom electrode layer as at least two electrode parts connected in sequence, which can save layout area compared with the related art.

[0055] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of this application.

[0056] Please refer to Figure 1As shown, an embodiment of the present application provides a magnetoresistive random access memory 10, which may include a plurality of memory cells 100, and the plurality of memory cells 100 may be arranged along rows and columns, or in other words, the plurality of memory cells 100 may be arranged in a matrix form. Among them, the memory cells 100 in the same row (or the same column) may be coupled to the same word line (word line, WL for short), and the memory cells 100 in the same column (or the same row) may be coupled to the same group of bit lines (bit line, BL for short) and source lines (source line, SL for short). In other words, the memory cell 100 may be a three-terminal device, and the memory cell 100 may include a first end coupled to the word line, a second end coupled to the bit line, and a third end coupled to the source line.

[0057] In the embodiment of the present application, the memory cell 100 includes a substrate, which can serve as a basic support structure of the memory cell 100, and can provide support for the structural layers stacked thereon. Exemplarily, the substrate can be a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon germanium substrate, a Germanium on Insulator (GOI) substrate, or a Silicon on Insulator (SOI) substrate, etc.

[0058] In some embodiments, please refer to Figure 1 As shown, the memory cell 100 further includes a bottom electrode layer 120 and at least two magnetic tunnel junctions 130 , wherein the bottom electrode layer 120 is disposed on the substrate; at least two magnetic tunnel junctions 130 are disposed on the bottom electrode layer 120 , and the bottom electrode layer 120 is electrically connected to the at least two magnetic tunnel junctions 130 .

[0059] In addition, each storage unit 100 has three transistors 150, the write transistor 150 connected to the bottom electrode layer 120 controls the application of the write current, and the data read transistor 150 connected to the top of each magnetic tunnel junction 130 reads the resistance state of each magnetic tunnel junction 130 and performs differential comparison to realize the writing of bit data.

[0060] In some embodiments, please refer to Figure 2 As shown, the magnetic tunnel junction 130 may include a free layer 131, a barrier layer 132, a reference layer 133 and a pinned layer 134 which are stacked in sequence. The free layer 131 is arranged close to the bottom electrode layer 120. The bottom electrode layer 120 is a spin-orbit torque layer which can generate a spin current when current flows through it to generate a torque and change the resistance state of the magnetic tunnel junction 130. The tunneling barrier layer 132 is located between the reference layer 133 and the free layer 131; the pinned layer 134 is arranged on the side of the reference layer 133 away from the barrier layer 132.

[0061] It should be noted that the pinning layer 134 is used to pin the magnetization direction of the reference layer 133 in a fixed direction.

[0062] The magnetic field direction of the reference layer 133 is fixed, while the magnetic field polarization direction of the free layer 131 can be changed. The barrier layer 132 separates the reference layer 133 from the free layer 131. Under the action of the electric field, electrons will tunnel through the barrier of the barrier layer 132 and vertically pass through the magnetic tunnel junction 130. The degree to which current can tunnel and the resistance of the magnetic tunnel junction 130 are determined by the relative magnetization direction between the free layer 131 and the reference layer 133.

[0063] The material forming the reference layer 133 and the free layer 131 may be a ferromagnetic material. For example, the material of the reference layer 133 and the free layer 131 may include at least one of cobalt (Co), iron (Fe), boron (B), nickel (Ni), ruthenium (Ru), iridium (Ir), and platinum (Pt). The material forming the barrier layer 132 may be an insulating material. For example, the material of the barrier layer 132 includes at least one of magnesium oxide (MgO), aluminum oxide (Al2O3), and silicon oxide (SiO2).

[0064] A metal layer or a non-metal layer may be inserted between the free layer 131 and the bottom electrode layer 120 to regulate the magnetic anisotropy of the free layer 131 or to regulate the Rashba effect between the interface of the free layer 131 and the bottom electrode layer 120 to reduce the write current power consumption.

[0065] In addition, an insertion layer 135 may be disposed between the free layer 131 and the barrier layer, between the barrier layer 132 and the reference layer 133 , or between the reference layer 133 and the pinned layer 134 to improve the performance of the magnetic tunnel junction 130 .

[0066] When the magnetic field direction of the free layer 131 is the same as that of the reference layer 133, the magnetic tunnel junction 130 is in a low resistance state (P state). When the magnetic field direction of the free layer 131 is opposite to that of the reference layer 133, the magnetic tunnel junction 130 is in a high resistance state (AP state).

[0067] Exemplarily, a storage unit 100 has two magnetic tunnel junctions 130, wherein one magnetic tunnel junction 130 is called a data unit and the other magnetic tunnel junction 130 is called a reference unit, wherein the magnetization direction of the free layer 131 in each magnetic tunnel junction 130 and the magnetization direction of the reference layer 133 are both in a parallel state or an antiparallel state, and when two write currents in opposite directions are applied to the data unit and the reference unit respectively, one magnetic tunnel junction 130 is in a low resistance state and the other magnetic tunnel junction 130 is in a high resistance state, and then the resistances of the two magnetic tunnel junctions 130 are read respectively, and the resistances of the two are compared, so as to achieve the writing of bit data through the differential comparison of the resistances between the two magnetic tunnel junctions 130. Therefore, the successful writing of a bit of data depends on the successful writing of the data unit and the reference unit at the same time, that is, one of the data unit and the reference unit is in a low resistance state and the other is in a high resistance state. If the writing of one of the data unit and the reference unit is unsuccessful (that is, when reading the resistance, the data unit and the reference unit are both in a high resistance state or a low resistance state), the writing of the bit data is unsuccessful.

[0068] Based on the above problems, in order to improve the success rate of bit data writing, in an embodiment of the present application, the bottom electrode layer 120 includes at least two electrode portions 121 connected in sequence, and there is an angle between two adjacent electrode portions 121, and the two adjacent electrode portions 121 are not collinear, that is, the angle between two adjacent electrode portions 121 is not 0° and 180°, and each electrode portion 121 has at least one magnetic tunnel junction 130; when a write current is applied to the bottom electrode layer 120, one of the at least two magnetic tunnel junctions 130 has a first resistance state, and the other of the at least two magnetic tunnel junctions 130 has a second resistance state, wherein the first resistance state and the second state are always in a differential state, that is, The first resistance state and the second resistance state are not equal, so that the magnetic tunnel junction 130 on two adjacent electrode portions 121 can achieve successful writing of bit data as long as the magnetic tunnel junction 130 on one electrode portion 121 is written successfully, thereby improving the success rate of data writing, and further improving the reliability of data writing storage of the magnetoresistive random access memory 10; in addition, in the related art, the bottom electrode layer under the magnetic tunnel junction used as a data unit in the SOT-MRAM, and the bottom electrode layer under the magnetic tunnel junction used as a reference unit, are usually separately arranged. The present application sets the bottom electrode layer as at least two electrode portions connected in sequence, which can save layout area compared with the related art.

[0069] In some embodiments, the first resistance state refers to the magnetization direction of the reference layer 133 in the magnetic tunnel junction 130 and the magnetization direction of the free layer 131 being parallel or antiparallel, and the first resistance state is a low resistance state or a high resistance state; the second resistance state refers to the magnetization direction of the reference layer 133 in the magnetic tunnel junction 130 and the magnetization direction of the free layer 131 being non-parallel or non-antiparallel, and the second resistance state is between the high resistance state and the low resistance state, that is, the second resistance state is a median resistance state, so that the resistance between the magnetic tunnel junctions 130 on two adjacent electrode portions 121 always forms a differential state, thereby achieving successful writing of bit data.

[0070] In some embodiments, please refer to Figure 3 As shown, two adjacent electrode portions 121 include a first electrode portion 121a and a second electrode portion 121b, and an angle is formed between the first electrode portion 121a and the second electrode portion 121b. Figure 3 In the embodiment, the first electrode portion 121a and the second electrode portion 121b are perpendicular to each other; at least two magnetic tunnel junctions 130 include a first magnetic tunnel junction 130a and a second magnetic tunnel junction 130b, the first magnetic tunnel junction 130a is arranged on the first electrode portion 121a, and the second magnetic tunnel junction 130b is arranged on the second electrode portion 121b; illustratively, the first magnetic tunnel junction 130a can be called a data unit, and the second magnetic tunnel junction 130b can be called a reference unit, and the data unit and the reference unit are consistent in the initial state after annealing, that is, in the first magnetic tunnel junction 130a and the second magnetic tunnel junction 130b, the magnetization direction of the free layer 131 and the magnetization direction of the reference layer 133 are both parallel or anti-parallel, then the resistance of the first magnetic tunnel junction 130a and the second magnetic tunnel junction 130b are both low resistance state or high resistance state, for example, in Figure 3 In the embodiment, the first magnetic tunnel junction 130a and the second magnetic tunnel junction 130b are both in a high resistance state.

[0071] When a write current is applied, the magnetization direction of the free layer 131 in the data unit is flipped, and the magnetization direction of the flipped free layer 131 is parallel or anti-parallel to the magnetization direction of the reference layer 133. The resistance state of the data unit before and after writing is switched between a low resistance state and a high resistance state, and the resistance state can be represented by a first resistance state; for example, Figure 4 In the example, the resistance state of the data unit before writing is a high resistance state, and the resistance state after writing is a low resistance state; in addition, Figure 3 and Figure 4In the embodiment, the first electrode portion 121a and the second electrode portion 121b are perpendicular to each other, and the current flowing through the first electrode portion 121a is perpendicular to the current direction flowing through the second electrode portion 121b. Therefore, the magnetization direction of the free layer 131 in the reference unit is perpendicular to the current direction of the second electrode portion 121b. At this time, the magnetization direction of the free layer 131 in the reference unit is flipped to a direction perpendicular to the magnetization direction of the reference layer 133. The specific flipping principle is that the write current flips the exchange bias coupling field of the free layer 131 to a direction perpendicular to the current through the SOT effect or the Oersted magnetic field, thereby flipping the magnetization direction of the free layer 131 to a direction perpendicular to the current. After the magnetization direction of the free layer 131 in the reference unit is flipped, the magnetization direction of the free layer 131 and the magnetization direction of the reference layer 133 are still perpendicular (presenting a non-parallel state or a non-anti-parallel state), that is, the resistance of the reference unit before and after writing is almost unchanged, and can be represented by the second resistance state (i.e., the median resistance state). Therefore, in Figure 4 In the embodiment, by comparing the resistances of the first magnetic tunnel junction 130a and the second magnetic tunnel junction 130b, the resistances between the first magnetic tunnel junction 130a and the second magnetic tunnel junction 130b are always in a differential state. The differential method is used to store one bit of data, and the writing of the bit data will not be affected by the success or failure of writing the second magnetic tunnel junction 130b (reference unit). As long as the writing of the first magnetic tunnel junction 130a (data unit) is successful, the bit data is written successfully, thereby improving the success rate of writing the bit data.

[0072] Of course, the angle between the first electrode portion 121a and the second electrode portion 121b may also be less than or greater than 90 degrees. Figure 5 In the embodiment, the angle between the first electrode portion 121a and the second electrode portion 121b is less than 90 degrees. Before and after the write current is applied, the magnetization direction of the free layer 131 in the first magnetic tunnel junction 130a and the magnetization direction of the reference layer 133 are always in a parallel or anti-parallel state, while the magnetization direction of the free layer 131 in the second magnetic tunnel junction 130b and the magnetization direction of the reference layer 133 have an angle. After the write current is applied, the magnetization direction of the free layer 131 is flipped and still has an angle with the magnetization direction of the reference layer 133. Therefore, the resistance value of the second magnetic tunnel junction 130b before and after writing is almost unchanged, presenting a second resistance state. In this way, in the process of writing bit data, as long as the first magnetic tunnel junction 130a is written successfully, the bit data is written successfully, thereby improving the success rate of bit data writing.

[0073] It should be noted that the resistance value of the reference unit will change with the change of the angle between the magnetization direction of the free layer 131 and the magnetization direction of the reference layer 133. However, as long as the angle between the magnetization direction of the free layer 131 and the magnetization direction of the reference layer 133 is not 0° and 180°, the resistance state of the reference unit is always between the low resistance state and the high resistance state, that is, it is always in the medium resistance state. Therefore, when the write current is applied, as long as the data unit is written successfully, the bit data is written successfully, thereby improving the success rate of bit data writing.

[0074] It can be seen that in the embodiment of the present application, as long as there is an angle between two adjacent electrode portions 121 and the two adjacent electrode portions 121 are not collinear, when writing bit data, it is only related to the success or failure of writing the magnetic tunnel junction 130 in the low resistance state or the high resistance state, and has nothing to do with the success or failure of writing the other magnetic tunnel junction 130 in the medium resistance state, thereby improving the success rate of bit data writing; in addition, by making the angle between two adjacent electrode portions 121, at least two magnetic tunnel junctions 130 are arranged on the same bottom electrode layer 120, so that the layout area can be saved and the storage density can be improved.

[0075] In some embodiments, please refer to Figure 6 and Figure 7 As shown in the figure, there is at least one antiferromagnetic layer 140 between at least one electrode portion 121 and the corresponding magnetic tunnel junction 130, so that an exchange bias coupling field can be formed between the antiferromagnetic layer 140 and the free layer 131 in the corresponding magnetic tunnel junction 130, so as to pin the magnetization direction of the free layer 131 in the corresponding magnetic tunnel junction 130 in one direction through the antiferromagnetic layer 140, thereby improving the stability of the magnetization direction of the free layer 131.

[0076] Among them, the exchange bias coupling field between the antiferromagnetic layer 140 and the free layer 131 of the magnetic tunnel junction 130 is greater than the coercive field of the free layer 131. In this way, the resistance of the free layer 131 in the corresponding magnetic tunnel junction 130 to external magnetic field interference can be improved, thereby improving the stability of the magnetization direction of the free layer 131, and further improving the success rate of bit data writing.

[0077] In an embodiment of the present application, an antiferromagnetic layer 140 is provided between the electrode portion 121 and the corresponding magnetic tunnel junction 130. Thus, the magnetization direction of the free layer 131 in the corresponding magnetic tunnel junction 130 can be pinned by the antiferromagnetic layer 140 to prevent the free layer 131 from changing under the stimulation of an external magnetic field, thereby improving the stability of data storage of the magnetoresistive random access memory 10.

[0078] It is understood that the exchange bias coupling field refers to the phenomenon that a unidirectional anisotropy is generated in a ferromagnetic material when a material containing a ferromagnetic or antiferromagnetic interface is cooled through the Neel temperature of the antiferromagnetic material in a magnetic field.

[0079] Coercive force, also known as coercive field or coercive force, is one of the characteristics of magnetic materials. It refers to the magnetic field strength required to reduce the magnetization intensity of the magnetic material to zero after it has been magnetized to magnetic saturation. Coercive force represents the ability of magnetic materials to resist demagnetization. It can be expressed by Hc, with units of A / m (International Standard System) or Oe (Gaussian System). Coercive force can be measured by a magnetometer or a BH analyzer.

[0080] In some embodiments, an antiferromagnetic layer 140 is provided between each electrode portion 121 and the corresponding magnetic tunnel junction 130. In this way, the magnetization direction of the free layer 131 in the corresponding magnetic tunnel junction 130 is pinned by each antiferromagnetic layer 140, thereby improving the stability of data storage. At the same time, each magnetic tunnel junction 130 and each antiferromagnetic layer 140 can be prepared synchronously, thereby reducing the preparation process and reducing the process cost.

[0081] In some embodiments, the projection of the bottom electrode layer 120 on the substrate covers the projection of the antiferromagnetic layer 140 on the substrate, and the projection of the antiferromagnetic layer 140 on the substrate covers the projection of the corresponding magnetic tunnel junction 130 on the substrate; in an exemplary embodiment, Figure 6 In the embodiment, the projection of the bottom electrode layer 120 on the substrate coincides with the projection of the antiferromagnetic layer 140 on the substrate, and the projection of the antiferromagnetic layer 140 on the substrate is larger than the projection of the magnetic tunnel junction 130 on the substrate. In this way, the antiferromagnetic layer 140 can be used as the bottom electrode layer 120, which reduces the distance between the bottom electrode layer 120 and the free layer 131 in the thickness direction of the substrate. When a write current is applied, the efficiency of the bottom electrode layer 120 in flipping the magnetization direction of the free layer 131 can be improved, thereby improving the writing efficiency of bit data. In another exemplary embodiment, in Figure 7 In the embodiment, the projection of the bottom electrode layer 120 on the substrate is larger than and coincides with the projection of the antiferromagnetic layer 140 on the substrate, and the projection of the antiferromagnetic layer 140 on the substrate coincides with the projection of the magnetic tunnel junction 130 on the substrate. Thus, the antiferromagnetic layer 140 is disposed between the bottom electrode layer 120 and the magnetic tunnel junction 130. When a write current is applied, the bottom electrode layer 120 has a high conductivity, so that it can quickly pass through the antiferromagnetic layer 140 to flip the magnetization direction of the free layer 131, thereby improving the writing efficiency of bit data.

[0082] In some embodiments, the material of the antiferromagnetic layer 140 includes but is not limited to one or more combinations of IrMn, PtMn, FeMn, PdMn, Mn3Sn, Mn3Pt, Mn3Ir, and Mn3Ge.

[0083] In some embodiments, please combine Figure 8 and Fig. 9 As shown, the bottom electrode layer 120 includes at least one first electrode portion 121a and at least two second electrode portions 121b, and the at least one first electrode portion 121a and the at least two second electrode portions 121b are alternately arranged in sequence, and there is an angle between adjacent first electrode portions 121a and second electrode portions 121b, and the current directions of adjacent second electrode portions 121b are the same or opposite. In this way, a storage unit 100 includes multiple magnetic tunnel junctions 130, which can further save space and improve storage density while increasing the bit data storage space.

[0084] An example, in Figure 8 In the embodiment, the bottom electrode layer 120 includes at least two first electrode portions 121a and at least two second electrode portions 121b, and the at least two first electrode portions 121a and the at least two second electrode portions 121b are alternately arranged in sequence, and the adjacent first electrode portions 121a and the second electrode portions 121b are perpendicular to each other, and the current directions of the two adjacent first electrode portions 121a are opposite. That is to say, there are multiple data units and multiple reference units on the bottom electrode layer 120, and the data unit is, for example, arranged on the first electrode portion 121a, and the reference unit is, for example, arranged on the second electrode portion 121b. Any differential storage can be performed between adjacent data units and reference units, and because the writing current directions of adjacent data units are opposite, one adjacent data unit is written in a low resistance state and the other is written in a high resistance state.

[0085] Another exemplary example is Fig. 9 In the embodiment, the bottom electrode layer 120 includes at least two first electrode portions 121a and at least two second electrode portions 121b, and the at least two first electrode portions 121a and at least two second electrode portions 121b are alternately arranged in sequence, and the adjacent first electrode portions 121a and the second electrode portions 121b are perpendicular to each other, and the current directions of the two adjacent first electrode portions 121a are the same, that is, there are multiple data units and multiple reference units on the bottom electrode layer 120, and the data unit is, for example, arranged on the first electrode portion 121a, and the reference unit is, for example, arranged on the second electrode portion 121b, and any differential storage can be performed between adjacent data units and reference units, and because the writing current directions of adjacent data units are the same, the adjacent data units are all in the same resistance state. In addition, when the reference unit adjacent to the data unit is damaged and cannot be used normally, the data unit can also be differentially stored with the reference unit at other positions, thereby improving flexibility.

[0086] In the embodiment of the present application, by setting multiple data units and multiple reference units on the same bottom electrode layer 120, adjacent data units and reference units are arbitrarily differentially stored, which improves the success rate of differential storage. In addition, it can improve space utilization and storage density.

[0087] In some embodiments, an antiferromagnetic layer 140 is disposed between each electrode portion 121 and the magnetic tunnel junction 130 thereon, so that the contour shape of the magnetic tunnel junction 130 is not limited to circular, elliptical, rectangular, square, etc.

[0088] In some embodiments, please combine Figures 3 to 5 , Figure 8 and Fig. 9 As shown, when the contour shape of the magnetic tunnel junction 130 is circular, there is at least one antiferromagnetic layer 140 between the magnetic tunnel junction 130 and the corresponding electrode portion 121, so that the magnetization direction of the free layer 131 in the circular magnetic tunnel junction 130 is pinned by the antiferromagnetic layer 140 to prevent the magnetization direction of the free layer 131 from being disturbed by the external magnetic field, thereby improving the stability of the magnetization direction of the free layer 131, thereby improving the stability of data storage.

[0089] In other embodiments, when the outline shape of the magnetic tunnel junction 130 is an ellipse or a parallelogram, the long axis direction of the ellipse or the parallelogram is perpendicular to the current direction of the magnetic tunnel junction 130; for example, Fig.10 As shown in , the contour shape of the magnetic tunnel junction 130 is an ellipse, and the long axis direction of the ellipse is perpendicular to the current direction of the magnetic tunnel junction 130. In this way, the resistance states of two adjacent magnetic tunnel junctions 130 can always be in a differential state, thereby improving the success rate of bit data writing, and further improving the reliability of data storage of the magnetoresistive random access memory 10.

[0090] Please refer to Fig.11 As shown, a second aspect of an embodiment of the present application provides a method for preparing a magnetoresistive random access memory, the method comprising:

[0091] Step S101: providing a substrate.

[0092] Step S102: forming a bottom electrode layer on the substrate; wherein the bottom electrode layer comprises at least two electrode parts connected in sequence, an angle is formed between two adjacent electrode parts, and the two adjacent electrode parts are not collinear.

[0093] Step S103: at least two magnetic tunnel junctions are formed on the bottom electrode layer; each electrode portion has at least one magnetic tunnel junction; wherein, when a write current is applied to the bottom electrode layer, one of the at least two magnetic tunnel junctions has a first resistance state, and the other of the at least two magnetic tunnel junctions has a second resistance state, so that the resistance between the at least two magnetic tunnel junctions forms a differential state.

[0094] When implementing it, please combine Figure 2As shown, first, a substrate may be formed by a deposition process. The substrate may be a semiconductor layer, and the material of the substrate may include silicon, germanium, silicon carbide, silicon germanium, germanium on insulator, or silicon on insulator.

[0095] After the substrate is formed, heavy metal materials are deposited on the substrate through a deposition process to form a bottom electrode layer 120 on the substrate, wherein the heavy metal materials include but are not limited to Pt, Pd, Hf, Au, AuPt, PtHf, PtCr, PtMn, IrMn, Ir, FeMn, NiMn, Ta, Ru, W, WO, WN, W(O, N), TaN, TaB, WTaB, etc., and can also be topological insulators such as BixSe1-x, BixSb1-x, (Bi, Sb)2Te3, or two-dimensional materials such as MoS2, WTe2, etc., or can be a multilayer film structure including two or more of the above materials.

[0096] After the bottom electrode is formed, an initial free layer, an initial barrier layer, an initial reference layer and an initial pinned layer can be deposited in sequence on the bottom electrode layer 120. The initial free layer, the initial barrier layer, the initial reference layer and the initial pinned layer stacked in sequence together form a magnetic tunnel junction. Afterwards, a hard mask layer is deposited on the magnetic tunnel junction 130, and the hard mask layer is patterned to form a hard mask structure. The magnetic tunnel junction is etched using the hard mask structure as a mask to form the magnetic tunnel junction 130.

[0097] In some embodiments, before forming at least two magnetic tunnel junctions 130 on the bottom electrode layer 120, the method further includes:

[0098] At least one antiferromagnetic layer 140 is formed on at least one electrode portion 121 .

[0099] For details, please combine Figure 6 and Figure 7 As shown, an antiferromagnetic layer 140 is formed on at least one electrode portion 121, and then a magnetic tunnel junction is formed on the antiferromagnetic layer 140. Then, when etching the magnetic tunnel junction, the etching can be stopped at the interface between the antiferromagnetic layer 140 and the free layer 131 (such as Figure 6 Alternatively, the etching may be stopped at the interface between the electrode portion 121 and the antiferromagnetic layer 140 (as shown in Figure 7 ), to form a magnetic tunnel junction 130 on the antiferromagnetic layer 140.

[0100] Afterwards, a dielectric protection layer is formed on the magnetic tunnel junction 130, the dielectric protection layer covers the exposed surface of the magnetic tunnel junction 130, and an interlayer dielectric layer is formed on the dielectric protection layer. Then, an electrode hole is formed on the interlayer dielectric layer, the electrode hole exposes the magnetic tunnel junction 130, and a metal conductive material is deposited in the electrode hole to form a top electrode.

[0101] The magnetoresistive random access memory provided by the embodiment of the present application includes a substrate, a bottom electrode layer arranged on the substrate, and at least two magnetic tunnel junctions arranged on the bottom electrode layer; the bottom electrode layer includes at least two electrode parts connected in sequence, an angle is formed between two adjacent electrode parts, and the two adjacent electrode parts are not collinear, at least two magnetic tunnel junctions are arranged on the bottom electrode layer, and each electrode part on the bottom electrode layer has at least one magnetic tunnel junction, when a write current is applied to the bottom electrode layer, the magnetic tunnel junction on one electrode part has a first resistance state (for example, the first resistance state is a low resistance state or a high resistance state), and the magnetic tunnel junction on another electrode part adjacent to the electrode part has a second resistance state (for example, the second resistance state is a median resistance state, that is, the value of the median resistance state is between the low resistance state and the high resistance state), and there is no magnetic tunnel junction between the two adjacent electrode parts. When the magnetic tunnel junction on one of the electrode portions is in a low resistance state or a high resistance state, the magnetic tunnel junction on the other electrode portion is always in a median resistance state, so that the resistances of the magnetic tunnel junctions on the two adjacent electrode portions can always form a differential state. In this way, as long as the magnetic tunnel junction on one electrode portion is successfully written, the bit data can be successfully written, thereby improving the success rate of data writing, and further improving the reliability of data writing storage in the magnetoresistive random access memory; in addition, in the related art, the bottom electrode layer under the magnetic tunnel junction used as a data unit in the SOT-MRAM, and the bottom electrode layer under the magnetic tunnel junction used as a reference unit, are usually separately arranged. The present application sets the bottom electrode layer as at least two electrode portions connected in sequence, which can save layout area compared with the related art.

[0102] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0103] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A magnetoresistive random access memory, characterized in that: include: A substrate, a bottom electrode layer disposed on the substrate, and at least two magnetic tunnel junctions disposed on the bottom electrode layer; The bottom electrode layer comprises at least two electrode parts connected in sequence, an angle is formed between two adjacent electrode parts, and the two adjacent electrode parts are not collinear; each electrode part has at least one magnetic tunnel junction; When a write current is applied to the bottom electrode layer, one of the at least two magnetic tunnel junctions has a first resistance state, and the other of the at least two magnetic tunnel junctions has a second resistance state, so that the resistance between the at least two magnetic tunnel junctions forms a differential state; Wherein, when the magnetization direction of the reference layer in the magnetic tunnel junction is parallel or antiparallel to the magnetization direction of the free layer, the magnetic tunnel junction has the first resistance state; When the magnetization direction of the reference layer in the magnetic tunnel junction is non-parallel or non-anti-parallel to the magnetization direction of the free layer, the magnetic tunnel junction has the second resistance state; There is at least one antiferromagnetic layer between at least one of the electrode portions and the magnetic tunnel junction corresponding thereto, and an exchange bias coupling field is formed between the antiferromagnetic layer and the free layer in the magnetic tunnel junction corresponding thereto.

2. The magnetoresistive random access memory according to claim 1, characterized in that: An exchange bias coupling field between the antiferromagnetic layer and the free layer of the magnetic tunnel junction is greater than a coercive field of the free layer.

3. The magnetoresistive random access memory according to claim 1, characterized in that: Two adjacent electrode portions are perpendicular to each other.

4. The magnetoresistive random access memory according to any one of claims 1 to 3, characterized in that: The bottom electrode layer comprises a first electrode portion and a second electrode portion, and the first electrode portion and the second electrode portion have the angle between them; The at least two magnetic tunnel junctions include a first magnetic tunnel junction and a second magnetic tunnel junction, the first magnetic tunnel junction is disposed on the first electrode portion, and the second magnetic tunnel junction is disposed on the second electrode portion.

5. The magnetoresistive random access memory according to any one of claims 1 to 3, characterized in that: The bottom electrode layer includes at least one first electrode portion and at least two second electrode portions, at least one first electrode portion and at least two second electrode portions are alternately arranged in sequence, there is the angle between adjacent first electrode portions and second electrode portions, and the current directions of adjacent second electrode portions are the same or opposite.

6. The magnetoresistive random access memory according to any one of claims 1 to 3, characterized in that: The outline shape of the magnetic tunnel junction includes any one of a circle, an ellipse or a parallelogram; Wherein, when the outline shape of the magnetic tunnel junction is circular, there is at least one antiferromagnetic layer between the magnetic tunnel junction and the electrode portion corresponding thereto; When the contour shape of the magnetic tunnel junction is an ellipse or a parallelogram, the major axis direction of the ellipse or parallelogram is perpendicular to the current direction of the magnetic tunnel junction.

7. The magnetoresistive random access memory according to any one of claims 1 to 3, characterized in that: The projection of the bottom electrode layer on the substrate covers the projection of the antiferromagnetic layer on the substrate; And / or, the projection of the antiferromagnetic layer on the substrate covers the projection of the corresponding magnetic tunnel junction on the substrate.

8. A method for preparing a magnetoresistive random access memory, characterized in that: include: providing a substrate; A bottom electrode layer is formed on the substrate; wherein the bottom electrode layer comprises at least two electrode parts connected in sequence, an angle is formed between two adjacent electrode parts, and the two adjacent electrode parts are not collinear; At least two magnetic tunnel junctions are formed on the bottom electrode layer; each of the electrode portions has at least one magnetic tunnel junction; Wherein, when a write current is applied to the bottom electrode layer, one of the at least two magnetic tunnel junctions has a first resistance state, and the other of the at least two magnetic tunnel junctions has a second resistance state, so that the resistance between the at least two magnetic tunnel junctions forms a differential state; Wherein, when the magnetization direction of the reference layer in the magnetic tunnel junction is parallel or antiparallel to the magnetization direction of the free layer, the magnetic tunnel junction has the first resistance state; When the magnetization direction of the reference layer in the magnetic tunnel junction is non-parallel or non-anti-parallel to the magnetization direction of the free layer, the magnetic tunnel junction has the second resistance state; There is at least one antiferromagnetic layer between at least one of the electrode portions and the magnetic tunnel junction corresponding thereto, and an exchange bias coupling field is formed between the antiferromagnetic layer and the free layer in the magnetic tunnel junction corresponding thereto.

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