Pixel structure, method for manufacturing pixel structure, and repairing method

Abstract

The application discloses a pixel structure, a preparation method and a repairing method of the pixel structure. The pixel structure comprises a thin film transistor, a pixel electrode layer, an organic flat layer, a common electrode layer and a first insulating layer. The pixel electrode layer comprises a first pixel electrode and a second pixel electrode. The pixel structure comprises a melting area and a fusion area. The thin film transistor and the first pixel electrode are arranged in the melting area. The common electrode layer and the second pixel electrode are arranged in the fusion area. The organic flat layer and the first insulating layer are arranged in the melting area and the fusion area. The organic flat layer is provided with a first hollow part corresponding to the fusion area. The common electrode layer and the second pixel electrode are arranged in the first hollow part. The thickness of the organic flat layer in the fusion area is smaller than that in the melting area. The thickness of the organic flat layer in the fusion area is changed, so that the shrinkage and collapse of the organic flat layer during laser irradiation are avoided, the pixel electrode is prevented from splashing during laser irradiation, and pixel dark point failure is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel structure, a preparation method and a repair method of the pixel structure. BACKGROUND

[0002] With the development of liquid crystal panel and the pursuit of high resolution, high refresh rate and high transmittance products by consumers, FFS (Fringe Field Switching) screen products are more and more favored. The thin film transistor array substrate of the existing FFS liquid crystal display device includes a plurality of gate lines, a plurality of data lines, a plurality of gate lines and a plurality of data lines arranged in a cross manner to define a plurality of pixel areas. The pixel area includes a pixel electrode and a common electrode formed by indium tin oxide (ITO), and a thin film transistor (TFT) disposed near the intersection of the data line and the gate line.

[0003] The thin film transistor is a switching element for applying or not applying voltage to the pixel electrode. In the production process of the liquid crystal display device, the thin film transistor is often contaminated by the manufacturing process or damaged by static electricity, so that the thin film transistor is abnormally short-circuited or open-circuited, or the pixel electrode and the common electrode in the pixel area are short-circuited due to the influence of conductive particles, so that the pixel cannot be normally displayed, thereby causing bright spots and dark spots of the pixel. When the bright spot occurs, laser is often used for repair, but the organic planar layer is easy to shrink and collapse, the pixel electrode and the common electrode are both made of ITO material, and it is difficult to realize laser welding, resulting in failure of pixel dark spot repair. SUMMARY

[0004] The purpose of the present application is to provide a pixel structure, a preparation method and a repair method of the pixel structure, and to improve the success rate of pixel dark spot repair.

[0005] The present application discloses a pixel structure, which comprises a thin film transistor and a pixel electrode layer, and further comprises an organic planar layer, a common electrode layer and a first insulating layer. The pixel electrode layer comprises a first pixel electrode and a second pixel electrode. The pixel structure comprises a fuse area and a welding area. The thin film transistor and the first pixel electrode are arranged in the fuse area, and the common electrode layer and the second pixel electrode are arranged in the welding area. The organic planar layer and the first insulating layer are arranged in the fuse area and the welding area, and the organic planar layer forms a first hollow part corresponding to the welding area. The common electrode layer and the second pixel electrode are arranged in the first hollow part, and the thickness of the organic planar layer in the welding area is less than the thickness of the organic planar layer in the fuse area.

[0006] Optionally, the pixel structure comprises a substrate and a first auxiliary conductive layer, the thin film transistor and the first auxiliary conductive layer are arranged on the substrate, the gate metal layer of the thin film transistor is arranged in the same layer with the first auxiliary conductive layer, the gate insulating layer of the thin film transistor extends to the fusion area and is hollowed out under the first hollow part, and the first auxiliary conductive layer is arranged under the first hollow part of the fusion area.

[0007] Optionally, the first auxiliary conductive layer comprises a first metal layer, and the first metal layer is formed by the same process as the gate metal layer of the thin film transistor.

[0008] Optionally, the length of the first metal layer in the extension direction of the gate insulating layer of the thin film transistor is greater than the length of the first hollow part.

[0009] Optionally, the first auxiliary conductive layer comprises indium tin oxide, and the first auxiliary conductive layer is arranged below the gate insulating layer of the thin film transistor under the first hollow part.

[0010] Optionally, the pixel structure further comprises a second auxiliary conductive layer, the second auxiliary conductive layer is arranged on the gate insulating layer extending to the fusion area and above the first auxiliary conductive layer.

[0011] Optionally, the second auxiliary conductive layer is formed of a metal material and formed by the same process as the source metal layer and the drain metal layer of the thin film transistor, the second auxiliary conductive layer comprises a first area and a second area, the first area is located under the first hollow part, and the length of the first area in the extension direction of the gate insulating layer of the thin film transistor is greater than the length of the second area.

[0012] Optionally, the pixel structure comprises a second insulating layer, the second insulating layer covers the thin film transistor, the second insulating layer extends from the fusion area to the fusion area, the drain metal layer of the thin film transistor extends to the fusion area, the second insulating layer in the fusion area is arranged on the drain metal layer in the fusion area, and the drain metal layer in the fusion area is located under the first hollow part.

[0013] The application also discloses a preparation method of a pixel structure, for preparing the pixel structure as described above, the pixel structure comprises a fusion area and a fusion area, and the preparation method comprises the following steps:

[0014] forming a thin film transistor on a first substrate;

[0015] forming an organic flat layer above the thin film transistor;

[0016] The organic flat layer is provided with a first hollow portion corresponding to the fusion area; and

[0017] forming a pixel electrode layer, a first insulating layer and a common electrode layer on the organic flat layer;

[0018] The thickness of the organic flat layer in the fusion area is less than the thickness of the organic flat layer in the fusing area.

[0019] Optionally, the step of forming a thin film transistor on the first substrate further comprises the following steps:

[0020] forming a first auxiliary conductive layer in the fusion area while forming the gate metal layer of the thin film transistor; and

[0021] forming a second insulating layer and a second auxiliary conductive layer after forming the source metal layer and the drain metal layer of the thin film transistor;

[0022] The first area of the second auxiliary conductive layer is located below the first hollow portion.

[0023] The application further discloses a repairing method of the pixel structure, which is used for repairing any one of the pixel structures as described above, and comprises the following steps:

[0024] providing any one of the pixel structures as described above; and

[0025] detecting whether the fusion area is abnormal, and if the fusion area is abnormal and causes the first pixel electrode in the pixel electrode layer to fail to effectively contact the thin film transistor, performing laser treatment on the second pixel electrode and the common electrode layer in the first hollow portion corresponding to the fusion area by using laser, so that the second pixel electrode and the common electrode layer are fused together;

[0026] The thickness of the organic flat layer in the fusion area is less than the thickness of the organic flat layer in the fusing area.

[0027] Optionally, in the first hollow portion, a second insulating layer and a first auxiliary conductive layer are arranged below the common electrode layer, and the step of detecting whether the fusion area is abnormal, and if the fusion area is abnormal and causes the first pixel electrode in the pixel electrode layer to fail to effectively contact the thin film transistor, performing laser treatment on the second pixel electrode and the common electrode layer in the first hollow portion corresponding to the fusion area by using laser, so that the second pixel electrode and the common electrode layer are fused together further comprises the following steps:

[0028] detecting whether the fusion area is abnormal, if the fusion area is abnormal, causing the first pixel electrode in the pixel electrode layer and the thin film transistor to be unable to effectively contact, using laser to cut off the connection between the source metal layer of the thin film transistor and the data line, and the connection between the drain metal layer of the thin film transistor and the first pixel electrode;

[0029] using laser to perform laser processing on the second pixel electrode and the common electrode layer in the first hollow part corresponding to the fusion area, so that the second pixel electrode and the common electrode layer are fused together at the first auxiliary conductive layer.

[0030] Compared with the scheme of fusing the pixel electrode and the common electrode on the organic flat layer, the pixel structure is divided into a fusion area and a fusion area in the present application, and the organic flat layer is provided with a first hollow part in the fusion area, that is, the organic flat layer is hollowed out in the fusion area, so that when the pixel electrode and the common electrode are fused, there is no need to worry about the shrinkage of the organic flat layer, which causes the pixel electrode to splash during laser processing, resulting in pixel dark point failure, improves the success rate of pixel dark point, thereby improving the yield of Oxide products. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings included to provide a further understanding of the embodiments of the present application, constitute a part of the specification, illustrate embodiments of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creating labor. In the drawings:

[0032] Figure 1 is a pixel structure schematic diagram of the first embodiment of the present application;

[0033] Figure 2 is a pixel structure schematic diagram of the second embodiment of the present application;

[0034] Figure 3 is a repair schematic diagram of the pixel structure of the second embodiment of the present application;

[0035] Figure 4 is a pixel structure schematic diagram of the third embodiment of the present application;

[0036] Figure 5 is a pixel structure schematic diagram of the fourth embodiment of the present application;

[0037] Figure 6 is a repair schematic diagram of the pixel structure of the fourth embodiment of the present application;

[0038] Figure 7is a pixel structure schematic diagram of a fifth embodiment of the present application;

[0039] Figure 8 is a preparation method flow chart of a pixel structure of a sixth embodiment of the present application;

[0040] Figure 9 is a repair method flow chart of a pixel structure of a seventh embodiment of the present application;

[0041] Figure 10 is a repair method flow chart of a pixel structure of an eighth embodiment of the present application.

[0042] Wherein, 100, pixel structure; 101, fuse area; 102, fusion area; 110, first substrate; 120, thin film transistor; 121, gate metal layer; 122, gate insulating layer; 123, source metal layer; 124, drain metal layer; 125, semiconductor layer; 130, pixel electrode layer; 131, first pixel electrode; 132, second pixel electrode; 140, organic flat layer; 141, first hollow part; 150, common electrode layer; 151, first via hole; 160, first insulating layer; 170, first auxiliary conductive layer; 171, first metal layer; 172, indium tin oxide; 180, second auxiliary conductive layer; 181, first area; 182, second area; 190, second insulating layer. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme of the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments of the present application.

[0044] In the description of the present application, the terms "first", "second" are only used for description purpose, and cannot be understood as indicating relative importance, or implying indicating the number of the indicated technical features. Therefore, unless otherwise specified, the features limited with "first", "second" can explicitly or implicitly include one or more of the features; the meaning of "multiple" is two or more. The term "include" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof can exist or be added.

[0045] In addition, the terms of orientation or positional relationship indicated by "center", "transverse", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are described based on the orientation or relative position relationship shown in the drawings, and are only for the convenience of the simplified description of the present application, and do not indicate that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0046] In addition, unless otherwise clearly specified and limited, the terms "mount", "connect", "connection" should be understood broadly, for example, can be fixed connection, can also be detachable connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, or the internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0047] The present application will be described in detail below with reference to the drawings and optional embodiments.

[0048] As shown in Figure 1 As a first embodiment of the present application, a pixel structure 100 is disclosed, which comprises a thin film transistor 120, a pixel electrode layer 130, an organic flat layer 140, a common electrode layer 150 and a first insulating layer 160; the pixel electrode layer 130 comprises a first pixel electrode 131 and a second pixel electrode 132, the pixel structure 100 comprises a fuse area 101 and a fusion area 102, the thin film transistor 120 and the first pixel electrode 131 are arranged in the fuse area 101, and the first pixel electrode 131 is connected with the drain metal layer 124 of the thin film transistor 120 through a via hole; the common electrode layer 150 and the second pixel electrode 132 are arranged in the fusion area 102, and the organic flat layer 140 and the first insulating layer 160 are arranged in the fuse area 101 and the fusion area 102, that is, the organic flat layer 140 is arranged in a whole layer, covering the fuse area 101 and the fusion area 102, and the first insulating layer 160 is also arranged in a whole layer, laid on the organic flat layer 140, covering the common electrode layer 150 at the same time, so as to insulate the second pixel electrode 132 from the common electrode layer 150.

[0049] Further, the organic flat layer 140 is formed with a first hollow part 141 corresponding to the fusion area 102; that is, the organic flat layer 140 is hollowed out in the fusion area 102, or the thickness is thinned, the organic flat layer 140 mainly adopts a resin material, and is formed using a PFA layer process; the common electrode layer 150 and the second pixel electrode 132 are arranged in the first hollow part 141, and the thickness of the organic flat layer 140 in the fusion area 102 is less than the thickness of the organic flat layer 140 in the fuse area 101; the organic flat layer 140 in the fusion area 102 is provided with the first hollow part 141 or a PFA via hole, that is, the organic flat layer 140 is thinned or directly removed in the fusion area, so that the problem of shrinkage and collapse of the organic flat layer 140 during laser fusion is not worried about, which is beneficial to improve the probability of successful fusion and break the limitation of pixel repair by PFA layer process.

[0050] As shown in Figure 2 and Figure 3 As a second embodiment of the present application, further refinement and improvement of the above-mentioned first embodiment, the pixel structure 100 includes a substrate and a first auxiliary conductive layer 170, the thin film transistor 120 and the first auxiliary conductive layer 170 are arranged on the substrate, the thin film transistor 120 includes a gate metal layer 121, a gate insulating layer 122, a semiconductor layer 125, a source metal layer 123 and a drain metal layer 124, and a second insulating layer 190 is usually arranged between the source metal layer 123, the drain metal layer 124 and the organic flat layer 140; the gate metal layer 121 of the thin film transistor 120 is arranged in the same layer with the first auxiliary conductive layer 170, the gate insulating layer 122 of the thin film transistor 120 extends to the fusion area 102 and is hollowed out under the first hollow part 141, the first auxiliary conductive layer 170 is arranged under the first hollow part 141 of the fusion area 102, the second pixel electrode 132 covers the first hollow part 141 and is connected with the first auxiliary conductive layer 170, that is, the organic flat layer 140, the gate insulating layer 122 and the second insulating layer 190 arranged between the first auxiliary conductive layer 170 and the common electrode layer 150 are all hollowed out and removed, the second pixel electrode 132 on the organic flat layer 140, the first insulating layer 160 and the common electrode layer 150 are all sunken into the first hollow part 141, and the common electrode layer 150 is directly connected with the first auxiliary conductive layer 170, so that the second pixel electrode 132 and the common electrode layer 150 are electrically connected on the first auxiliary conductive layer 170 during fusion.

[0051] Further, in order to improve the success probability of the connection between the second pixel electrode 132 and the common electrode layer 150, the first auxiliary conductive layer 170 is formed of a metal material, that is, the first auxiliary conductive layer 170 includes a first metal layer 171, and in order to facilitate the process and improve the preparation efficiency of the overall pixel structure 100, the first metal layer 171 and the gate metal layer 121 of the thin film transistor 120 are formed by the same process; and in order to avoid the influence of the first metal layer 171 on the aperture ratio of the pixel structure 100, the first metal layer 171 is usually arranged near the gate line and arranged in parallel with the gate line.

[0052] In addition, in the extension direction of the gate insulating layer 122 of the thin film transistor 120 to the fusion area 102, the length of the first metal layer 171 is greater than the length of the first hollow part 141, so as to avoid the formation of the fusion between the second pixel electrode 132 and the common electrode outside the first metal layer 171 during fusion, which causes the first metal layer 171 to fail to realize the communication between the pixel electrode and the common electrode; the embodiment adds a metal layer, so that the common electrode layer 150 is directly connected with the first auxiliary conductive layer 170 through the PFA via hole, the resistance of the common electrode in the common electrode layer 150 is reduced, which not only improves the uniformity of the common electrode potential in the common electrode layer 150, but also reduces the delay effect and avoids the poor crosstalk.

[0053] As shown in Figure 4 As a third embodiment of the present application, the first auxiliary conductive layer 170 includes indium tin oxide 172, and the first auxiliary conductive layer 170 is arranged below the gate insulating layer 122 of the thin film transistor 120 below the first hollow part 141, which is different from the second embodiment, and in consideration of the fusion area 102 in the display area, in order to avoid the first auxiliary conductive layer 170 shielding the light of the display area and affecting the aperture ratio, the first auxiliary conductive layer 170 is prepared and formed by using transparent indium tin oxide 172 (ITO), so as to avoid the loss of aperture ratio while improving the success probability of darkening.

[0054] As shown in Figure 5 and Figure 6 As a fourth embodiment of the present application, the pixel structure 100 further includes a second auxiliary conductive layer 180, the second auxiliary conductive layer 180 is arranged on the gate insulating layer 122 extending to the fusion area 102 and located above the first auxiliary conductive layer 170; in the extension direction of the gate insulating layer 122, the length (L1+L2) of the second auxiliary conductive layer 180 is less than the length L3 of the first auxiliary conductive layer 170, and the length of the first auxiliary conductive layer 170 is greater than the sum of the length L4 of the first hollow part and the length (L1+L2) of the second auxiliary conductive layer 180.

[0055] The second auxiliary conductive layer 180 is formed by a metal material, is formed by the same process as the source metal layer 123 and the drain metal layer 124 of the thin film transistor 120, and includes a first region 181 and a second region 182. The first region 181 is located below the first hollow part 141, and the length L1 of the first region 181 is greater than the length L2 of the second region 182 in the extension direction of the gate insulating layer 122 of the thin film transistor 120 to the fusion area 102. More metal material is close to the first hollow part 141, and the PFA layer is not present at the fusion position during pixel repair. The two metal layers can be melted, the amount of molten metal is increased, and the success rate of electrical connection between the second pixel electrode 132 and the common electrode layer 150 through the molten metal is increased. The disadvantages of the pixel with the PFA layer process cannot be darkened are improved, and the product yield is improved. In addition, the repair position is obviously different, and the auxiliary operator can quickly locate the repair position, and the operability of repair is improved. L1 needs to be greater than 0 to ensure that the process is made to exceed the PFA hole, that is, L1 is positive. The greater, the farther the fusion point from the PFA, the smaller the value of L4-L1 caused by the collapse of the PFA, which needs to be ensured to be able to etch the gate insulating layer and the second insulating layer by the PFA process, and to ensure the electrical connection between the electrode in the common electrode layer and the first metal layer.

[0056] As shown in Figure 7 The fifth embodiment of the present application is a further refinement and improvement of the first embodiment. Unlike the above-mentioned embodiments, the second insulating layer 190 is arranged on the thin film transistor 120 and extends from the fusion area 102 to the fusion area 102. The drain metal layer 124 of the thin film transistor 120 extends to the fusion area 102. The second insulating layer 190 in the fusion area 102 is arranged on the drain metal layer 124 in the fusion area 102. The drain metal layer 124 in the fusion area 102 is located below the first hollow part 141.

[0057] In this embodiment, a metal layer is not additionally arranged to increase the success rate of fusion between the pixel electrode and the common electrode at the fusion position. Instead, the drain metal layer 124 of the thin film transistor 120 is extended, that is, the length of the drain metal layer 124 is increased, so that part of the drain metal layer 124 is located directly below the common electrode layer 150, acting as a first auxiliary conductive layer 170. During fusion, the pixel electrode and the common electrode are connected to realize darkening.

[0058] As shown in Figure 8As shown, as the sixth embodiment of the present application, a preparation method of a pixel structure is disclosed, the preparation method is used for preparing the pixel structure as claimed in any one of the above embodiments, referring to Figure 1 、 Figure 3 、 Figure 5 、 Figure 6 and Figure 8 As shown, the pixel structure 100 includes a fusing area 101 and a fusion area 102, the preparation method includes the following steps:

[0059] S1: forming a thin film transistor on a first substrate;

[0060] S2: forming an organic flat layer above the thin film transistor;

[0061] S3: the organic flat layer corresponds to the fusing area to form a first hollow part; and

[0062] S4: forming a pixel electrode layer, a first insulating layer and a common electrode layer on the organic flat layer;

[0063] Wherein, the thickness of the organic flat layer 140 in the fusing area 102 is less than the thickness of the organic flat layer 140 in the fusing area 101.

[0064] This embodiment relates to a preparation method, in order to avoid the problem of shrinkage collapse caused by the thickness of the organic flat layer 140 in the fusing area being too thick, a first hollow part 141 is formed in the fusing area of the organic flat layer 140, the thickness of the organic flat layer 140 in the fusing area is reduced, the success rate of pixel darkening is improved, and the yield of oxide product is improved.

[0065] Further, in order to provide the success rate of fusion, the step S1 further includes the following steps:

[0066] Forming a first auxiliary conductive layer in the fusing area while forming the gate metal layer of the thin film transistor; and

[0067] Forming a second insulating layer and a second auxiliary conductive layer after forming the source metal layer and the drain metal layer of the thin film transistor;

[0068] Wherein, the first area 181 of the second auxiliary conductive layer 180 is located below the first hollow part 141.

[0069] In the FFS type liquid crystal display device with the organic planar layer 140PFA process, two layers of metal traces are newly added through a 7mask 2 etching process, the common electrode is directly connected with the first metal layer 171 trace through the PFA via hole, at the PFA via hole, the second auxiliary conductive metal layer is designed and shields half of the PFA hole; secondly, the pixel electrode layer 130 completely covers the via hole, the first metal layer 171, the second auxiliary conductive layer 180, the common electrode and the pixel electrode overlap to form a common overlapping area, without the thickest PFA layer, a dedicated fusion position is formed. When repairing, the two layers of metal can be melted, the molten metal is increased, thereby increasing the success rate of electrical connection between the pixel electrode layer 130 and the com electrode layer through the molten metal, and the disadvantage that the pixel cannot be darkened in the PFA layer process is improved.

[0070] As shown in Figure 9 , as a seventh embodiment of the present application, a pixel structure 100 repair method is disclosed, the repair method comprising the following steps:

[0071] I: providing a pixel structure as described in any of the above embodiments;

[0072] II: detecting whether the fusion area is abnormal, if the fusion area is abnormal, causing the first pixel electrode in the pixel electrode layer and the thin film transistor to fail to effectively contact, laser processing is performed on the second pixel electrode and the common electrode layer in the first hollow part corresponding to the fusion area, so that the second pixel electrode and the common electrode layer are fused together;

[0073] Among them, the thickness of the organic planar layer in the fusion area is less than the thickness of the organic planar layer in the fusion area.

[0074] Referring to Figure 2 , Figure 3 and Figure 9 , the organic planar layer 140 is thinned at the position of the fusion area 102, or the organic planar layer 140 is directly removed, whether the pixel structure 100 is darkened by detecting whether the fusion area 102 is abnormal; if the fusion area 102 is abnormal, it can be judged that the first pixel electrode 131 and the thin film transistor 120 appear connection abnormality, laser processing is performed on the second pixel electrode 132 and the common electrode layer 150 in the first hollow part 141 corresponding to the fusion area 102, so that the second pixel electrode 132 and the common electrode layer 150 are fused together, realizing the darkening of the pixel structure 100.

[0075] Further, as shown in Figure 10 , as an eighth embodiment of the present application, it is a further refinement and improvement of the above-mentioned seventh embodiment, referring to 2、 Figure 3 and Figure 10As shown, the second insulating layer 190 and the first auxiliary conductive layer 170 are arranged below the common electrode layer 150 in the first hollow part 141, and the step II further includes the following steps:

[0076] II1: detecting whether the fusion zone is abnormal, if the first pixel electrode in the pixel electrode layer and the thin film transistor cannot be effectively contacted due to the abnormality of the fusion zone, the connection between the source metal layer of the thin film transistor and the data line and the connection between the drain metal layer of the thin film transistor and the first pixel electrode are cut off by laser;

[0077] II2: laser processing the second pixel electrode and the common electrode layer corresponding to the first hollow part in the fusion zone by laser, so that the second pixel electrode and the common electrode layer are fused together at the first auxiliary conductive layer.

[0078] By arranging the first auxiliary conductive layer 170 formed of metal material, i.e. the common wiring, at the fusion position, the second pixel electrode 132 and the common electrode layer 150 are fused together at the first auxiliary conductive layer 170 after laser processing, i.e. the pixel electrode and the common electrode are connected through the first auxiliary conductive layer 170; specifically, the connection between the drain metal layer 124 of the thin film transistor 120 of the defective pixel and the pixel electrode is cut off by laser; the connection between the source metal layer 123 and the data line is cut off; laser fusion is performed at the fusion position to connect the pixel electrode and the common electrode to the common wiring, so that the pixel electrode and the common electrode have equal potential, and a constant black point is repaired.

[0079] Further, a second auxiliary conductive metal layer is designed to shield half of the PFA hole; secondly, the pixel electrode layer 130 completely covers the via hole, forming a common overlapping area formed by the overlapping of the first metal layer 171, the second auxiliary conductive layer 180, the common electrode in the common electrode layer 150 and the pixel electrode in the pixel electrode layer 130, without the thickest PFA layer, forming a dedicated fusion position. When repairing, the two metal layers can be melted to increase the amount of molten metal, thereby increasing the success rate of electrical connection between the pixel electrode layer 130 and the com electrode layer through the molten metal, and improving the disadvantage that the pixel with the PFA layer process cannot be darkened.

[0080] It should be noted that the limitations of each step involved in the present scheme do not limit the order of the steps without affecting the implementation of the specific scheme, the steps written in the front can be executed first, or executed later, or even executed at the same time, as long as the scheme can be implemented, it should be considered as belonging to the protection scope of the present application.

[0081] The technical solutions of the present application can be widely used in various display panels, such as TN (Twisted Nematic) display panels, IPS (In-Plane Switching) display panels, VA (Vertical Alignment) display panels, MVA (Multi-Domain Vertical Alignment) display panels, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panels, Mini / micro LED display panels, etc. The above-mentioned display panels are only commonly used, and in some other display panels, as long as the pixel structure of the present application is used, it also belongs to the protection scope of the present application.

[0082] Finally, it should be pointed out that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel structure, comprising a thin-film transistor and a pixel electrode layer, characterized in that, The pixel structure further includes an organic planarization layer, a common electrode layer, and a first insulating layer; the pixel electrode layer includes a first pixel electrode and a second pixel electrode, the pixel structure includes a fused region and a welded region, the thin film transistor and the first pixel electrode are disposed in the fused region, the common electrode layer and the second pixel electrode are disposed in the welded region, the organic planarization layer and the first insulating layer cover and are disposed in the fused region and the welded region, and the organic planarization layer has a first cutout portion corresponding to the welded region; The common electrode layer and the second pixel electrode are disposed in the first hollow portion, and the thickness of the organic planarization layer in the fusion zone is less than the thickness of the organic planarization layer in the fusion break zone. The pixel structure includes a substrate and a first auxiliary conductive layer. The thin film transistor and the first auxiliary conductive layer are both disposed on the substrate. The gate metal layer of the thin film transistor is disposed in the same layer as the first auxiliary conductive layer at a distance. The gate insulating layer of the thin film transistor extends toward the fusion region and is hollowed out under the first hollowed-out portion. The first auxiliary conductive layer is disposed under the first hollowed-out portion of the fusion region.

2. The pixel structure as described in claim 1, characterized in that, The first auxiliary conductive layer includes a first metal layer, which is formed by the same process as the gate metal layer of the thin-film transistor. In the direction in which the gate insulating layer of the thin-film transistor extends toward the fusion region, the length of the first metal layer is greater than the length of the first cutout portion.

3. The pixel structure as described in claim 1, characterized in that, The first auxiliary conductive layer comprises indium tin oxide and is disposed below the gate insulating layer of the thin-film transistor located below the first cutout.

4. The pixel structure as described in claim 2 or 3, characterized in that, The pixel structure further includes a second auxiliary conductive layer, which is disposed on the gate insulating layer extending to the fusion region and located above the first auxiliary conductive layer; The second auxiliary conductive layer is formed of a metal material and is formed using the same process as the source metal layer and drain metal layer of the thin film transistor. The second auxiliary conductive layer includes a first region and a second region. The first region is located below the first cutout portion. In the direction of extension of the gate insulating layer of the thin film transistor toward the fusion region, the length of the first region is greater than the length of the second region.

5. A method for fabricating a pixel structure, used to fabricate the pixel structure as described in any one of claims 1-4, characterized in that, The pixel structure includes a fused region and a fused region, and the fabrication method includes the following steps: Thin-film transistors are formed on the first substrate; An organic planarization layer is formed above the thin-film transistor; The organic planarization layer has a first perforation corresponding to the weld area; and A pixel electrode layer, a first insulating layer, and a common electrode layer are formed on an organic planarization layer; The thickness of the organic planarization layer in the weld zone is less than the thickness of the organic planarization layer in the break zone.

6. The method for fabricating a pixel structure as described in claim 5, characterized in that, The step of forming a thin-film transistor on the first substrate further includes the following steps: While forming the gate metal layer of the thin-film transistor, a first auxiliary conductive layer is formed in the fusion region; and After forming the source metal layer and drain metal layer of the thin-film transistor, a second insulating layer and a second auxiliary conductive layer are formed. The first region of the second auxiliary conductive layer is located below the first hollowed-out portion.

7. A method for repairing pixel structures, used to repair the pixel structure as described in any one of claims 1-4, characterized in that, Includes the following steps: Provide a pixel structure as described in any one of claims 1-4; and If the welding area is abnormal, and the first pixel electrode in the pixel electrode layer cannot make effective contact with the thin film transistor, a laser is used to laser process the second pixel electrode and the common electrode layer corresponding to the first hollow part in the welding area, so that the second pixel electrode and the common electrode layer are welded together. The thickness of the organic planarization layer in the weld zone is less than the thickness of the organic planarization layer in the break zone.

8. The pixel structure repair method as described in claim 7, characterized in that, Within the first hollow portion, a second insulating layer and a first auxiliary conductive layer are disposed below the common electrode layer. The step of detecting whether the welding area is abnormal, and if an abnormality occurs, causing the first pixel electrode in the pixel electrode layer to fail to effectively contact the thin-film transistor, involves using a laser to perform laser treatment on the second pixel electrode and the common electrode layer corresponding to the welding area within the first hollow portion, thereby fusing the second pixel electrode and the common electrode layer together. This step further includes the following steps: If the weld area is abnormal, and the first pixel electrode in the pixel electrode layer cannot make effective contact with the thin film transistor, a laser is used to cut off the connection between the source metal layer of the thin film transistor and the data line, as well as the connection between the drain metal layer of the thin film transistor and the first pixel electrode. A laser is used to laser process the second pixel electrode and the common electrode layer corresponding to the first hollow part in the fusion area, so that the second pixel electrode and the common electrode layer are fused together at the first auxiliary conductive layer.

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