A DDR host DQS gate control circuit

Abstract

The present invention discloses a DDR host DQS gate control circuit, belonging to the technical field of DQS gate control circuits. The control circuit adopts a method of delaying dfi_rddata_en by an integer cycle plus a fractional cycle, and a control signal gate_close_extend controls whether to extend the positive level of the delayed dfi_rddata_en by half a cycle. The present invention makes the distance between the opening and closing of the gate logic and the DQS clock edge programmable, which can be up to 1 / 2 cycle, so as to tolerate greater changes in round-trip delay and greatly reduce the frequency of retraining; even if the system changes greatly and needs to be retrained, the gate logic searches for a fast algorithm, which can spend very little time and reduce the occupation of effective bandwidth.

Description

Technical Field

[0001] The invention belongs to the technical field of gate control circuits, and in particular relates to a DDR host DQS gate control circuit. Background Art

[0002] The demand for storage bandwidth in contemporary SoC (System-On-Chip) is increasing. The single-bit rates of DDRn and LPDDRn are increasing. HBM expands the data bit width and also increases the single-bit rate, so the clock frequency is also increasing. Figure 1 As shown. In high-speed bidirectional source synchronous systems such as DDR, LPDDRn, and HBM, the memory returns data (DQ) and its accompanying clock 100 (DQS). DQS (Data Strobe) is a bidirectional signal. When neither the SoC nor the memory drives it, that is, before the preamble 102 and after the postamble 103, DQS is in a tri-state, and is affected by noise and electromagnetic radiation to form glitches 101. Once the host regards it, especially the glitches and noise before the preamble, as the real DQS, it will cause a read error.

[0003] To solve this problem, the host uses a gate circuit to shield the glitches and noise before the preamble and after the postamble. If the gate is opened too early, the glitches before the preamble will be included. Figure 2 If the gate is opened too late, after the first real DQS rising edge, the complete DQS will not be obtained. Figure 3 Therefore, the gate is opened during the preamble period and closed during the postamble period, as shown in Figure 4 However, due to the unknown host IO delay and board-level wiring delay, only an approximate range is known, and the memory parameter tDQSCK also specifies only a range. Therefore, the arrival time of the first real DQS rising edge at the SoC is unknown, that is, the round-trip delay is unknown, as shown in Figure 1. Figure 5As shown in the figure, as the frequency continues to increase, the round-trip delay can be as long as several cycles. The unknown round-trip delay is the first problem that the DDR host system needs to solve. The SoC needs to calculate this time, then generate the correct gate signal and provide time information for PHY_CLK to read data from FIFO.

[0004] There are two ways to generate gate logic. One is to simply delay dfi_rddate_en by an integer cycle plus a fractional cycle. The maximum margin between the opening and closing of the gate logic and the clock edge is only 1 / 4 clock cycle. Figure 4 As shown. Once the round-trip delay changes by more than 1 / 4 cycle, it will cause read data errors. In another case, the gate opening logic also delays dfi_rddata_en by an integer cycle plus a fractional cycle, but the gate closing logic counts the clean DQS cycle in the clean DQS clock domain after the gate filtering. On the last falling edge of the clean DQS, the gate opening logic and the gate closing logic perform an "or" to obtain the final gate signal, and the final gate signal then acts on the dirty DQS to obtain the clean DQS. Its timing waveform is shown as follows Figure 6 As shown in the figure, it can be seen that in such a structure, the closing time of the DQS gate signal follows the change of the round-trip delay, but the logic needs to be added to the clean DQS, and there is a combination feedback loop.

[0005] In the search algorithm, generally Figure 7As shown, a linear search is adopted, and a certain step, such as 1 / 8 cycle, is used to increase the delay of the gate signal, where Gate (n-1) represents the gate signal generated by the nth setting, and the rising edge of the gate signal is used to sample DQS until a change from 0 to 1 occurs. This edge may be a glitch or noise before the preamble. The gate signal needs to continue to increase the delay, and the width of the positive level is measured to determine whether it is a true DQS rising edge. Assuming that the round-trip delay is 2.5 cycles, a total of 2.5*8=16 times are required, and each time the gate signal delay sampling DQS is changed, a read command needs to be initiated, resulting in a relatively long search time. 1 / 8 cycle is still a relatively rough setting, and in order to improve the accuracy, a longer time is required. When the temperature and voltage of the SoC drift and need to be retrained, the gate signal training takes a long time, which means that more time is occupied for normal reading and writing, resulting in a reduction in effective bandwidth. Summary of the invention

[0006] The purpose of the present invention is to provide a DDR host DQS gate control circuit, which adopts a simple gate logic, but makes programmable logic for whether to extend the high-level half cycle of the gate logic. If the extension is configured to 1, a larger margin (1 / 2 cycle) can be reserved for the distance from the opening and closing of the gate logic to the clock edge to cope with large changes in the round-trip delay; at the same time, a novel algorithm is used to reduce the search time, so that when the voltage and temperature of the SoC drift and need to be retrained, the gate training time is reduced, so that its occupancy of the effective bandwidth is as small as possible, so as to solve the problems raised in the above-mentioned background technology.

[0007] To achieve the above object, the present invention provides the following technical solutions: A DDR host DQS gate control circuit adopts a method of delaying dfi_rddata_en by an integer cycle plus a fractional cycle, and a control signal gate_close_extend controls whether to extend the positive level of the delayed dfi_rddata_en by half a cycle;

[0008] Among them, the integer cycle delay is realized by the shift register, and the programmable signal gate_coarse_delay selects the dfi_rddata_en of a certain cycle delay to latch it into the DFF; and the first half cycle delay gate_fine_delay of the fractional cycle is realized by the falling edge triggered DFF, and the remaining second half cycle is realized by the delay line Gate DLL combined with the control signal gate_fine_delay.

[0009] Preferably, the control signal gate_close_extend is set to 1 to extend the distance from the gate signal opening and closing to the clock edge to 1 / 2 cycle; at this time, the gate logic is closed at the node where the post-order / post-leading ends, and a half-cycle margin is reserved for the increase of the round-trip delay;

[0010] If the round-trip delay is shortened, even if the glitches and noise after the post-sequence / post-lead are included, for the method of using FIFO to handle the cross-clock domain of DQS and PHY_CLK, when the lag time of PHY_CLK read FIFO is not large compared to DQS write FIFO, there is no impact on the function.

[0011] Preferably, the DQS is sent to DQS_DLL through the IO module, wherein DQS_DLL is an existing module, and its coverage range is 1 cycle, and in functional mode, it is used to delay DQS by 1 / 4 cycle to sample DQ;

[0012] In the measurement phase, the fractional cycle part of the phase difference between DQS and PHY_CLK is measured first. The initial value of DQS_DLL is set to 0, the gate is set to 1, and the measurement state machine initiates a long read. After waiting for a programmable cycle, it starts to use PHY_CLK to measure the phase of DQS. The specific measurement process includes:

[0013] From the highest bit to the nth bit of DQS_DLL, set it to 1, wait for DQS to stabilize before sampling, and set it to 0 or 1 according to the sampling result; then, use an 8-bit unsigned number E[7:0] to represent 1 cycle. According to the lock value L[7:0] of the main delay line, it can be determined that the lower bits of E from the nth bit down do not affect the accuracy of delay line control; perform the first 1 operation on L-1 to obtain the binary digit m required for L, and subtract m from 7 to get this n; finally, the delayed DQS will be aligned with the PHY_CLK edge, and the value a of DQS_DLL is recorded;

[0014] Wherein, a is an 8-bit unsigned number, which means that DQS is aligned with the rising edge of PHY_CLK after a fractional delay of a. It can be inferred that PHY_CLK is aligned with the rising edge of DQS after a fractional delay of -a.

[0015] Preferably, it also includes measuring the integer cycle portion of the round trip delay, and the specific measurement process includes:

[0016] Switch to function delay control, set the DQS_DLL delay to b, where b is 1 / 4 cycle, switch the normally open gate signal to function gate control, and set rd_coarse_delay to 0; then, set rd_fine_delay[7:0] to ~a-(h40<<gce)+b, set gce to 1, the opening of the gate logic is at the place of half a cycle before the first rising edge, set gce to 0, and the opening of the gate logic is at the place of 1 / 4 cycle before the first rising edge;

[0017] Initiate a read MPR instruction. If the data matches the expected value, stop and record the value of rd_coarse_delay. Otherwise, increment rd_coarse_delay and initiate the read MPR instruction again until the data matches the expected value.

[0018] Preferably, it further includes another more delicate way to measure the integer cycle part of the round-trip delay. The specific measurement process includes:

[0019] First, write the 16-bit data sequence h0000, h0001, h0002,..., h0007 into a row of the memory in sequence. In the function mode, set rd_coarse_delay to the value S. When the first byte T read is the difference between the set value S and the correct value, set S-T back to rd_coarse_delay. When the set gate opening time rd_coarse_delay is 2 cycles later than the set value, a byte h0002 is read. Subtract 2 from the set rd_coarse_delay and set it back to obtain the correct rd_coarse_delay.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] In the present invention, the distances between the opening and closing of the gate logic and the DQS clock edge are made programmable, up to 1 / 2 cycle at most, so as to be able to tolerate larger variations in the round-trip delay, and can greatly reduce the frequency of retraining. Even when the system changes greatly and retraining is required, the fast algorithm for searching the gate logic can spend very little time and reduce the occupation of the effective bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a timing waveform diagram of the accompanying clock DQS, preamble / lead-in, and postamble / trailer on the on-chip system communication architecture.

[0023] Figure 2 It is a waveform diagram of the preamble / lead-in and the previous glitch when the gate opens too early.

[0024] Figure 3 The accompanying clock DQS waveform is shown when the gate is opened too late.

[0025] Figure 4 The accompanying clock DQS waveform diagram is a diagram in which the gate is opened during the preceding / leading period and closed during the succeeding / post-leading period.

[0026] Figure 5 Schematic diagram of the round trip operation of the companion clock DQS in the system-on-chip communication architecture.

[0027] Figure 6 This is the timing waveform diagram of the gate opening logic and gate closing logic acting on the gate signal.

[0028] Figure 7 This is the waveform of the DQS gate signal round-trip delay search algorithm.

[0029] Figure 8 It is a gate logic circuit diagram in the functional mode of the present invention.

[0030] Fig. 9 This is a waveform diagram of the distance between the gate signal opening and closing and the clock edge after expansion.

[0031] Fig.10 It is an exploded view of the DQS and DQ modules of the present invention.

[0032] Fig.11 This is a waveform diagram showing the phase measurement of DQS by PHY_CLK of the present invention.

[0033] Fig.12 This is a diagram of the DQS and PHY_CLK edge alignment of the present invention.

[0034] Fig.13 FIG. 4 is a diagram showing the alignment of the fractional delay of PHY_CLK and the rising edge of DQS of the present invention.

[0035] Fig.14 This is a flow chart of the fractional period measurement of the present invention.

[0036] Fig.15 This is a flow chart of integer cycle measurement of the present invention.

[0037] Fig.16 This is a waveform diagram of the gate opening time rd_coarse_delay set in the present invention. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] like Figure 1-Figure 2 As shown, a DDR host DQS gate control circuit adopts a method of delaying dfi_rddata_en by an integer cycle plus a fractional cycle, and the control signal gate_close_extend controls whether to extend the positive level of the delayed dfi_rddata_en by half a cycle;

[0040] Among them, the integer cycle delay is realized by the shift register, and the programmable signal gate_coarse_delay selects the dfi_rddata_en of a certain cycle delay to latch it into the DFF; and the first half cycle delay gate_fine_delay of the fractional cycle is realized by the falling edge triggered DFF, and the remaining second half cycle is realized by the delay line Gate DLL combined with the control signal gate_fine_delay.

[0041] Specifically, the gate logic (Func Gate) in the functional mode is as follows: Figure 8 As shown, the method of delaying dfi_rddata_en by an integer cycle plus a fractional cycle is adopted, and the control signal gate_close_extend controls whether the positive level of the delayed dfi_rddata_en is extended by half a cycle. The integer cycle delay is implemented by the shift register 200, and the programmable signal gate_coarse_delay selects a dfi_rddata_en delayed by a certain cycle and latches it into DFF 1 202. The first half cycle of the fractional cycle is delayed by gate_fine_delay[7] and is implemented by DFF 2 203 triggered by the falling edge. The remaining second half cycle is implemented by the delay line 206 (Gate DLL) combined with the control signal gate_fine_delay[6:0]. The signal gate_close_extend is set to 1, which can expand the distance from the gate (Gate) signal opening and closing to the clock edge to 1 / 2 cycle, as shown in FIG. Fig. 9As shown. It can be seen that at this time, the closure of the gate logic is already at the end of the postamble, leaving enough margin for half a cycle for the increase of the round-trip delay. If the round-trip delay is shortened, even if the burrs and noise after the postamble are circled, for the method of using FIFO to process DQS and PHY_CLK across clock domains, if the PHY_CLK read FIFO is not much behind the DQS write FIFO, there will be no impact on the function. The DQS caused by the burrs and noise will make the write pointer continue to move forward, and invalid garbage data will also enter the FIFO, but the number of times PHY_CLK reads data is based on the length of dfi_rddata_en. After the valid data is read, the read and write pointers can be reset immediately.

[0042] Based on the modular concept, DQS and DQ are divided into several modules. Fig.10 As shown, DQS is sent to the data sampling delay unit 300 (DQS DLL) through the IO module. This data sampling delay unit 300 (DQS DLL) is an existing module, which covers 1 cycle. In the functional mode, its function is to delay DQS by 1 / 4 cycle to sample DQ. In the measurement phase, the phase difference between DQS and PHY_CLK (fractional cycle part) is measured first, the initial value of DQS_DLL is set to 0, the gate 301 is set to 1 (normally open), and the measurement state machine 303 (Measure FSM) initiates a long read (read any row of the memory Memory), waits for a programmable cycle (avoid preamble), such as 8 cycles, thereby avoiding the preamble, as shown in Fig.11 As shown, PHY_CLK is used to measure the phase of DQS. From the highest bit to the nth bit of DQS_DLL, set it to 1, wait for DQS to stabilize, sample, and set it to 0 or 1 according to the sampling result. Among them, the low bits below the nth bit have no effect on the accuracy and do not need to be paid attention to. Use an 8-bit unsigned number E[7:0] to represent 1 cycle. According to the lock value L[7:0] of the master delay line (Master DLL), it can be determined that the low bits of E below the nth bit do not affect the accuracy of the delay line control. Perform the leading one operation on L-1 to get the number of binary bits m required for L. Subtract m from 7 to get this n. As shown Fig.12As shown, assuming the main delay line lock value is d19, it can be obtained that the lower bits below the 3rd bit do not affect the accuracy. Finally, the delayed DQS will be aligned with the PHY_CLK edge, and the value a of DQS_DLL is recorded. Here, a is an 8-bit unsigned number, representing that DQS is aligned with the rising edge of PHY_CLK after a fractional delay with a value of a, as Fig.13 shown. It can be deduced that PHY_CLK is aligned with the rising edge of DQS after a fractional delay with a value of ~a (a bitwise inversion of a). The flowchart of fractional period measurement is as Fig.14 shown.

[0043] Then measure the integer period part of the Round-Trip Delay. Switch to the functional delay control 305 (Func DLYC), set the DQS_DLL delay to b (usually 1 / 4 cycle, i.e., h40). The normally open gate signal switches to the functional gate control 304 (Func Gate), set rd_coarse_delay to 0, use the abbreviation gce to represent gate_close_extend, then set rd_fine_delay[7:0] to ~a - (h40 << gce) + b, set gce to 1, and the opening of the Gate logic is at h80 (half cycle) before the first rising edge, set gce to 0, and the opening of the Gate logic is at h40 (1 / 4 cycle) before the first rising edge. Initiate the read MPR instruction. If the data matches the expected value, stop and record the value of rd_coarse_delay. Otherwise, increment rd_coarse_delay and initiate the read MPR instruction again until the data matches the expected value. The flowchart of integer period measurement is as Fig.15 shown.

[0044] In addition, there is a more sophisticated way to measure the integer period part of the Round-Trip Delay. First, write the 16-bit data sequence h0000, h0001, h0002,..., h0007 into a row of the memory in sequence. In the functional mode, set rd_coarse_delay to the value S, such as 8, to avoid the preamble. The first byte T read is the difference between the set value S and the correct value. Set rd_coarse_delay back to S - T, as Fig.16 shown. If the set Gate opening time rd_coarse_delay is 2 cycles later than the value that should be set, then a byte h0002 is read. Subtract 2 from the set rd_coarse_delay and set it back to obtain the correct rd_coarse_delay. Its flowchart is as Fig.12 shown.

[0045] The present invention makes the distance between the opening and closing of the gate logic and the DQS clock edge programmable to a maximum of 1 / 2 cycle, thereby being able to tolerate greater changes in the round-trip delay and significantly reducing the frequency of retraining. Even when the system changes greatly and needs to be retrained, the gate logic searches for a fast algorithm, which can reduce the occupation of effective bandwidth in a very short time.

[0046] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0047] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A DDR host DQS gate control circuit, characterized in that: The control circuit adopts the method of delaying dfi_rddata_en by an integer period plus a fractional period, and the control signal gate_close_extend controls whether to extend the positive level of the delayed dfi_rddata_en by half a period; Among them, the integer cycle delay is realized by the shift register, and the programmable signal gate_coarse_delay selects the dfi_rddata_en of a certain cycle delay to latch into the DFF; and the first half cycle delay gate_fine_delay of the fractional cycle is realized by the falling edge triggered DFF, and the remaining second half cycle is realized by the delay line Gate DLL combined with the control signal gate_fine_delay; The control signal gate_close_extend is set to 1 to extend the distance from the gate signal opening and closing to the clock edge to 1 / 2 cycle; at this time, the gate logic is closed at the node where the post-order / post-leading ends, leaving a half-cycle margin for the increase of the round-trip delay; If the round-trip delay is shortened, even if the glitches and noise after the post-sequence / post-lead are included, for the method of using FIFO to handle the cross-clock domain of DQS and PHY_CLK, when the lag time of PHY_CLK read FIFO is not large compared with DQS write FIFO, there will be no impact on the function; The DQS is sent to DQS_DLL through the IO module, where DQS_DLL is an existing module with a coverage range of 1 cycle. In functional mode, it is used to delay DQS by 1 / 4 cycle to sample DQ; In the measurement phase, the fractional cycle part of the phase difference between DQS and PHY_CLK is measured first. The initial value of DQS_DLL is set to 0, the gate is set to 1, and the measurement state machine initiates a long read. After waiting for a programmable cycle, it starts to use PHY_CLK to measure the phase of DQS. The specific measurement process includes: From the highest bit to the nth bit of DQS_DLL, set it to 1, wait for DQS to stabilize before sampling, and set it to 0 or 1 according to the sampling result; then, use an 8-bit unsigned number E[7:0] to represent 1 cycle. According to the lock value L[7:0] of the main delay line, it can be determined that the lower bits of E from the nth bit down do not affect the accuracy of delay line control; perform the first 1 operation on L-1 to obtain the binary digit m required for L, and subtract m from 7 to get this n; finally, the delayed DQS will be aligned with the PHY_CLK edge, and the value a of DQS_DLL is recorded; Wherein, a is an 8-bit unsigned number, which means that DQS is aligned with the rising edge of PHY_CLK after a fractional delay of a. It can be inferred that PHY_CLK is aligned with the rising edge of DQS after a fractional delay of -a. The specific measurement process of measuring the integer cycle portion of the round trip delay includes: Switch to function delay control, set the DQS_DLL delay to b, where b is 1 / 4 cycle, switch the normally open gate signal to function gate control, and set rd_coarse_delay to 0; then, set rd_fine_delay[7:0] to ~a-(h40<<gce)+b, set gce to 1, the opening of the gate logic is at half a cycle before the first rising edge, set gce to 0, and the opening of the gate logic is at 1 / 4 cycle before the first rising edge; Initiate a read MPR instruction, stop if the data matches the expected value, record the value of rd_coarse_delay, otherwise increment rd_coarse_delay and initiate a read MPR instruction again until the data matches the expected value; Or measure the integer cycle part of the round-trip delay, and the specific measurement process includes: First, write the 16-bit data sequence h0000, h0001, h0002,..., h0007 into a row of the memory in sequence, and in the function mode, set rd_coarse_delay to the value S. When the first byte T read is the difference between the set value S and the correct value, set rd_coarse_delay back to S-T. When the set gate opening time rd_coarse_delay is 2 cycles later than the set value, a byte h0002 is read. Subtract 2 from the set rd_coarse_delay and set it back to obtain the correct rd_coarse_delay.

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