A chiplet integrated structure and interconnection system based on high-speed interface

Abstract

The present application discloses a chiplet integrated structure and interconnection system based on a high-speed interface, wherein the chiplet integrated structure based on a high-speed interface includes: a protocol layer, adapted with a controller IP for establishing a link; a physical layer, adapted with a PHY IP for establishing a link; a D2D module, adapted with a first high-speed interface for information interaction with the controller IP, and a second high-speed interface for information interaction with the PHY IP; the first high-speed interface is used to receive or send interaction information of the protocol layer during the information interaction process, and the second high-speed interface is used to receive or send interaction information of the physical layer during the information interaction process. The technical solution of the present application can reduce the design complexity and area power consumption of the die in the chiplet.

Description

Technical Field

[0001] The present application relates to the technical field of chip design, and in particular to a chiplet integrated structure and interconnection system based on a high-speed interface. Background Art

[0002] Chiplet, commonly known as core particles, is a type of die (bare die) that meets specific functions. It uses die-to-die internal interconnection technology to package multiple module chips and underlying basic chips together to form a system chip to achieve a new form of IP reuse.

[0003] Related technologies include a chiplet that uses a bus-based on-chip interconnect as a protocol layer, similar to the UCIe protocol, namely Universal Chiplet Interconnect Express, whose main purpose is to unify the interconnection interface standards between chiplets and create an open chiplet ecosystem, and implement subsystem-level chiplets through Die-to-Die Adaptor and UCIe PHY. Figure 1 The overall structural diagram of a chiplet integrated structure is exemplified as a related art of this application, such as Figure 1 As shown in the figure, the existing chiplet implementation solutions are basically subsystem-level segmented dies (such as AMD's IO die including controller and PHY), and the protocol layer between dies is based on bus-type interconnection.

[0004] In actual application, for chiplet integration structures that use bus-based intra-chip interconnection as the protocol layer, that is, to implement IO die segmentation through the bus, relatively large design complexity and area power consumption are required. Summary of the invention

[0005] To solve the above technical problems, the embodiments of the present application provide a chiplet integration structure and interconnection system based on a high-speed interface.

[0006] According to one aspect of an embodiment of the present application, a chiplet integration structure based on a high-speed interface is provided, including: a protocol layer, adapted with a controller IP for establishing a link; a physical layer, adapted with a PHY IP for establishing a link; a D2D module, adapted with a first high-speed interface for information interaction with the controller IP, and a second high-speed interface for information interaction with the PHY IP; the first high-speed interface is used to receive or send interaction information of the protocol layer during the information interaction process, and the second high-speed interface is used to receive or send interaction information of the physical layer during the information interaction process.

[0007] In some embodiments of the present application, based on the above technical solution, the first high-speed interface includes a first high-speed sending interface and a first high-speed receiving interface respectively connected to the protocol layer, wherein the first high-speed sending interface is used to send the interactive information sent by the protocol layer, and the first high-speed receiving interface is used to receive the interactive information sent by the physical layer; the second high-speed interface includes a second high-speed sending interface and a second high-speed receiving interface respectively connected to the physical layer, wherein the second high-speed sending interface is used to send the interactive information sent by the physical layer, and the second high-speed receiving interface is used to receive the interactive information sent by the protocol layer.

[0008] In some embodiments of the present application, based on the above technical solution, the clock of the D2D module is the same as the clock of the protocol layer, or the clock of the D2D module is the same as the clock of the physical layer.

[0009] In some embodiments of the present application, based on the above technical solution, the clock of the D2D module is different from the clock of the protocol layer, and the clock frequency of the D2D module is fixed, or the clock of the D2D module is different from the clock of the physical layer, and the clock frequency of the D2D module is fixed.

[0010] In some embodiments of the present application, based on the above technical solution, when the clock of the D2D module is different from the clock of the protocol layer and the clock frequency of the D2D module is fixed, the clock frequency of the D2D module is greater than the clock frequency of the protocol layer; and, when the clock of the D2D module is different from the clock of the physical layer and the clock frequency of the D2D module is fixed, the clock frequency of the D2D module is greater than the clock frequency of the physical layer.

[0011] In some embodiments of the present application, based on the above technical solution, a first asynchronous FIFO is provided between the D2D module and the protocol layer, and a second asynchronous FIFO is provided between the D2D module and the physical layer, wherein the first asynchronous FIFO is used for rate matching between the D2D module and the protocol layer, and the second asynchronous FIFO is used for rate matching between the D2D module and the physical layer.

[0012] In some embodiments of the present application, based on the above technical solution, the first asynchronous FIFO includes a first output asynchronous FIFO and a first input asynchronous FIFO respectively connected to the protocol layer, wherein the first output asynchronous FIFO is used for output control of information interaction between the D2D module and the protocol layer, and the first input asynchronous FIFO is used for input control of information interaction between the D2D module and the protocol layer; the second asynchronous FIFO includes a second output asynchronous FIFO and a second input asynchronous FIFO respectively connected to the physical layer, wherein the first output asynchronous FIFO is used for output control of information interaction between the D2D module and the physical layer, and the first input asynchronous FIFO is used for input control of information interaction between the D2D module and the physical layer.

[0013] In some embodiments of the present application, based on the above technical solution, the first asynchronous FIFO includes a write port and a read port, and the read signal of the read port serves as an enable signal of the write port; and the second asynchronous FIFO includes a write port and a read port, and the read signal of the read port serves as an enable signal of the write port.

[0014] In some embodiments of the present application, based on the above technical solution, when the D2D module is rate matched with the protocol layer, the write port of the first asynchronous FIFO writes the preset data valid signal as the in-path data into the first asynchronous FIFO; and when the D2D module is rate matched with the physical layer, the write port of the second asynchronous FIFO writes the preset data valid signal as the in-path data into the second asynchronous FIFO.

[0015] According to another aspect of an embodiment of the present application, a chiplet interconnection system is provided, characterized in that it includes chiplets located at different levels in at least two three-dimensional packages, and the chiplets include the chiplet integrated structure based on the high-speed interface described above.

[0016] In the technical solution of the embodiment of the present application, the above invention content can at least bring the following beneficial effects:

[0017] The chiplet integrated structure of the present application sets an independent high-speed interface between the protocol layer and the physical layer, so that the IO die segmentation of the chiplet integrated structure is implemented on the subsystem formed by the protocol layer and the physical layer, and there is no need to perform IO die segmentation based on the bus. Therefore, when the chiplet integrated structure performs information exchange based on the high-speed interface, the bus interface matching corresponding new protocols can be reduced, and information exchange can be performed directly through the high-speed interface between the protocol layer and the physical layer, thereby reducing the design complexity and area power consumption of the die in the chiplet. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0019] Figure 1 The overall structural diagram of a chiplet integrated structure is exemplified as a related art of the present application.

[0020] Figure 2 The overall structural diagram of a chiplet integrated structure based on a high-speed interface is exemplified in this application.

[0021] Figure 3 This is a schematic diagram of the interactive information flow of the internal structure of the D2D module shown in an exemplary embodiment of the present application.

[0022] Figure 4 This is a schematic diagram of the flow of the internal clock signal of the D2D module shown in an exemplary embodiment of the present application.

[0023] Figure 5 This is a schematic diagram of the interactive information flow of the internal structure of a D2D module according to another exemplary embodiment of the present application.

[0024] Figure 6 This is a schematic diagram of the overall internal structure of a D2D module shown in an exemplary embodiment of the present application.

[0025] It should be noted that, in the above figures, Diel represents an independent processing unit; IO die represents an interface processing unit; Bus represents a bus; Die-to-die adapter represents a chip-to-chip adapter; Physical layer represents a physical layer; PIPE TX represents a transmitting channel; PIPE RX represents a receiving channel; Tx data flow represents a transmitting data flow; and Rx data flow represents a receiving data flow. DETAILED DESCRIPTION

[0026] In order to make the purpose and implementation method of the present application clearer, the exemplary implementation method of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0027] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their ordinary and common meanings.

[0028] The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances.

[0029] The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0030] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0031] This application discloses a chiplet integrated structure and interconnection system based on a high-speed interface. Figure 2 The overall structural diagram of a chiplet integrated structure based on a high-speed interface is exemplified in this application. Figure 2 As shown, the chiplet integration structure based on the high-speed interface may include at least:

[0032] The protocol layer 101 is adapted with a controller IP for establishing a link.

[0033] Specifically, the protocol layer 101 is used to define the rules and conventions for data transmission between different layers. For example, in the chiplet integrated structure 100, the present application converts data into Flit packets for transmission through the protocol layer 101. The controller IP represents the IP address used to establish a link with the protocol layer 101.

[0034] It should be noted that IP address (Internet Protocol Address) refers to the Internet Protocol address. It is a unified address format provided by the IP protocol, which assigns a logical address to each network and each host on the Internet. It is used to uniquely identify and locate devices on the Internet to ensure that data can be accurately transmitted to the target device.

[0035] The physical layer 103 is adapted with a PHY IP for establishing a link.

[0036] Specifically, the physical layer 103 is used to define the physical characteristics of the transmission medium, such as transmission rate, transmission distance, etc., and is responsible for transparent transmission of bit streams, including modulation and demodulation of signals, transmission and reception of data, etc. Among them, the PHY IP is similar to the controller IP of the protocol layer 101, and the PHY IP represents the IP address used to establish a link with the physical layer 103.

[0037] The physical layer 103 of the present application can be understood as a broad physical layer 103 in the field of data transmission, which provides a data transmission path for the data terminal device. The data path can be a physical medium or a plurality of physical media connected. A complete data transmission includes activating the physical connection, transmitting data, and terminating the physical connection.

[0038] The D2D module is adapted to have a first high-speed interface for information interaction with the controller IP and a second high-speed interface for information interaction with the PHY IP; the first high-speed interface is used to receive or send interaction information of the protocol layer 101 during the information interaction process, and the second high-speed interface is used to receive or send interaction information of the physical layer 103 during the information interaction process.

[0039] At the same time, the protocol layer 101 is also equipped with a data bus Bus for information exchange with Chiplet. In order to realize the connection between the protocol layer 101 and the bus, a corresponding bus interface needs to be designed. This interface is responsible for encapsulating the data transmitted by the protocol layer 101 into a format that can be recognized by the bus and transmitting it to the target device through the bus. For example, the protocol stack is a specific implementation method of the protocol, which implements various rules and formats defined in the protocol in code.

[0040] During data transmission, the protocol layer 101 needs to ensure data synchronization and correctness. This is usually achieved through clock signals and data signals on the bus. The clock signal is used to determine the transmission rate and timing of the data, while the data signal is used to transmit the actual data content.

[0041] The protocol layer 101 is also responsible for addressing and routing data. This includes determining the source address and destination address of the data, and selecting the best transmission path. This information is usually transmitted through the address lines and control lines on the bus.

[0042] Specifically, D2D (Die-to-Die) is a technology used in the semiconductor field, mainly used as a functional module to provide a data interface between two chip dies (or dies) in the same package.

[0043] Based on the technical solution of the present application, direct data communication between two chip dies in the package is realized through the Die-to-Die interface. At the same time, in order to achieve high efficiency and high bandwidth, the D2D interface utilizes the extremely short channel characteristics of the connecting dies, usually including a physical layer PHY and a controller module, to provide seamless connection for the internal interconnection structure of the two dies.

[0044] For example, for the high-speed interface 102, the technical solutions in the related field are generally divided into PHY (physical layer) IP and controller IP, which generally follow the standard communication protocol (such as PCIe, SATA, USB PHY and controllers all follow the same PIPE interface protocol).

[0045] For example, in the design process of some SoC (System on Chip) chips, SoC chip design engineers can purchase PHY IP and controller IP from different IP suppliers, and integrate and design various high-speed interface subsystems (such as PCIe subsystem, SATA subsystem, USB subsystem). These high-speed interface subsystems are important components of SoC chips.

[0046] In the chiplet implementation, in order to reduce the design complexity and area power consumption of the two dies in Die-to-Die, a D2D module is set between the controller IP of the protocol layer 101 and the PHY IP of the physical layer 103. Information interaction is realized through the first high-speed interface and the second high-speed interface inside the D2D module, so as to realize the IO die segmentation inside the subsystem instead of the IO die segmentation on the bus side. In this way, from the perspective of the entire SoC system level, these high-speed interface subsystems do not need to add chiplet protocols and chiplet PHY, thereby reducing the design complexity and area power consumption of the two dies.

[0047] It should be noted that, since not all SoC subsystems have PHY IP and controller IP, most chiplet implementations will choose to split the die on the bus side, rather than splitting the die between PHY IP and control IP. At the same time, for SoC systems with high-speed interface subsystems, there are generally PHY IP and controller IP, so the application of this application can be a dedicated design for the high-speed interface subsystem and IO die with PHY and controller standard interfaces. This allows this application to optimize the design of chiplet implementation solutions within some inherent fields without affecting some standardized settings.

[0048] Specifically, the SoC system in the above example is used as an example. In the related technology of the SoC system, the protocol layer 101 and the physical layer 103 generally exchange information through a communication bus, and the corresponding protocol information is required for data transmission. Therefore, the corresponding IO die segmentation is also implemented based on the bus.

[0049] Based on this, through the above implementation, the chiplet integrated structure 100 of the present application sets an independent high-speed interface 102 between the protocol layer 101 and the physical layer 103, so that the IO die segmentation of the chiplet integrated structure 100 is implemented on the subsystem formed by the protocol layer 101 and the physical layer 103, and there is no need to perform IO die segmentation based on the bus, thereby reducing the number of new protocols matched with the bus, and directly performing information interaction through the high-speed interface 102 between the protocol layer 101 and the physical layer 103, thereby reducing the design complexity and area power consumption of the die in the chiplet.

[0050] Based on the above embodiments, Figure 3 The following is a schematic diagram of the interactive information flow of the internal structure of the D2D module shown in the exemplary embodiment of the present application. Figure 3 As shown, in some embodiments of the present application, the first high-speed interface may include a first high-speed transmitting interface and a first high-speed receiving interface respectively connected to the protocol layer 101, wherein the first high-speed transmitting interface is used to send interactive information sent by the protocol layer 101, and the first high-speed receiving interface is used to receive interactive information sent by the physical layer 103.

[0051] The second high-speed interface includes a second high-speed transmitting interface and a second high-speed receiving interface respectively connected to the physical layer 103, wherein the second high-speed transmitting interface is used to send the interactive information sent by the physical layer 103, and the second high-speed receiving interface is used to receive the interactive information sent by the protocol layer 101.

[0052] Specifically, for the first high-speed interface and the second high-speed interface, the receiving end and the sending end can be implemented by two independent sub-modules, such as Figure 3 As shown, taking the first high-speed interface as an example, the first high-speed sending interface and the first high-speed receiving interface are independent of each other, so that the transmission channel corresponding to information reception and the transmission channel corresponding to information sending do not interfere with each other. When the packaged chips corresponding to the chiplet technology perform information interaction, the accuracy and reliability of information interaction can be improved.

[0053] Based on the above embodiments, in some embodiments of the present application, the clock of the D2D module is the same as the clock of the protocol layer 101 , or the clock of the D2D module is the same as the clock of the physical layer 103 .

[0054] To illustrate by way of example, Figure 4 FIG. 1 is a schematic diagram showing the flow of the internal clock signal of the D2D module according to an exemplary embodiment of the present application. Figure 4 As shown, in order to cope with the frequency conversion requirements of the high-speed interface and the protocol layer 101 or the physical layer 103, the D2D of the present application discloses a solution, by setting the D2D and the protocol layer 101 to use the same clock, or setting the D2D and the physical layer 103 to use the same clock, that is, the path-associated clock. This makes the real-time performance of data transmission higher.

[0055] Based on the above embodiments, in some embodiments of the present application, the clock of the D2D module is different from the clock of the protocol layer 101, and the clock frequency of the D2D module is fixed, or the clock of the D2D module is different from the clock of the physical layer 103, and the clock frequency of the D2D module is fixed.

[0056] To illustrate by way of example, in order to cope with the frequency conversion requirements of the high-speed interface 102 and the protocol layer 101 or the physical layer 103, the D2D of the present application discloses another solution. The clock of the D2D module is different from the clock of the protocol layer 101, and the clock frequency of the D2D module is fixed. In this way, the jitter difference between the clock PLLs can be absorbed under the premise of satisfying data transmission. Among them, jitter is the instability of data transmission time, which is manifested as random fluctuations in the arrival time of data packets. In data transmission, the ideal transmission situation is that the data packet arrives at the receiving end at a constant rate and a fixed time interval, but in fact, due to the influence of various factors, the arrival time of the data packet will deviate. Therefore, the present application can perform adaptive rate matching on the clock between the protocol layer 101 and the physical layer 103 through the above-mentioned clock setting method to synchronize the clocks between the transmitter and the receiver, thereby reducing the impact of clock drift.

[0057] Specifically, in order to meet the frequency conversion requirements of the above-mentioned high-speed interface 102 and the protocol layer 101 or the physical layer 103, and to absorb the jitter differences between the clock PLLs, in the technical solution of the present application, when the clock of the D2D module is different from the clock of the protocol layer 101 and the clock frequency of the D2D module is fixed, the clock frequency of the D2D module is greater than the clock frequency of the protocol layer 101; and, when the clock of the D2D module is different from the clock of the physical layer 103 and the clock frequency of the D2D module is fixed, the clock frequency of the D2D module is greater than the clock frequency of the physical layer 103.

[0058] When data is transmitted between the high-speed interface 102 and the protocol layer 101, since there is a certain difference in the clock frequency between the high-speed interface 102 and the protocol layer 101, the difference detection caused by jitter can be absorbed, thereby improving the stability of data transmission. The same is true between the high-speed interface 102 and the physical layer 103, which will not be repeated.

[0059] Based on the above embodiments, Figure 5 FIG. 1 is a schematic diagram of the interactive information flow of the internal structure of the D2D module shown in another exemplary embodiment of the present application. Figure 5 As shown, in some embodiments of the present application, adaptive rate matching is performed on the clocks between the protocol layer 101 and the physical layer 103 in the above embodiments. A specific implementation method is to provide a first asynchronous FIFO between the D2D module and the protocol layer 101, and a second asynchronous FIFO between the D2D module and the physical layer 103, wherein the first asynchronous FIFO is used for rate matching between the D2D module and the protocol layer 101, and the second asynchronous FIFO is used for rate matching between the D2D module and the physical layer 103.

[0060] FIFO (First In, First Out) is a first-in, first-out data processing principle or data structure. In data structures, FIFO is usually associated with queues. A queue is a special linear list that only allows deletion operations at the front of the list and insertion operations at the rear of the list. This operation mode ensures that the earliest element added to the queue will be removed first, that is, first-in, first-out. There are many ways to implement queues, including chain queues and circular queues.

[0061] Asynchronous FIFO is a special FIFO memory used to handle data transmission across clock domains. Asynchronous FIFO refers to a FIFO memory in which the read and write clocks are inconsistent and independent of each other. The first asynchronous FIFO and the second asynchronous FIFO disclosed in this application are used for rate matching between D2D and protocol layer 101 and between D2D and physical layer 103, respectively.

[0062] The present application can realize data transmission between different clock domains through asynchronous FIFO, and realize data interface interconnection with different data widths, allowing read and write operations to be performed in different clock domains, thereby improving the flexibility and efficiency of data transmission.

[0063] Based on the above embodiments, Figure 6 FIG. 1 is a schematic diagram of the overall internal structure of a D2D module according to an exemplary embodiment of the present application. Figure 6 As shown, in some embodiments of the present application, the first asynchronous FIFO includes a first output asynchronous FIFO and a first input asynchronous FIFO respectively connected to the protocol layer 101, wherein the first output asynchronous FIFO is used for output control of information interaction between the D2D module and the protocol layer 101, and the first input asynchronous FIFO is used for input control of information interaction between the D2D module and the protocol layer 101; the second asynchronous FIFO includes a second output asynchronous FIFO and a second input asynchronous FIFO respectively connected to the physical layer 103, wherein the first output asynchronous FIFO is used for output control of information interaction between the D2D module and the physical layer 103, and the first input asynchronous FIFO is used for input control of information interaction between the D2D module and the physical layer 103.

[0064] Specifically, the technical solution of this embodiment can be set corresponding to the embodiment of the high-speed interface 102 in the above embodiment. For example, the first input asynchronous FIFO can be adapted to be used with the first high-speed receiving interface, the first output asynchronous FIFO can be adapted to be used with the first high-speed transmitting interface, the second input asynchronous FIFO can be adapted to be used with the second high-speed receiving interface, and the second output asynchronous FIFO can be adapted to be used with the second high-speed transmitting interface.

[0065] Of course, there is no specific limitation on the specific adaptation combination of the first high-speed interface, the second high-speed interface and the first asynchronous FIFO, the second asynchronous FIFO, and it is only used as an example.

[0066] Through the above implementation, the first output asynchronous FIFO and the first input asynchronous FIFO are relatively independent, thereby reducing interference between data input and output and improving the transmission quality and transmission efficiency of interactive information.

[0067] The technical effects brought about by setting the second output asynchronous FIFO and the second input asynchronous FIFO are similar and will not be elaborated on.

[0068] Based on the above embodiments, in some embodiments of the present application, the first asynchronous FIFO includes a write port and a read port, and the read signal of the read port serves as an enable signal of the write port; and the second asynchronous FIFO includes a write port and a read port, and the read signal of the read port serves as an enable signal of the write port.

[0069] Specifically, the asynchronous FIFO uses a dual-port RAM as a data storage medium, allowing read and write operations to be performed simultaneously. The write operation writes data to the address indicated by the write pointer, while the read operation reads data from the address indicated by the read pointer.

[0070] In the technical solution of the present application, when the read port of the first asynchronous FIFO reads a signal, the read signal is used as an enable signal of the write port to achieve read and write synchronization of the read port and the write port, thereby improving data transmission efficiency. The second asynchronous FIFO is similar and will not be described in detail.

[0071] Based on the above embodiments, in some embodiments of the present application, when rate matching is performed between the D2D module and the protocol layer 101, the write port of the first asynchronous FIFO writes a preset data valid signal as in-path data into the first asynchronous FIFO; and when rate matching is performed between the D2D module and the physical layer 103, the write port of the second asynchronous FIFO writes a preset data valid signal as in-path data into the second asynchronous FIFO.

[0072] Specifically, in order to improve the accuracy of data transmission, the preset data valid signal is written into the first asynchronous FIFO and the second asynchronous FIFO as the accompanying data, so that the present application can identify the data based on the data valid signal during the data transmission process, thereby improving the accuracy of the data.

[0073] The present application also discloses a chiplet interconnection system, including chiplets located at different levels in at least two three-dimensional packages, and the chiplets include a chiplet integrated structure based on a high-speed interface disclosed in any of the above embodiments.

[0074] In order to more clearly disclose the technical solution of the present application, further exemplary description is given in combination with the above-mentioned multiple embodiments, and the specific contents are as follows:

[0075] The present invention is directed to the chiplet integrated structure 100 in which some high-speed interface subsystems have a protocol layer (controller IP) and a physical layer (PHYIP). By implementing the IO die segmentation inside the subsystem instead of segmenting the IO die on the bus side, these high-speed interface subsystems do not need to add chiplet protocols and chiplet PHY at the level of the entire SoC system in the above example, thereby reducing the design complexity and area power consumption of the two dies.

[0076] Specifically, the physical interface between the two dies is called D2D, that is, a D2D module between the protocol layer 101 and the physical layer 103. In order to implement the above solution through the D2D module, the present application discloses at least two configuration structures.

[0077] The first one is implemented through the first high-speed interface and the second high-speed interface inside the D2D module, and requires the D2D module and the protocol layer 101 or the physical layer 103 to use the same clock signal, that is, the path-associated clock.

[0078] The second method is implemented through the first high-speed interface and the second high-speed interface, and the first asynchronous FIFO and the second asynchronous FIFO inside the D2D module, and requires the D2D module to use different clock signals from the protocol layer 101 or the physical layer 103, and requires the clock frequency corresponding to the D2D module to be fixed, and requires the clock frequency corresponding to the D2D module to be higher than the highest clock frequency of the protocol layer 101 or the highest clock frequency of the physical layer 103. The jitter difference between the clock PLLs is absorbed by the clock frequency difference.

[0079] In the second setting structure, the purpose of the first asynchronous FIFO and the second asynchronous FIFO is to achieve adaptive rate matching between the protocol layer 101 or the physical layer 103 through the first asynchronous FIFO and the second asynchronous FIFO.

[0080] It should be noted that for the first setting structure, the real-time nature of information interaction can be guaranteed. For the second setting structure, since the asynchronous FIFO is added to realize automatic rate matching, the processing of interactive information is easier and the design complexity is relatively low. And either of the two structures is based on the chiplet integrated structure 100 by setting an independent high-speed interface 102 between the protocol layer 101 and the physical layer 103, so that the IO die of the chiplet integrated structure 100 is divided on the subsystem formed by the protocol layer 101 and the physical layer 103, and there is no need to divide the IO die based on the bus.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0082] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A chiplet integration structure based on a high-speed interface, characterized in that: include: Protocol layer, adapted with controller IP for establishing links; Physical layer, adapted with PHY IP for establishing links; The D2D module is adapted to be equipped with a first high-speed interface for information interaction with the controller IP and a second high-speed interface for information interaction with the PHY IP; the first high-speed interface is used to receive or send interaction information of the protocol layer during the information interaction process, and the second high-speed interface is used to receive or send interaction information of the physical layer during the information interaction process; A first asynchronous FIFO is provided between the D2D module and the protocol layer, and a second asynchronous FIFO is provided between the D2D module and the physical layer, wherein the first asynchronous FIFO is used for rate matching between the D2D module and the protocol layer, and the second asynchronous FIFO is used for rate matching between the D2D module and the physical layer; When data is transmitted based on the first high-speed interface and the second high-speed interface, if data transmission is implemented through the first high-speed interface and the second high-speed interface, and the first asynchronous FIFO and the second asynchronous FIFO, the clock of the D2D module is different from the clock of the protocol layer, and the clock frequency of the D2D module is fixed, or the clock of the D2D module is different from the clock of the physical layer, and the clock frequency of the D2D module is fixed; When the clock of the D2D module is different from the clock of the protocol layer and the clock frequency of the D2D module is fixed, the clock frequency of the D2D module is greater than the clock frequency of the protocol layer; And, when the clock of the D2D module is different from the clock of the physical layer and the clock frequency of the D2D module is fixed, the clock frequency of the D2D module is greater than the clock frequency of the physical layer.

2. The chiplet integrated structure based on high-speed interface according to claim 1, characterized in that: The first high-speed interface comprises a first high-speed sending interface and a first high-speed receiving interface respectively connected to the protocol layer, wherein the first high-speed sending interface is used to send the interactive information sent by the protocol layer, and the first high-speed receiving interface is used to receive the interactive information sent by the physical layer; The second high-speed interface includes a second high-speed transmitting interface and a second high-speed receiving interface respectively connected to the physical layer, wherein the second high-speed transmitting interface is used to send the interactive information sent by the physical layer, and the second high-speed receiving interface is used to receive the interactive information sent by the protocol layer.

3. The chiplet integrated structure based on high-speed interface according to claim 1, characterized in that: When data transmission is performed based on the first high-speed interface and the second high-speed interface, if data transmission is achieved through the first high-speed interface and the second high-speed interface, the clock of the D2D module is the same as the clock of the protocol layer, or the clock of the D2D module is the same as the clock of the physical layer.

4. The chiplet integrated structure based on high-speed interface according to claim 1, characterized in that: The first asynchronous FIFO includes a first output asynchronous FIFO and a first input asynchronous FIFO respectively connected to the protocol layer, wherein the first output asynchronous FIFO is used for output control of information interaction between the D2D module and the protocol layer, and the first input asynchronous FIFO is used for input control of information interaction between the D2D module and the protocol layer; The second asynchronous FIFO includes a second output asynchronous FIFO and a second input asynchronous FIFO respectively connected to the physical layer, wherein the first output asynchronous FIFO is used for output control of information interaction between the D2D module and the physical layer, and the first input asynchronous FIFO is used for input control of information interaction between the D2D module and the physical layer.

5. The chiplet integrated structure based on high-speed interface according to claim 1, characterized in that: The first asynchronous FIFO includes a write port and a read port, and a read signal of the read port serves as an enable signal of the write port; And the second asynchronous FIFO includes a write port and a read port, and the read signal of the read port serves as an enable signal of the write port.

6. The chiplet integrated structure based on high-speed interface according to claim 5, characterized in that: When the D2D module is rate matched with the protocol layer, the write port of the first asynchronous FIFO writes a preset data valid signal into the first asynchronous FIFO as accompanying data; And when the D2D module is rate matched with the physical layer, the write port of the second asynchronous FIFO writes a preset data valid signal into the second asynchronous FIFO as accompanying data.

7. A chiplet interconnection system, characterized in that: The invention comprises chiplets located at different levels in at least two three-dimensional packages, and the chiplets comprise a chiplet integrated structure based on a high-speed interface according to any one of claims 1 to 6.

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