Data transmission circuit and memory

Abstract

An embodiment of the present disclosure provides a data transmission circuit and a memory. The data transmission circuit includes a calibration circuit and an output circuit. The calibration circuit is connected to the output circuit and is used to adjust the impedance of the output circuit. The calibration circuit includes: a calibration control circuit for generating and outputting a calibration code; a calibration unit including multiple groups of first transistors and second transistors connected in series; the gate of the first transistor is connected to the calibration control circuit and is used to receive the calibration code; the calibration control circuit is also used to control the conduction or cutoff of the multiple first transistors through the calibration code to adjust the resistance value of the calibration unit to a standard resistance value; when the first transistor is turned on, the first operating voltage on the gate is less than the second operating voltage on the gate when the second transistor is turned on.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to, but not limited to, a data transmission circuit and a memory. Background Art

[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and electronic products. For example, dynamic random access memory (DRAM), static random access memory (SRAM), and NAND memory are all commonly used semiconductor memory devices in computers.

[0003] In recent years, the consumer market's demand for memory transmission speeds has continuously increased, posing new challenges to memory power consumption control. Typically, memory devices use ZQ calibration to adjust the impedance of data input and output circuits to maintain data signal integrity. Therefore, how to reduce memory power consumption while ensuring data signal transmission speed and integrity has become a pressing issue for the industry. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a data transmission circuit and a memory.

[0005] An embodiment of the present disclosure provides a data transmission circuit, including a calibration circuit and an output circuit, wherein the calibration circuit is connected to the output circuit; the calibration circuit includes: a calibration control circuit for generating and outputting a calibration code; a calibration unit including multiple groups of first transistors and second transistors connected in series; the gate of the first transistor is connected to the calibration control circuit and is used to receive the calibration code; the calibration control circuit is also used to control the conduction or cutoff of multiple first transistors through the calibration code to adjust the resistance value of the calibration unit to a standard resistance value; when the first transistor is turned on, the first operating voltage on the gate is less than the second operating voltage on the gate when the second transistor is turned on.

[0006] In some embodiments, the output circuit includes: a pull-up driving unit and a pull-down driving unit having the same structure as the calibration unit; the pull-up driving unit and the pull-down driving unit are connected between a first voltage terminal and a second voltage terminal; the pull-down driving unit includes a plurality of groups of third transistors and fourth transistors connected in series, and the pull-up driving unit includes a plurality of groups of fifth transistors and sixth transistors connected in series; the third transistor and the fifth transistor are the same as the first transistor, and the fourth transistor and the sixth transistor are the same as the second transistor; the gates of the fourth transistor and the sixth transistor are connected to the calibration control circuit and are used to receive the calibration code; the gates of the third transistor and the fifth transistor are used to receive a data signal; an end of the third transistor away from the fourth transistor is connected to a data transmission terminal, and an end of the fifth transistor away from the sixth transistor is connected to the data transmission terminal; the calibration control circuit is further used to control the conduction or cut-off of the fourth transistor and the sixth transistor according to the calibration code to adjust the resistance values ​​of the pull-up driving unit and the pull-down driving unit to a standard resistance value; and the output circuit is used to output the calibrated data signal through the data transmission terminal.

[0007] In some embodiments, the calibration circuit further includes: a voltage converter connected between the calibration control circuit and the output circuit; the voltage converter is used to convert the voltage of the calibration code from the first operating voltage to the second operating voltage.

[0008] In some embodiments, the first end of the fourth transistor is connected to the second voltage end, the second end of the fourth transistor is connected to the first end of the third transistor, and the second end of the third transistor is connected to the data transmission end; the first end of the sixth transistor is connected to the first voltage end, the second end of the sixth transistor is connected to the first end of the fifth transistor, and the second end of the fifth transistor is connected to the data transmission end.

[0009] In some embodiments, the calibration unit includes: a pull-down calibration unit and a pull-up calibration unit; the pull-up calibration unit is connected between the first voltage terminal and the detection node, and the pull-down calibration unit is connected between the second voltage terminal and the detection node; the pull-down calibration unit has the same structure as the pull-down drive unit; the pull-up calibration unit has the same structure as the pull-up drive unit; the calibration code includes: a first calibration code and a second calibration code; the calibration control circuit is further configured to generate and output a changing pre-calibration code based on the voltage value obtained from the detection node to adjust the resistance value of the calibration unit; when the resistance value of the pull-down calibration unit is equal to the standard resistance value, the calibration control circuit determines that the pre-calibration code is the first calibration code; when the resistance value of the pull-up calibration unit is equal to the standard resistance value, the calibration control circuit determines that the pre-calibration code is the second calibration code.

[0010] In some embodiments, the detection node includes a first node and a second node, and the calibration circuit also includes: an external resistor for providing the standard resistance value; the pull-down calibration unit includes: a first pull-down calibration unit and a second pull-down calibration unit; the first pull-down calibration unit and the external resistor are connected between the first voltage end and the second voltage end; there is the first node between the first pull-down calibration unit and the external resistor; the second pull-down calibration unit and the pull-up calibration unit are connected between the first voltage end and the second voltage end; there is the second node between the second pull-down calibration unit and the pull-up calibration unit; the calibration control circuit is specifically used to latch the pre-calibration code as the first calibration code when the first voltage of the first node is equal to the first reference voltage; the calibration control circuit is also used to output the first calibration code to the second pull-down calibration unit, and latch the pre-calibration code as the second calibration code when the second voltage of the second node is equal to the second reference voltage.

[0011] In some embodiments, the calibration control circuit includes: a voltage generating circuit, including a first output terminal for outputting the first reference voltage and a second output terminal for outputting the second reference voltage; a comparator, for comparing the first voltage with the first reference voltage to output a first comparison signal, or comparing the second voltage with the second reference voltage to output a second comparison signal; a calibration code generating circuit, connected to the comparator; the calibration code generating circuit is used to generate the changed pre-calibration code; the calibration code generating circuit is also used to latch the pre-calibration code as the first calibration code according to the first comparison signal, and latch the pre-calibration code as the second calibration code according to the second comparison signal; a calibration selection circuit, connected to the comparator and the calibration code generating circuit; the calibration selection circuit is used to output a selection signal to select the comparison a first voltage and the first reference voltage, or compares the second voltage and the second reference voltage; a first selection unit, the input end of the first selection unit is connected to the first node and the second node, the output end of the first selection unit is connected to the comparator, and the selection end of the first selection unit is connected to the calibration selection circuit; the first selection unit is used to select the first voltage or the second voltage to output to the comparator according to the selection signal; a second selection unit, the input end of the second selection unit is connected to the first output end and the second output end of the voltage generating circuit, the output end of the second selection unit is connected to the comparator, and the selection end of the second selection unit is connected to the calibration selection circuit; the second selection unit is used to select the first reference voltage or the second reference voltage to output to the comparator according to the selection signal.

[0012] In some embodiments, the gate oxide layers of the first transistor, the third transistor, and the fifth transistor have a first thickness, the gate oxide layers of the second transistor, the fourth transistor, and the sixth transistor have a second thickness, and the first thickness is less than the second thickness.

[0013] An embodiment of the present disclosure provides another data transmission circuit, including a calibration circuit and an output circuit, wherein the calibration circuit is connected to the output circuit; the calibration circuit includes: a calibration control circuit for generating and outputting a calibration code; a calibration unit connected between a detection node and a first voltage terminal or between the detection node and a second voltage terminal; the calibration unit includes multiple groups of first transistors and second transistors connected in series; the first transistor is connected between the second transistor and the detection node; the gate of the first transistor is connected to the calibration control circuit and is used to receive the calibration code; the calibration control circuit is also used to generate the calibration code based on the voltage value obtained from the detection node, and control the conduction or cutoff of multiple first transistors through the calibration code to adjust the resistance value of the calibration unit to a standard resistance value.

[0014] In some embodiments, the output circuit includes: a pull-up driving unit and a pull-down driving unit with the same structure as the calibration unit; the pull-down driving unit includes multiple groups of third transistors and fourth transistors connected in series, and the pull-up driving unit includes multiple groups of fifth transistors and sixth transistors connected in series; the third transistor and the fifth transistor are the same as the first transistor, and the fourth transistor and the sixth transistor are the same as the second transistor; the gates of the fourth transistor and the sixth transistor are connected to the calibration control circuit and are used to receive the calibration code; the gates of the third transistor and the fifth transistor are used to receive data signals; the end of the third transistor away from the fourth transistor is connected to the data transmission end, and the end of the fifth transistor away from the sixth transistor is connected to the data transmission end; the calibration control circuit is also used to control the conduction or cutoff of the fourth transistor and the sixth transistor according to the calibration code to adjust the resistance value of the pull-up driving unit and the pull-down driving unit to a standard resistance value; the output circuit is used to output the calibrated data signal through the data transmission end.

[0015] In some embodiments, a first operating voltage on the gate of the first transistor when the first transistor is turned on is less than a second operating voltage on the gate of the second transistor when the second transistor is turned on.

[0016] In some embodiments, the calibration circuit further includes: a voltage converter connected between the calibration control circuit and the output circuit; the voltage converter is used to convert the voltage of the calibration code from the first operating voltage to the second operating voltage.

[0017] In some embodiments, the calibration unit includes: a pull-down calibration unit and a pull-up calibration unit; the pull-down calibration unit has the same structure as the pull-down drive unit; the pull-up calibration unit has the same structure as the pull-up drive unit; the calibration code includes: a first calibration code and a second calibration code; the calibration control circuit is further configured to generate and output a changing pre-calibration code based on the voltage value obtained from the detection node to adjust the resistance value of the calibration unit; when the resistance value of the pull-down calibration unit is equal to the standard resistance value, the calibration control circuit determines that the pre-calibration code is the first calibration code; when the resistance value of the pull-up calibration unit is equal to the standard resistance value, the calibration control circuit determines that the pre-calibration code is the second calibration code.

[0018] In some embodiments, the detection node includes a first node and a second node, and the calibration circuit also includes: an external resistor for providing the standard resistance value; the pull-down calibration unit includes: a first pull-down calibration unit and a second pull-down calibration unit; the first pull-down calibration unit and the external resistor are connected between the first voltage end and the second voltage end; there is the first node between the first pull-down calibration unit and the external resistor; the second pull-down calibration unit and the pull-up calibration unit are connected between the first voltage end and the second voltage end; there is the second node between the second pull-down calibration unit and the pull-up calibration unit; the calibration control circuit is specifically used to latch the pre-calibration code as the first calibration code when the first voltage of the first node is equal to the first reference voltage; the calibration control circuit is also used to output the first calibration code to the second pull-down calibration unit, and latch the pre-calibration code as the second calibration code when the second voltage of the second node is equal to the second reference voltage.

[0019] An embodiment of the present disclosure provides a memory, comprising: a peripheral circuit, including the data transmission circuit described in any one of the above embodiments; and a memory cell array connected to the peripheral circuit.

[0020] In the data transmission circuit provided in the embodiments of the present disclosure, a calibration unit includes multiple groups of first and second transistors connected in series. A calibration control circuit is used to control the conduction or cutoff of the first transistors based on a calibration code. When the first transistors are on, a first operating voltage on the gate is lower than a second operating voltage on the gate when the second transistors are on. As a result, the first operating voltage of the first transistors used to receive the calibration code is lower, allowing the calibration control circuit to use a lower voltage power domain. This reduces the power consumption of the entire data transmission circuit without affecting the transmission performance of the output circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a data transmission circuit provided in an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of a pull-up and pull-down driving unit in a data transmission circuit provided by an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of a calibration circuit in a data transmission circuit provided by an embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram of another data transmission circuit provided in an embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of an output circuit in another data transmission circuit provided by an embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of a voltage converter in another data transmission circuit provided by an embodiment of the present disclosure;

[0027] Figure 7 A schematic diagram of a calibration control circuit in another data transmission circuit provided by an embodiment of the present disclosure;

[0028] Figure 8 A schematic diagram of a calibration circuit in another data transmission circuit provided by an embodiment of the present disclosure;

[0029] Figure 9 A schematic diagram of another data transmission circuit provided in an embodiment of the present disclosure;

[0030] Figure 10 A schematic diagram of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0032] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0033] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0034] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0036] In some embodiments, as Figure 1 , is a schematic diagram of a data transmission circuit 10 in a memory. The data transmission circuit 10 includes at least an output circuit 110 and a calibration circuit 120. The output circuit 110 can be used to receive read data provided by the serial-to-parallel conversion circuit and output the read data to the memory controller through the data pad (DQ pad) 115. The calibration circuit 120 can be a ZQ calibration circuit for performing a ZQ calibration operation to perform impedance calibration on the output circuit and the terminal resistor (On Die Termination, ODT) to maintain the integrity of multiple signals including the data signal. The output circuit 110 may include a pre-driver circuit 111 and an output driver circuit 112, wherein the output driver circuit 112 includes multiple pull-up driver units and multiple pull-down driver units. The pre-driver circuit 111 is used to receive read data and transmit the pre-driven read data to the output driver circuit 112. The output driver circuit 112 can receive the calibration code ZQCD provided by the calibration circuit 120 to adjust the resistance of the pull-up driver unit and the pull-down driver unit, and output the calibrated data through the data pad 115. In this way, compared with transmitting the calibration code ZQCD provided by the calibration circuit 120 to the pre-driver circuit 111, the output driver circuit 112 in the present disclosure directly receives the calibration code ZQCD, that is, the transmission path of the calibration code ZQCD does not need to pass through the pre-driver circuit 111, thereby reducing power consumption without affecting the memory transmission performance.

[0037] like Figure 2As shown, the pull-up drive unit 113 and the pull-down drive unit 114 are connected between the first voltage terminal VDDQ and the second voltage terminal VSS. The pull-up drive unit 113 may include multiple sets of transistors M1 and M2 connected in series, and the pull-down drive unit 114 may include multiple sets of transistors M3 and M4 connected in series. The pull-up data (DPU) and the pull-down data (DPD) are transmitted to the pre-driver circuit 111 through a data selector (Mux) controlled by a four-frequency sampling clock Wck, and then transmitted to the pull-up drive unit 113 and the pull-down drive unit 114 by the pre-driver circuit 111. In order to minimize the capacitance on the data pad 115 and meet the requirements of the Joint Electron Device Engineering Council (JEDEC) standard protocol for pull-up and pull-down resistors, the transistors M2 and M3 close to the data pad 115 are smaller in size, and the transistors M1 and M4 far from the data pad 115 are larger in size. In order to reduce the load of the pre-driver circuit 111, the data can be transmitted to the smaller transistors M2 and M3. In this way, the calibration code can be transmitted to the transistors M1 and M4. The calibration code provided by the calibration circuit here can include the pull-up calibration code PUCD and the pull-down calibration code PDCD. In addition, the JEDEC standard protocol also has certain requirements for the leakage current of the output driver circuit 112. Therefore, the transistors M1 and M4 used to receive the calibration code generally use thick-gate oxide transistors to control leakage, while the transistors M2 and M3 use thin-gate oxide transistors. It can be understood that each bit in the calibration code can control the conduction or cutoff of a transistor.

[0038] like Figure 3As shown, the calibration circuit 120 may include a calibration control circuit 123, a plurality of pull-up calibration units 121 having the same structure as the pull-up drive unit, and a plurality of pull-down calibration units 122 having the same structure as the pull-down drive unit. Accordingly, transistors M5 and M8 are thick-gate oxide transistors, while transistors M6 and M7 are thin-gate oxide transistors. During the ZQ calibration process, a voltage (e.g., 1.05V) is applied to transistors M6 and / or M7 to turn them on, and the pre-calibration code PreCD generated by the calibration control circuit 123 is transmitted to transistors M5 and / or M8. When the resistance value of the pull-up calibration unit 121 or the pull-down calibration unit 122 is equal to the standard resistance value, the pre-calibration code PreCD at this time is latched as the pull-up calibration code or the pull-down calibration code. However, since transistors M5 and M8 are thick-gate oxide transistors, the operating voltage of transistors M5 and M8 when they are turned on will be higher, making the high level of the calibration code higher. The calibration control circuit 123 requires a power domain with a higher voltage, which in turn increases the power consumption of the calibration circuit 120. For example, the high level of the calibration code transmitted to the thick-gate oxide transistor is 3V, that is, the calibration control circuit 123 operates in a 3V power domain. In some embodiments, the conventional calibration control circuit 123 operates in a 1.05V power domain. It is worth noting that the thick-gate oxide transistor and thin-gate oxide transistor here only refer to the relative size of the specific gate control voltage compared to the normal value. Thick gate oxide and thin gate oxide are relative to transistors with the same product structure and the same process node, and will not be described in detail below.

[0039] First, as Figure 4 As shown, the embodiment of the present disclosure provides a data transmission circuit 20, including a calibration circuit 200 and an output circuit ( Figure 4 The output circuit is not shown), and the calibration circuit 200 is connected to the output circuit; the calibration circuit 200 includes: a calibration control circuit 210, which is used to generate and output a calibration code ZQCD; a calibration unit 201, including a plurality of first transistors 202 and second transistors 203 connected in series; the gate of the first transistor 202 is connected to the calibration control circuit 210, and is used to receive the calibration code ZQCD; the calibration control circuit 210 is also used to control the conduction or cutoff of the plurality of first transistors 202 through the calibration code ZQCD, so as to adjust the resistance value of the calibration unit 201 to a standard resistance value; when the first transistor 202 is turned on, the first operating voltage on the gate is less than the second operating voltage on the gate when the second transistor 203 is turned on.

[0040] In an embodiment of the present disclosure, the calibration circuit 200 may include a calibration control circuit 210, and a plurality of calibration units 201. The calibration control circuit 210 may generate and output a calibration code ZQCD, and the calibration unit 201 may be a pull-up calibration unit and / or a pull-down calibration unit in the above-mentioned embodiment. Exemplarily, the pull-up calibration unit is connected between the detection node Node and the first voltage terminal, and the pull-down calibration unit is connected between the detection node Node and the second voltage terminal. Specifically, the calibration unit 201 may include a plurality of groups of first transistors 202 and second transistors 203 connected in series, the first end of the second transistor 203 may be connected to the first voltage terminal VDDQ or the second voltage terminal VSS, the second end of the second transistor 203 is connected to the first end of the first transistor 202, and the second end of the first transistor 202 may be connected to the detection node Node. During the ZQ calibration process, a voltage (such as 3V) is applied to the gate of the second transistor 203 to turn it on, and the gate of the first transistor 202 receives the pre-calibration code output by the calibration control circuit 210. The calibration control circuit 210 can determine whether the calibration unit 201 is adjusted to the standard resistance value based on the voltage of the detection node Node, and when the resistance value of the calibration unit 201 is equal to the standard resistance value, the pre-calibration code at this time is latched as the calibration code ZQCD. It can be understood that the detection node Node here can be connected to the second end of the plurality of first transistors 202. It is worth noting that the standard resistance value here can be determined by an external resistor. For example, the standard resistance value can be 240Ω. In the case where the first transistor and the second transistor are NMOS tubes, the first end of the above-mentioned transistor can be a drain, and the second end of the above-mentioned transistor can be a source, such as the drain of the second transistor is connected to the first voltage terminal VDDQ, and the source of the first transistor is connected to the detection node Node. Here, the first transistor 202 can be a thin-gate oxide transistor, that is, corresponding to the transistor M6 or M7 in the above embodiment, and the second transistor 203 can be a thick-gate oxide transistor, that is, corresponding to the transistor M5 or M8 in the above embodiment. When the first transistor 202 is turned on, the first operating voltage on the gate is less than the second operating voltage on the gate when the second transistor 203 is turned on. For example, the first operating voltage of the first transistor 202 can be 1.05V, and the second operating voltage of the second transistor 203 can be 3V. In this way, the first operating voltage of the first transistor 202 for receiving the calibration code ZQCD is relatively low, so the calibration control circuit 210 can use a power supply domain with a lower voltage, thereby reducing the power consumption of the entire data transmission circuit 20 without affecting the transmission performance of the output circuit. It can be understood that in the output circuit, the calibration code ZQCD can still be transmitted to the thick-gate oxide transistor, that is, the larger transistor, while the data signal is transmitted to the smaller transistor to reduce the load of the pre-driver circuit.

[0041] It is worth noting that when there is only a separate pull-up calibration unit or a pull-down calibration unit, the other end of the detection node is connected to an external resistor that provides a standard resistance value.

[0042] In some embodiments, as Figure 5 As shown, the output circuit 300 includes: a pull-up driving unit 301 and a pull-down driving unit 302 with the same structure as the calibration unit; the pull-up driving unit 301 and the pull-down driving unit 302 are connected between a first voltage terminal VDDQ and a second voltage terminal VSS; the pull-down driving unit 302 includes a plurality of groups of third transistors 303 and fourth transistors 304 connected in series, and the pull-up driving unit 301 includes a plurality of groups of fifth transistors 305 and sixth transistors 306 connected in series; the third transistor 303 and the fifth transistor 305 are the same as the first transistor, and the fourth transistor 304 and the sixth transistor 306 are the same as the second transistor; the gates of the fourth transistor 304 and the sixth transistor 306 are connected The calibration control circuit is used to receive the calibration code; the gates of the third transistor 303 and the fifth transistor 305 are used to receive data signals; the end of the third transistor 303 away from the fourth transistor 304 is connected to the data transmission end 315, and the end of the fifth transistor 305 away from the sixth transistor 306 is connected to the data transmission end 315; the calibration control circuit is also used to control the conduction or cutoff of multiple fourth transistors 304 and the sixth transistor 306 through the calibration code ZQCD to adjust the resistance values ​​of the pull-up drive unit 301 and the pull-down drive unit 302 to standard resistance values; the output circuit 300 is used to output the calibrated data signal through the data transmission end 315.

[0043] In the embodiments of the present disclosure, reference Figure 4 The first transistor 202 is connected between the second transistor 203 and the detection node Node. That is, the first transistor 202 for receiving the calibration code ZQCD is disposed close to the detection node Node. The first transistor 202 is a thin-gate oxide transistor with a low gate voltage when on. This allows the calibration control circuit to operate in a lower voltage power domain, thereby reducing power consumption of the data transmission circuit.

[0044] The output circuit 300 is connected to the calibration control circuit. After the ZQ calibration is completed, the calibration control circuit can adjust the resistance values ​​of the pull-up driving unit 301 and the pull-down driving unit 302 to the standard resistance values ​​through the calibration code ZQCD, so that the data signal output by the output circuit 300 has better integrity and higher transmission rate. It is worth noting that Figure 5 The calibration control circuit is not shown.

[0045] Exemplarily, the output circuit 300 includes a pull-up drive unit 301 and a pull-down drive unit 302. The pull-up / pull-down drive unit has the same structure as the calibration unit. The pull-down drive unit 302 may include multiple groups of third transistors 303 and fourth transistors 304 connected in series. Here, the third transistor 303 can be the same as the first transistor, that is, a transistor with a smaller size, and the fourth transistor 304 can be the same as the second transistor, that is, a transistor with a larger size. The third transistor 303 is close to the data transmission terminal 315, which can be the data pad in the above embodiment. The gate of the fourth transistor 304 is connected to the calibration control circuit and is used to receive the calibration code ZQCD. The gate of the third transistor 303 is used to receive the data signal. In other words, the calibration control circuit can control the conduction or shutdown of the multiple fourth transistors 304 according to the calibration code ZQCD to adjust the resistance value of the pull-down drive unit 302 to the standard resistance value.

[0046] The pull-up drive unit 301 includes multiple groups of fifth transistors 305 and sixth transistors 306 connected in series. Here, the fifth transistor 305 can be the same as the first transistor, i.e., a smaller transistor, and the sixth transistor 306 can be the same as the second transistor, i.e., a larger transistor. The fifth transistor 305 is close to the data transmission end 315, and the gate of the sixth transistor 306 is connected to the calibration control circuit and is used to receive the calibration code ZQCD. The gate of the fifth transistor 305 is used to receive the data signal. The calibration control circuit can control the conduction or closing of multiple sixth transistors 306 through the calibration code ZQCD to adjust the resistance value of the pull-up drive unit 301 to a standard resistance value. It is worth noting that the gate of the fifth transistor 305 in the pull-up drive unit 301 and the third transistor 303 in the pull-down drive unit 302 is used to receive the data signal DTA, while the gate of the other is used to receive the inverted data signal DTA_b. In this way, at the same time, only one of the pull-up drive unit 301 and the pull-down drive unit 302 is in the open state. Preferably, the fifth transistor 305 in the pull-up drive unit 301 can be the same as the third transistor 303 in the pull-down drive unit 302, and the fourth transistor 304 in the pull-up drive unit 301 can be the same as the sixth transistor 306 in the pull-down drive unit 302. In this way, in the output circuit 300, the calibration code ZQCD can still be transmitted to the larger fourth transistor 304 and the sixth transistor 306, while the data signal DTA and the inverted data signal DTA_b are transmitted to the smaller third transistor 303 and the fifth transistor 305, thereby reducing the load on the pre-driver circuit. It can be understood that although the calibration code ZQCD acts on the fourth transistor 304 and the sixth transistor 306, the number of fourth transistors 304 or sixth transistors 306 that are turned on in the drive unit is the same as the number of first transistors that are turned on in the calibration unit, that is, the driving strength of the drive unit does not change.

[0047] In some embodiments, the gate oxide layers of the first transistor, the third transistor, and the fifth transistor have a first thickness, the gate oxide layers of the second transistor, the fourth transistor, and the sixth transistor have a second thickness, and the first thickness is less than the second thickness.

[0048] In an embodiment of the present disclosure, the first thickness of the gate oxide layer of the first transistor, the third transistor, and the fifth transistor is less than the second thickness of the gate oxide layer of the second transistor, the fourth transistor, and the sixth transistor. For example, the first transistor, the third transistor, and the fifth transistor can be the same, all thin-gate oxide transistors, and the operating voltage when turned on is the first operating voltage; the second transistor, the fourth transistor, and the sixth transistor can be the same, all thick-gate oxide transistors, and the operating voltage when turned on is the second operating voltage, and the first operating voltage is less than the second operating voltage. It should be noted that the thick-gate oxide transistor and the thin-gate oxide transistor here only refer to the relative size of the gate control voltage compared to the normal value, and the thick gate oxide and the thin gate oxide are relative to the transistors with the same product structure and the same process node.

[0049] In this way, the gate of the first transistor in the calibration unit is used to receive the calibration code, and the operating voltage of the gate is low when the first transistor is turned on, so as to reduce the load of the calibration control circuit; and the gates of the third transistor and the fifth transistor in the driving unit are used to receive the calibration code, and the operating voltage of the gate is low when the third transistor and the fifth transistor are turned on, so as to reduce the load of the pre-driving circuit, that is, without affecting the transmission performance of the output circuit, the power consumption of the entire data transmission circuit is reduced.

[0050] refer to Figure 4 , the embodiment of the present disclosure provides another data transmission circuit 20, including a calibration circuit 200 and an output circuit ( Figure 4 (output circuit not shown), the calibration circuit 200 is connected to the output circuit; the calibration circuit 200 includes: a calibration control circuit 210, for generating and outputting a calibration code ZQCD; a calibration unit 201, connected between the detection node and the first voltage terminal or the detection node and the second voltage terminal; the calibration unit 201 includes a plurality of groups of first transistors 202 and second transistors 203 connected in series; the first transistor 202 is connected between the second transistor 203 and the detection node Node; the gate of the first transistor 202 is connected to the calibration control circuit 210 and is used to receive the calibration code ZQCD; the calibration control circuit 210 is also used to generate the calibration code ZQCD according to the voltage value obtained from the detection node Node, and control the conduction or cutoff of multiple first transistors 202 through the calibration code ZQCD to adjust the resistance value of the calibration unit 201 to the standard resistance value.

[0051] In some embodiments, a first operating voltage on the gate of the first transistor 202 when the first transistor 202 is turned on is less than a second operating voltage on the gate of the second transistor 203 when the second transistor 203 is turned on.

[0052] In the embodiments of the present disclosure, reference Figure 4 , the first transistor 202 is connected between the second transistor 203 and the detection node Node. That is, the first transistor 202 for receiving the calibration code ZQCD is located close to the detection node Node, and the first transistor 202 can be a thin-gate oxide transistor with a low operating voltage on the gate when it is turned on; while the gate of the second transistor 203, which is farther away from the detection node Node, can be applied with a turn-on voltage (e.g., 3V) to turn on the second transistor 203, and the second transistor 203 can be a thick-gate oxide transistor with a high operating voltage on the gate when it is turned on. In this way, the calibration control circuit can operate in a lower voltage power domain, thereby reducing the power consumption of the data transmission circuit.

[0053] For example, when the first transistor 202 is turned on, the first operating voltage on the gate may be 1.05V, that is, the high level of the calibration code ZQCD may be 1.05V; when the second transistor 203 is turned on, the second operating voltage on the gate may be 3V.

[0054] In some embodiments, as Figure 6 As shown, the calibration circuit 200 further includes: a voltage converter 220 connected between the calibration control circuit 210 and the output circuit 300; the voltage converter 220 is used to convert the operating voltage of the calibration code ZQCD signal from the first operating voltage to the second operating voltage.

[0055] In the embodiment of the present disclosure, the gate of the first transistor in the calibration unit 201 receives the pre-calibration code output by the calibration control circuit 210, and the first transistor is a thin-gate oxide transistor. Therefore, the voltage of the calibration code ZQCD generated by the calibration control circuit 210 is relatively low, which is the first operating voltage. In the output circuit 300, the fourth transistor and the sixth transistor for receiving the calibration code ZQCD are thick-gate oxide transistors. The operating voltage of the fourth transistor and the sixth transistor when they are turned on is the second operating voltage. This means that the calibration code ZQCD output by the calibration control circuit 210 needs to undergo voltage conversion before it can be applied to the fourth transistor and the sixth transistor. Therefore, the voltage converter (Level Shifter) 220 can be connected between the calibration control circuit 210 and the output circuit 300 to convert the voltage of the calibration code ZQCD from the first operating voltage to the second operating voltage.

[0056] In some embodiments, as Figure 5As shown, the first end of the fourth transistor 304 is connected to the second voltage end, the second end of the fourth transistor 304 is connected to the first end of the third transistor 303, and the second end of the third transistor 303 is connected to the data transmission end 315; the first end of the sixth transistor 306 is connected to the first voltage end, the second end of the sixth transistor 306 is connected to the first end of the fifth transistor 305, and the second end of the fifth transistor 305 is connected to the data transmission end 315.

[0057] In the embodiment of the present disclosure, the pull-up driving unit 301 and the pull-down driving unit 302 are connected between a first voltage terminal VDDQ and a second voltage terminal VSS, and a data transmission terminal 315 is provided between the pull-up driving unit 301 and the pull-down driving unit 302. For example, in the pull-up driving unit 301, a first terminal of the sixth transistor 306 is connected to the first voltage terminal VDDQ, a second terminal of the sixth transistor 306 is connected to the first terminal of the fifth transistor 305, and a second terminal of the fifth transistor 305 is connected to the data transmission terminal 315. In the pull-down driving unit 302, a first terminal of the fourth transistor 304 is connected to the second voltage terminal VSS, a second terminal of the fourth transistor 304 is connected to the first terminal of the third transistor 303, and a second terminal of the third transistor 303 is connected to the data transmission terminal 315. In this manner, the calibration control circuit can control the conduction or discontinuation of the plurality of fourth transistors 304 or sixth transistors 306 using the calibration code ZQCD to adjust the resistance values ​​of the pull-up driving unit 301 and the pull-down driving unit 302 to a standard resistance value. It is worth noting that the first end of the above-mentioned transistor can be a drain and the second end can be a source; or the first end of the above-mentioned transistor can be a source and the second end can be a drain. There is no limitation here. The specific situation is determined according to the type of transistor (PMOS tube or NMOS tube) and the connection method of the two ends.

[0058] In some embodiments, as Figure 7As shown, the calibration unit includes: a pull-down calibration unit 230 and a pull-up calibration unit 240; the pull-up calibration unit 240 is connected between the first voltage terminal VDDQ and the detection node, and the pull-down calibration unit 230 is connected between the second voltage terminal VSS and the detection node; the pull-down calibration unit 230 has the same structure as the pull-down drive unit; the pull-up calibration unit 240 has the same structure as the pull-up drive unit; the calibration code includes: a first calibration code and a second calibration code; the calibration control circuit 210 is further configured to generate and output a changing pre-calibration code PreCD according to the voltage value obtained from the detection node to adjust the resistance value of the calibration unit; when the resistance value of the pull-down calibration unit 230 is equal to the standard resistance value, the calibration control circuit 210 determines that the pre-calibration code PreCD is the first calibration code; when the resistance value of the pull-up calibration unit 240 is equal to the standard resistance value, the calibration control circuit 210 determines that the pre-calibration code is the second calibration code.

[0059] In an embodiment of the present disclosure, the calibration unit may include: a pull-down calibration unit 230 having the same structure as the pull-down drive unit, and a pull-up calibration unit 240 having the same structure as the pull-up drive unit. During impedance calibration of the pull-down calibration unit 230, the calibration control circuit 210 may output a varying pre-calibration code PreCD to the pull-down calibration unit 230 based on a voltage value obtained from a detection node to adjust the resistance value of the pull-down calibration unit 230. When the resistance value of the pull-down calibration unit 230 is equal to a standard resistance value, the calibration control circuit 210 latches the pre-calibration code PreCD at this time as a first calibration code. During impedance calibration of the pull-up calibration unit 240, the calibration control circuit 210 may output a varying pre-calibration code PreCD to the pull-up calibration unit 240 based on a voltage value obtained from a detection node to adjust the resistance value of the pull-up calibration unit 240. When the resistance value of the pull-up calibration unit 240 is equal to the standard resistance value, the calibration control circuit 210 latches the pre-calibration code PreCD at this time as a second calibration code. It can be understood that the first calibration code here may be the pull-down calibration code in the above embodiment, and the second calibration code may be the pull-up calibration code in the above embodiment.

[0060] In some embodiments, the calibration control circuit is further used to adjust the resistance value of the pull-down drive unit to the standard resistance value through the first calibration code, and to adjust the resistance value of the pull-up drive unit to the standard resistance value through the second calibration code, so that the output circuit outputs the calibrated data signal.

[0061] In the embodiment of the present disclosure, since the pull-down calibration unit and the pull-down drive unit have the same structure, the first calibration code can make the resistance value of the pull-down drive unit equal to the resistance value of the pull-down calibration unit, that is, equal to the standard resistance value; since the pull-up calibration unit and the pull-up drive unit have the same structure, the second calibration code can make the resistance value of the pull-up drive unit equal to the resistance value of the pull-up calibration unit, that is, equal to the standard resistance value. In this way, the output circuit can output the calibrated data signal through the pull-up drive unit and the pull-down drive unit with standard resistance values, which is conducive to ensuring the integrity and transmission rate of the data signal. It can be understood that the transistor that receives the calibration code in the pull-up / pull-down calibration unit (such as the first transistor) and the transistor that receives the data signal in the pull-up / pull-down drive unit (such as the third transistor and the fifth transistor) operate at the same voltage.

[0062] In some embodiments, as Figure 7 As shown, the detection node includes a first node N1 and a second node N2, and the calibration circuit 200 further includes: an external resistor 205 for providing the standard resistance value; the pull-down calibration unit 230 includes: a first pull-down calibration unit 231 and a second pull-down calibration unit 232; the first pull-down calibration unit 231 and the external resistor 205 are connected between the first voltage terminal VDDQ and the second voltage terminal VSS; there is the first node N1 between the first pull-down calibration unit 231 and the external resistor 205; the second pull-down calibration unit 232 and the pull-up calibration unit 240 are connected to the first voltage terminal VDDQ and the second voltage terminal VSS; there is a second node N2 between the second pull-down calibration unit 232 and the pull-up calibration unit 240; the calibration control circuit 210 is specifically used to latch the pre-calibration code PreCD as the first calibration code when the first voltage V1 of the first node N1 is equal to the first reference voltage Refpd; the calibration control circuit 210 is also used to output the first calibration code to the second pull-down calibration unit 232, and latch the pre-calibration code PreCD as the second calibration code when the second voltage V2 of the second node N2 is equal to the second reference voltage Refpu.

[0063] In the embodiment of the present disclosure, the external resistor 205 is connected to the first pull-down calibration unit 231, and the second pull-down calibration unit 232 is connected to the pull-up calibration unit 240. In this manner, the calibration control circuit 210 can perform impedance calibration on the first pull-down calibration unit 231 via the external resistor 205 to adjust the resistance value of the first pull-down calibration unit 231 to a standard resistance value. The calibration control circuit 210 can also perform impedance calibration on the pull-up calibration unit 240 via the second pull-down calibration unit 232 to adjust the resistance value of the pull-up calibration unit 240 to a standard resistance value.

[0064] Specifically, the calibration control circuit 210 can detect a first voltage V1 at the first node N1 and a second voltage V2 at the second node N2. When the first voltage V1 is equal to the first reference voltage Refpd, it indicates that the resistance of the first pull-down calibration unit 231 is equal to the resistance of the external resistor 205, i.e., the standard resistance value. Therefore, the calibration control circuit 210 can latch the pre-calibration code PreCD at this time as the first calibration code. The calibration control circuit 210 can also output the first calibration code to the second pull-down calibration unit 232 to adjust the resistance value of the second pull-down calibration unit 232 to the standard resistance value. When the second voltage V2 is equal to the second reference voltage Refpu, it indicates that the resistance of the pull-up calibration unit 240 is equal to the standard resistance value. Therefore, the calibration control circuit 210 can latch the pre-calibration code PreCD at this time as the second calibration code.

[0065] In some embodiments, in order to simplify the setting of the circuit and power domain, the first reference voltage Refpd and the second reference voltage Refpu can be equal to VDDQ / 2; in other embodiments, the first reference voltage Refpd and the second reference voltage Refpu can be unequal, and the specific values ​​of the two can be determined according to the actual needs of the circuit.

[0066] In some embodiments, as Figure 8 As shown, the calibration circuit 200 may further include a first pull-up calibration unit 241 connected to the external resistor 205, and a second pull-up calibration unit 242 connected to the pull-down calibration unit 230. In other words, the calibration control circuit 210 may first perform impedance calibration on the first pull-up calibration unit 241 to obtain a third calibration code, and transmit the third calibration code to the second pull-up calibration unit 242. The second pull-up calibration unit 242 may then perform impedance calibration on the pull-down calibration unit 230 to obtain a fourth calibration code. The third calibration code and the fourth calibration code are provided to the pull-up drive unit and the pull-down drive unit, respectively.

[0067] In some embodiments, as Figure 7As shown, the calibration control circuit 210 includes: a voltage generating circuit 211, including a first output terminal out1 for outputting the first reference voltage Refpd and a second output terminal out2 for outputting the second reference voltage Refpu; a comparator 212, used to compare the first voltage V1 with the first reference voltage Refpd to output a first comparison signal Compout1, or compare the second voltage V2 with the second reference voltage Refpu to output a second comparison signal Compout2; a calibration code generating circuit 213, connected to the comparator 212; the calibration code generating circuit 213 is used to generate the changing pre-calibration code PreCD; the calibration code generating circuit 213 is further used to latch the pre-calibration code PreCD as the first calibration code according to the first comparison signal Compout1, and latch the pre-calibration code PreCD as the second calibration code according to the second comparison signal Compout2.

[0068] In the disclosed embodiment, the calibration control circuit 210 includes a voltage generation circuit 211, a comparator 212, and a calibration code generation circuit 213. The input of the comparator 212 is connected to the voltage generation circuit 211, a first node N1, and a second node N2, and the output of the comparator 212 is connected to the calibration code generation circuit 213. The voltage generation circuit 211 may include multiple resistors connected in series between a first voltage terminal VDDQ and a second voltage terminal VSS, and a plurality of voltage output terminals located between different resistors to generate the at least two reference voltages Refpd and Refpu. When the first voltage V1 is equal to the first reference voltage Refpd, the level of the first comparison signal Compout1 output by the comparator 212 is reversed, so that the calibration code generation circuit 213 can latch the pre-calibration code PreCD at this time as the first calibration code. When the second voltage V2 is equal to the second reference voltage Refpu, the level of the second comparison signal Compout2 output by the comparator 212 is reversed, so that the calibration code generation circuit 213 can latch the pre-calibration code PreCD at this time as the second calibration code. Exemplarily, the calibration code generating circuit 213 may utilize a bisection method to generate and latch the pre-calibration code PreCD as the first calibration code or the second calibration code.

[0069] In some embodiments, as Figure 7 As shown, the calibration control circuit 210 also includes: a calibration selection circuit 214, connected to the comparator 212 and the calibration code generation circuit 213; the calibration selection circuit 214 is used to output a selection signal Sel to select to compare the first voltage V1 with the first reference voltage Refpd, or to compare the second voltage V2 with the second reference voltage Refpu.

[0070] In the embodiment of the present disclosure, the calibration selection circuit 214 is configured to generate a selection signal Sel to determine the order of performing impedance calibration operations on the pull-down calibration unit 230 and the pull-up calibration unit 240 .

[0071] In some embodiments, as Figure 7 As shown, the calibration control circuit 210 also includes: a first selection unit 215, the input end of the first selection unit 215 is connected to the first node N1 and the second node N2, the output end of the first selection unit 215 is connected to the comparator 212, and the selection end of the first selection unit 215 is connected to the calibration selection circuit 214; the first selection unit 215 is used to select the first voltage V1 or the second voltage V2 according to the selection signal Sel to output to the comparator 212.

[0072] In the embodiment of the present disclosure, the calibration selection circuit 214 can control the first selection unit 215 to output the first voltage V1 or the second voltage V2 to the comparator 212 through the selection signal Sel, so that the comparator 212 compares the first voltage V1 with the first reference voltage Refpd, or compares the second voltage V2 with the second reference voltage Refpu. The first selection unit 215 here can be a data selector.

[0073] In some embodiments, as Figure 7 As shown, the calibration control circuit 210 also includes: a second selection unit 216, the input end of the second selection unit 216 is connected to the first output end out1 and the second output end out2 of the voltage generating circuit 211, the output end of the second selection unit 216 is connected to the comparator 212, and the selection end of the second selection unit 216 is connected to the calibration selection circuit 214; the second selection unit 216 is used to select the first reference voltage Refpd or the second reference voltage Refpu according to the selection signal Sel to output to the comparator 212.

[0074] In the embodiment of the present disclosure, the voltage generating circuit 211 may have a first output terminal out1 and a second output terminal out2 to output a first reference voltage Refpd and a second reference voltage Refpu, respectively. The calibration selection circuit 214 may control the second selection unit 216 to output the first reference voltage Refpd or the second reference voltage Refpu to the comparator 212 via a selection signal Sel, thereby causing the comparator 212 to compare the first voltage V1 with the first reference voltage Refpd, or compare the second voltage V2 with the second reference voltage Refpu. The second selection unit 216 may be a data selector.

[0075] In some embodiments, as Figure 7As shown, the calibration control circuit 210 further includes: an oscillator 217 connected to the calibration selection circuit 214, the comparator 212 and the calibration code generation circuit 213; the oscillator 217 is used to provide a calibration clock signal ZQclk.

[0076] In the embodiment of the present disclosure, the calibration control circuit 210 further includes an oscillator 217 for providing a calibration clock signal ZQclk. The oscillator 217 can ensure synchronous operation of the calibration selection circuit 214, the comparator 212 and the calibration code generation circuit 213 through the calibration clock signal ZQclk.

[0077] like Figure 9 As shown, the embodiment of the present disclosure further provides a data transmission circuit 20 , including: an output circuit 300 connected to the calibration control circuit 210 ; an input circuit 410 , connected together with the output circuit 300 to a data transmission terminal 315 .

[0078] In the disclosed embodiment, the data transmission circuit 20 can be used for data input and output of the memory. The calibration control circuit 210 can provide a calibration code to the output circuit 300 to adjust the impedance of the output circuit 300 and maintain the integrity of the data signal. The input circuit 410 and the output circuit 300 can share a data transmission terminal 315, which can be the data pad in the above-mentioned embodiment.

[0079] Second, as Figure 10 As shown, an embodiment of the present disclosure provides a memory 500 , including: a peripheral circuit 510 , including the data transmission circuit 20 according to any one of the above embodiments; and a memory cell array 520 , connected to the peripheral circuit 510 .

[0080] In the embodiment of the present disclosure, the memory 500 includes, but is not limited to, DRAM, static random access memory (SRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc. The peripheral circuit 510 is connected to the memory cell array 520, and the data transmission circuit 20 is located in the peripheral circuit 510. In this way, in the data transmission circuit 20, the first operating voltage of the first transistor for receiving the calibration code is relatively low, so the calibration control circuit can use a lower voltage power domain, thereby reducing the power consumption of the entire data transmission circuit 20 without affecting the transmission performance of the output circuit.

[0081] It should be noted that the features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0082] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A data transmission circuit, characterized in that: The device comprises a calibration circuit and an output circuit, wherein the calibration circuit is connected to the output circuit; the calibration circuit comprises: A calibration control circuit, configured to generate and output a calibration code; A calibration unit comprising a plurality of groups of first transistors and second transistors connected in series; The gate of the first transistor is connected to the calibration control circuit and is used to receive the calibration code; the calibration control circuit is further used to control the conduction or cutoff of the plurality of first transistors according to the calibration code, so as to adjust the resistance value of the calibration unit to a standard resistance value; A first operating voltage on the gate of the first transistor when it is turned on is lower than a second operating voltage on the gate of the second transistor when it is turned on.

2. The data transmission circuit according to claim 1, wherein: The output circuit includes: a pull-up driving unit and a pull-down driving unit having the same structure as the calibration unit; the pull-up driving unit and the pull-down driving unit are connected between a first voltage terminal and a second voltage terminal; the pull-down driving unit includes a plurality of sets of third transistors and fourth transistors connected in series, and the pull-up driving unit includes a plurality of sets of fifth transistors and sixth transistors connected in series; The third transistor and the fifth transistor are the same as the first transistor, and the fourth transistor and the sixth transistor are the same as the second transistor; the gates of the fourth transistor and the sixth transistor are connected to the calibration control circuit and are used to receive the calibration code; the gates of the third transistor and the fifth transistor are used to receive data signals; an end of the third transistor away from the fourth transistor is connected to a data transmission end, and an end of the fifth transistor away from the sixth transistor is connected to the data transmission end; The calibration control circuit is further configured to control the on or off state of the fourth transistor and the sixth transistor through the calibration code, so as to adjust the resistance values ​​of the pull-up driving unit and the pull-down driving unit to standard resistance values; and the output circuit is configured to output the calibrated data signal through the data transmission end.

3. The data transmission circuit according to claim 2, wherein: The calibration circuit further includes: A voltage converter is connected between the calibration control circuit and the output circuit; the voltage converter is used to convert the voltage of the calibration code from the first operating voltage to the second operating voltage.

4. The data transmission circuit according to claim 2, wherein: The first end of the fourth transistor is connected to the second voltage end, the second end of the fourth transistor is connected to the first end of the third transistor, and the second end of the third transistor is connected to the data transmission end; the first end of the sixth transistor is connected to the first voltage end, the second end of the sixth transistor is connected to the first end of the fifth transistor, and the second end of the fifth transistor is connected to the data transmission end.

5. The data transmission circuit according to claim 2, wherein: The calibration unit includes: a pull-down calibration unit and a pull-up calibration unit; the pull-up calibration unit is connected between the first voltage terminal and the detection node, and the pull-down calibration unit is connected between the second voltage terminal and the detection node; the pull-down calibration unit has the same structure as the pull-down driving unit; the pull-up calibration unit has the same structure as the pull-up driving unit; the calibration code includes: a first calibration code and a second calibration code; The calibration control circuit is further configured to generate and output a changing pre-calibration code according to the voltage value obtained from the detection node to adjust the resistance value of the calibration unit; When the resistance value of the pull-down calibration unit is equal to the standard resistance value, the calibration control circuit determines that the pre-calibration code is the first calibration code; When the resistance value of the pull-up calibration unit is equal to the standard resistance value, the calibration control circuit determines that the pre-calibration code is the second calibration code.

6. The data transmission circuit according to claim 5, characterized in that: The detection node includes a first node and a second node, and the calibration circuit further includes: an external resistor, used to provide the standard resistance value; The pull-down calibration unit includes: a first pull-down calibration unit and a second pull-down calibration unit; The first pull-down calibration unit and the external resistor are connected between the first voltage terminal and the second voltage terminal; there is a first node between the first pull-down calibration unit and the external resistor; The second pull-down calibration unit and the pull-up calibration unit are connected between the first voltage terminal and the second voltage terminal; a second node is provided between the second pull-down calibration unit and the pull-up calibration unit; The calibration control circuit is specifically configured to latch the pre-calibration code as the first calibration code when the first voltage of the first node is equal to a first reference voltage; The calibration control circuit is further configured to output the first calibration code to the second pull-down calibration unit, and latch the pre-calibration code as the second calibration code when the second voltage at the second node is equal to a second reference voltage.

7. The data transmission circuit according to claim 6, characterized in that: The calibration control circuit comprises: a voltage generating circuit comprising a first output terminal for outputting the first reference voltage and a second output terminal for outputting the second reference voltage; a comparator, configured to compare the first voltage with the first reference voltage to output a first comparison signal, or to compare the second voltage with the second reference voltage to output a second comparison signal; a calibration code generating circuit connected to the comparator; the calibration code generating circuit is used to generate the changed pre-calibration code; the calibration code generating circuit is further used to latch the pre-calibration code as the first calibration code according to the first comparison signal, and latch the pre-calibration code as the second calibration code according to the second comparison signal; a calibration selection circuit connected to the comparator and the calibration code generation circuit; the calibration selection circuit is used to output a selection signal to select comparison between the first voltage and the first reference voltage, or comparison between the second voltage and the second reference voltage; a first selection unit, wherein an input end of the first selection unit is connected to the first node and the second node, an output end of the first selection unit is connected to the comparator, and a selection end of the first selection unit is connected to the calibration selection circuit; the first selection unit is configured to select the first voltage or the second voltage to output to the comparator according to the selection signal; A second selection unit, wherein the input end of the second selection unit is connected to the first output end and the second output end of the voltage generating circuit, the output end of the second selection unit is connected to the comparator, and the selection end of the second selection unit is connected to the calibration selection circuit; the second selection unit is used to select the first reference voltage or the second reference voltage according to the selection signal to output to the comparator.

8. The data transmission circuit according to claim 2, wherein: The gate oxide layers of the first transistor, the third transistor, and the fifth transistor have a first thickness, and the gate oxide layers of the second transistor, the fourth transistor, and the sixth transistor have a second thickness, and the first thickness is smaller than the second thickness.

9. A data transmission circuit, characterized in that: The device comprises a calibration circuit and an output circuit, wherein the calibration circuit is connected to the output circuit; the calibration circuit comprises: A calibration control circuit, configured to generate and output a calibration code; a calibration unit connected between the detection node and the first voltage terminal or between the detection node and the second voltage terminal; the calibration unit comprises a plurality of groups of first transistors and second transistors connected in series; The first transistor is connected between the second transistor and the detection node; The gate of the first transistor is connected to the calibration control circuit and is used to receive the calibration code; The calibration control circuit is further configured to generate the calibration code according to the voltage value obtained from the detection node, and control the on or off of the plurality of first transistors by using the calibration code to adjust the resistance value of the calibration unit to a standard resistance value.

10. The data transmission circuit according to claim 9, characterized in that: The output circuit includes: A pull-up driving unit and a pull-down driving unit having the same structure as the calibration unit; the pull-down driving unit comprises a plurality of sets of third transistors and fourth transistors connected in series, and the pull-up driving unit comprises a plurality of sets of fifth transistors and sixth transistors connected in series; The third transistor and the fifth transistor are the same as the first transistor, and the fourth transistor and the sixth transistor are the same as the second transistor; the gates of the fourth transistor and the sixth transistor are connected to the calibration control circuit and are used to receive the calibration code; the gates of the third transistor and the fifth transistor are used to receive data signals; an end of the third transistor away from the fourth transistor is connected to a data transmission end, and an end of the fifth transistor away from the sixth transistor is connected to the data transmission end; The calibration control circuit is further configured to control the on or off state of the fourth transistor and the sixth transistor through the calibration code, so as to adjust the resistance values ​​of the pull-up driving unit and the pull-down driving unit to standard resistance values; and the output circuit is configured to output the calibrated data signal through the data transmission end.

11. The data transmission circuit according to claim 9, wherein: A first operating voltage on the gate of the first transistor when it is turned on is lower than a second operating voltage on the gate of the second transistor when it is turned on.

12. The data transmission circuit according to claim 11, wherein: The calibration circuit further includes: A voltage converter is connected between the calibration control circuit and the output circuit; the voltage converter is used to convert the voltage of the calibration code from the first operating voltage to the second operating voltage.

13. The data transmission circuit according to claim 10, wherein: The calibration unit includes: a pull-down calibration unit and a pull-up calibration unit; the pull-down calibration unit has the same structure as the pull-down driving unit; the pull-up calibration unit has the same structure as the pull-up driving unit; the calibration code includes: a first calibration code and a second calibration code; The calibration control circuit is further configured to generate and output a changing pre-calibration code according to the voltage value obtained from the detection node to adjust the resistance value of the calibration unit; When the resistance value of the pull-down calibration unit is equal to the standard resistance value, the calibration control circuit determines that the pre-calibration code is the first calibration code; When the resistance value of the pull-up calibration unit is equal to the standard resistance value, the calibration control circuit determines that the pre-calibration code is the second calibration code.

14. The data transmission circuit according to claim 13, wherein: The detection node includes a first node and a second node, and the calibration circuit further includes: an external resistor, used to provide the standard resistance value; The pull-down calibration unit includes: a first pull-down calibration unit and a second pull-down calibration unit; The first pull-down calibration unit and the external resistor are connected between the first voltage terminal and the second voltage terminal; there is a first node between the first pull-down calibration unit and the external resistor; The second pull-down calibration unit and the pull-up calibration unit are connected between the first voltage terminal and the second voltage terminal; a second node is provided between the second pull-down calibration unit and the pull-up calibration unit; The calibration control circuit is specifically configured to latch the pre-calibration code as the first calibration code when the first voltage of the first node is equal to a first reference voltage; The calibration control circuit is further configured to output the first calibration code to the second pull-down calibration unit, and latch the pre-calibration code as the second calibration code when the second voltage at the second node is equal to a second reference voltage.

15. A memory, characterized in that: include: A peripheral circuit comprising the data transmission circuit according to any one of claims 1 to 14; The memory cell array is connected to the peripheral circuit.

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