Junction field effect transistor and its preparation method and application

Abstract

The present invention relates to a junction field effect transistor and a preparation method and application thereof. The junction field effect transistor comprises a substrate, an N-type In2Se3 thin film layer and a P-type SnSe thin film layer which are stacked in sequence, the N-type In2Se3 thin film layer is provided with a source electrode and a drain electrode on a surface away from the substrate, a channel is formed between the source electrode and the drain electrode, the P-type SnSe thin film layer is arranged in the channel and is isolated from the source electrode and the drain electrode, a gate electrode is provided on the P-type SnSe thin film layer, wherein the thickness ratio of the N-type In2Se3 thin film layer to the P-type SnSe thin film layer is 1:1.5~1:2. The junction field effect transistor provided by the present invention can take into account high input impedance, low noise and high integration, and at the same time has programmability, storage, low power consumption and neural synaptic characteristics, etc., and has broad application prospects.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor electronic devices, and in particular to a junction field effect transistor and a preparation method and application thereof. Background Art

[0002] Junction field effect transistor (JFET) is an electronic device made of P-type and N-type semiconductor materials. The contact between P-type and N-type semiconductor materials forms a PN junction depletion region. The width of the PN junction depletion region is adjusted by the gate electrode voltage, thereby controlling the conduction and shutdown of the current in the channel. Due to its advantages such as high input impedance and low noise, junction field effect transistors have been widely used in electronic devices such as amplifiers and switching circuits.

[0003] With the rapid development of electronic devices, requirements have been put forward for high integration, programmability and versatility of junction field effect transistors. However, existing junction field effect transistors based on two-dimensional materials such as graphene and molybdenum disulfide have high power consumption, insufficient performance stability at a tiny size, low integration, and difficulty in achieving functions such as programmability, storage, low power consumption and neural synaptic characteristics. Therefore, there is an urgent need for a junction field effect transistor that combines high input impedance, low noise and high integration, as well as programmability and versatility. Summary of the invention

[0004] Based on this, it is necessary to provide a junction field effect transistor and its preparation method and application to address the above problems. The junction field effect transistor of the present invention can take into account high input impedance, low noise and high integration, and at the same time has programmability, storage, low power consumption and neural synaptic characteristics, etc., and has broad application prospects.

[0005] A junction field effect transistor comprises a substrate, an N-type In2Se3 thin film layer and a P-type SnSe thin film layer which are stacked in sequence, wherein a source electrode and a drain electrode are provided on a surface of the N-type In2Se3 thin film layer away from the substrate, a channel is formed between the source electrode and the drain electrode, the P-type SnSe thin film layer is provided in the channel and is isolated from the source electrode and the drain electrode, and a gate electrode is provided on the P-type SnSe thin film layer, wherein a thickness ratio of the N-type In2Se3 thin film layer to the P-type SnSe thin film layer is 1:1.5~1:2.

[0006] In one of the embodiments, the thickness of the N-type In2Se3 thin film layer is 30nm~50nm.

[0007] In one embodiment, the thickness of the P-type SnSe thin film layer is 50nm~100nm.

[0008] In one embodiment, the width of the P-type SnSe thin film layer accounts for more than 50% of the length of the channel.

[0009] In one embodiment, the length of the channel is 1 μm to 2 μm.

[0010] In one embodiment, the source electrode, the drain electrode and the gate electrode each include a first metal layer and a second metal layer stacked in layers, the first metal layer is selected from at least one of chromium, titanium, platinum and nickel, and the second metal layer is selected from at least one of gold, silver, copper, platinum and palladium;

[0011] And / or, the substrate is selected from at least one of silicon, silicon dioxide, aluminum oxide, glass and polyethylene terephthalate.

[0012] In one embodiment, the thickness of the first metal layer is 3nm-20nm, and the thickness of the second metal layer is 30nm-80nm.

[0013] A method for preparing the junction field effect transistor as described above comprises the following steps:

[0014] The N-type In2Se3 thin film obtained by mechanical stripping is transferred to a substrate to form an N-type In2Se3 thin film layer;

[0015] Transferring the P-type SnSe thin film obtained by mechanical stripping onto the N-type In2Se3 thin film layer to form a P-type SnSe thin film layer;

[0016] A source electrode and a drain electrode are deposited on the surface of the N-type In2Se3 thin film layer, so that the P-type SnSe thin film layer is arranged between the source electrode and the drain electrode and isolated from the source electrode and the drain electrode, and a gate electrode is deposited on the P-type SnSe thin film layer to obtain the junction field effect transistor.

[0017] In one of the embodiments, when depositing the source electrode and the drain electrode, the temperature is less than 180°C.

[0018] An application of the junction field effect transistor as described above in an electronic device.

[0019] The above-mentioned junction field effect transistor adopts an N-type In2Se3 thin film layer and a P-type SnSe thin film layer of specific thickness. On the one hand, the depletion region of the PN junction is close to one side of the N-type In2Se3 thin film layer, thereby realizing precise control of the channel conductance and preventing electric field asymmetry during operation, thereby effectively improving the rectification characteristics, switching characteristics and electrical performance of the PN junction; on the other hand, the ferroelectric polarization characteristics and excellent conductivity of the In2Se3 channel of the junction field effect transistor are effectively realized, the demand for an external electric field is reduced, the power consumption of the junction field effect transistor is reduced, and the integration is improved. At the same time, the programmability, storage, low power consumption and synaptic characteristics of the junction field effect transistor are realized.

[0020] Therefore, the junction field effect transistor provided by the present invention not only has the advantages of high input impedance and low noise, but also has high integration, programmability, low power consumption and versatility. It has broad application prospects, especially in the fields of information perception and storage, programmable electronic devices and neuromorphic electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 is a schematic structural diagram of a junction field effect transistor in one embodiment of the present invention;

[0023] Figure 2 The transfer characteristic curve of the junction field effect transistor prepared in Example 1 of the present invention;

[0024] Figure 3 The linear region output characteristic curve of the junction field effect transistor obtained in Example 1 of the present invention;

[0025] Figure 4 The saturation region output characteristic curve of the junction field effect transistor obtained in Example 1 of the present invention;

[0026] Figure 5 The pulse voltage control resistance switching performance diagram of the junction field effect transistor prepared in Example 1 of the present invention, the test conditions are that the forward pulse gate voltage has an amplitude of +2V, a pulse width of 400 microseconds, and the control device is in a high resistance state, the reverse pulse gate voltage has an amplitude of -2V, a pulse width of 400 microseconds, and the control device is in a low resistance state, and the gate voltage for reading the resistance state is -1V;

[0027] Figure 6This is a graph showing the long-range enhancement and suppression characteristics of the junction field effect transistor obtained in Example 1 of the present invention;

[0028] Figure 7 This is a double pulse facilitation characteristic diagram of the junction field effect transistor prepared in Example 1 of the present invention.

[0029] Figure numerals: 1, substrate; 2, N-type In2Se3 thin film layer; 3, P-type SnSe thin film layer; 4, source electrode; 5, drain electrode; 6, gate electrode. DETAILED DESCRIPTION

[0030] For ease of understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific implementation methods or embodiments, and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of related listed items, and the combinations include any two related listed items, any more related listed items, or all related listed items.

[0032] like Figure 1 As shown, it is a schematic structural diagram of a junction field effect transistor in one embodiment of the present invention, wherein the junction field effect transistor comprises a substrate 1, an N-type In2Se3 thin film layer 2 and a P-type SnSe thin film layer 3 which are stacked in sequence, wherein a source electrode 4 and a drain electrode 5 are provided on the surface of the N-type In2Se3 thin film layer 2 away from the substrate, a channel is formed between the source electrode 4 and the drain electrode 5, the P-type SnSe thin film layer 3 is provided in the channel and is isolated from the source electrode 4 and the drain electrode 5, and a gate electrode 6 is provided on the P-type SnSe thin film layer 3, wherein the thickness ratio of the N-type In2Se3 thin film layer 2 to the P-type SnSe thin film layer 3 is 1:1.5~1:2.

[0033] Specifically, the thickness ratio of the N-type In2Se3 thin film layer 2 to the P-type SnSe thin film layer 3 includes but is not limited to any point value among 1:1.5, 1:1.6, 1:1.7, 1:1.8, 1:1.9, 1:2 or a range value between any two of them.

[0034] In2Se3 is a two-dimensional layered ferroelectric material. As it is a III-VI semiconductor with a layered structure, it has good photoelectric response and excellent stability. At the same time, it has spontaneous in-plane and out-of-plane polarization effects and has a non-volatile memory function. The junction field effect transistor provided by the present invention adopts an N-type In2Se3 thin film layer and a P-type SnSe thin film layer of a specific thickness. On the one hand, the depletion region of the PN junction is close to one side of the N-type In2Se3 thin film layer, which realizes precise control of the channel conductance and prevents the asymmetry of the electric field during operation, thereby effectively improving the rectification characteristics, switching characteristics and electrical performance of the PN junction; on the other hand, the ferroelectric polarization characteristics and excellent conductivity of the In2Se3 channel of the junction field effect transistor are effectively realized, the demand for an external electric field is reduced, the power consumption of the junction field effect transistor is reduced, and the integration is improved. At the same time, the programmability, storage, low power consumption and synaptic characteristics of the junction field effect transistor are realized.

[0035] Therefore, the junction field effect transistor provided by the present invention not only has the advantages of high input impedance and low noise, but also has high integration, programmability and versatility, and has broad application prospects, especially in the fields of information perception and storage, programmable electronic devices and neuromorphic electronic devices.

[0036] In one embodiment, the thickness of the N-type In2Se3 thin film layer 2 is 30nm~50nm, which is beneficial to improve the symmetry of the PN junction area, and then to achieve precise control of the channel conductance, and further improve the rectification characteristics, switching characteristics and electrical performance of the PN junction; at the same time, it is beneficial to ensure the ferroelectric properties and conductive properties of the N-type In2Se3 thin film layer 2, further reduce the demand for external electric fields, reduce the power consumption of junction field effect transistors, and improve integration. In addition, it is beneficial to realize the programmability, storage, low power consumption and synaptic characteristics of junction field effect transistors.

[0037] It should be noted that the present invention has no special restrictions on the crystal form of the N-type In2Se3 thin film layer 2, such as α-In2Se3, β-In2Se3, γ-In2Se3, etc. In order to further improve the ferroelectric properties and conductive properties of the N-type In2Se3 thin film layer 2, the present invention preferably uses ferroelectric phase α-In2Se3.

[0038] In one embodiment, the thickness of the P-type SnSe thin film layer 3 is 50nm~100nm, which is beneficial to avoid excessive carrier concentration in the P-type SnSe thin film layer 3, reduce the metallic properties of the P-type SnSe thin film layer 3, and ensure its P-type semiconductor performance. At the same time, it is beneficial to improve the symmetry of the PN junction area, and further improve the rectification characteristics, switching characteristics and electrical performance of the PN junction.

[0039] Specifically, the included angle between the length direction of the N-type In2Se3 thin film layer 2 and the length direction of the P-type SnSe thin film layer 3 is a right angle.

[0040] It can be understood that the length of the channel is represented by the distance between the source electrode 4 and the drain electrode 5 , and the P-type SnSe thin film layer 3 is disposed between the source electrode 4 and the drain electrode 5 , and its width is smaller than the length of the channel.

[0041] In order to further increase the relative proportion of the PN junction depletion region in the channel length, reduce the off-state current, and improve the switching characteristics of the junction field effect transistor, the width of the P-type SnSe thin film layer accounts for more than 50% of the length of the channel, including but not limited to any point value among 50%, 52%, 55%, 60%, 65%, 70%, 80%, 85%, 90%, 95%, 98%, and 99%, or any range value between two of them.

[0042] In order to shorten the migration path of carriers, further enhance the ohmic contact formed by the source electrode 4, the drain electrode 5 and the channel, improve the performance of the junction field effect transistor, and reduce the process difficulty, the length of the channel between the source electrode 4 and the drain electrode 5 is preferably 1μm~2μm, and the length of the channel includes but is not limited to any point value among 1μm, 1.1μm, 1.2μm, 1.3μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm or a range value between any two of them.

[0043] It should be noted that the present invention has no special restrictions on the left and right positions of the source electrode 4 and the drain electrode 5 , and the positions of the source electrode 4 and the drain electrode 5 can be interchanged.

[0044] In one embodiment, the source electrode 4, the drain electrode 5 and the gate electrode 6 all include a first metal layer and a second metal layer that are stacked, the first metal layer is selected from at least one of chromium, titanium, platinum and nickel, and the second metal layer is selected from at least one of gold, silver, copper, platinum and palladium. The first metal layer is beneficial to improving the ohmic contact between the electrode and the N-type In2Se3 thin film layer 2 and the P-type SnSe thin film layer 3, and plays the role of an adhesion layer. At the same time, the second metal layer is beneficial to improving the anti-oxidation effect of the electrode.

[0045] It should be noted that the first metal layer in the source electrode and the drain electrode contacts the surface of the N-type In2Se3 thin film layer 2, and the second metal layer contacts the surface of the first metal layer away from the N-type In2Se3 thin film layer 2; the first metal layer in the gate electrode contacts the surface of the P-type SnSe thin film layer 3, and the second metal layer contacts the surface of the first metal layer away from the P-type SnSe thin film layer 3.

[0046] It can be understood that the types of the first metal layer in the source electrode 4, the drain electrode 5 and the gate electrode 6 can be the same or different; at the same time, the types of the second metal layer in the source electrode 4, the drain electrode 5 and the gate electrode 6 can be the same or different, and the present invention has no special restrictions on this.

[0047] Specifically, the thickness of the first metal layer is 3nm~20nm, and the thickness of the second metal layer is 30nm~80nm. The thickness of the first metal layer includes but is not limited to any point value among 3μm, 4μm, 5μm, 8μm, 10μm, 12μm, 15μm, 17μm, 19μm, 20μm or a range value between any two of them. The thickness of the second metal layer includes but is not limited to any point value among 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 70μm, 80μm or a range value between any two of them.

[0048] It can be understood that the thickness of the first metal layer in the source electrode 4, the drain electrode 5 and the gate electrode 6 can be the same or different; at the same time, the thickness of the second metal layer in the source electrode 4, the drain electrode 5 and the gate electrode 6 can be the same or different, and the present invention has no special restrictions on this.

[0049] In one embodiment, the substrate 1 is at least one selected from silicon, silicon dioxide, aluminum oxide (sapphire), glass, and polyethylene terephthalate (PET).

[0050] like Figure 1 As shown, it is a schematic diagram of the structure of a junction field effect transistor in one embodiment of the present invention, wherein the substrate 1 comprises a Si substrate 11 and a SiO2 substrate 12 which are stacked in sequence, and the SiO2 substrate 12 is adjacent to the Si substrate 11 and the N-type In2Se3 thin film layer 2 respectively.

[0051] The present invention has no special limitation on the stacking order of the Si substrate 11 and the SiO2 substrate 12. In another embodiment of the present invention, the Si substrate 11 is adjacent to the SiO2 substrate 12 and the N-type In2Se3 thin film layer 2, respectively.

[0052] It should be noted that the present invention has no special restrictions on the specific type, thickness, etc. of the substrate 1, and those skilled in the art can make selections based on actual needs.

[0053] The present invention also provides a method for preparing the junction field effect transistor as described above, comprising the following steps:

[0054] S1, transferring the N-type In2Se3 thin film obtained by mechanical stripping onto a substrate to form an N-type In2Se3 thin film layer;

[0055] S2, transferring the P-type SnSe thin film obtained by mechanical stripping onto the N-type In2Se3 thin film layer to form a P-type SnSe thin film layer;

[0056] S3. Depositing a source electrode and a drain electrode on the surface of the N-type In2Se3 thin film layer, so that the P-type SnSe thin film layer is arranged between the source electrode and the drain electrode and isolated from the source electrode and the drain electrode, and depositing a gate electrode on the P-type SnSe thin film layer to obtain the junction field effect transistor.

[0057] The above preparation method is conducive to simplifying the manufacturing process of the junction field effect transistor, reducing the production cost, and improving the consistency and repeatability of the junction field effect transistor product, and is suitable for large-scale production of the junction field effect transistor.

[0058] Before step S1, the substrate is cleaned to ensure that the surface of the substrate is smooth and free of contamination. The cleaning agent used in the present invention is a commonly used solvent in the art, and the present invention has no special restrictions on this, such as acetone, isopropanol and deionized water.

[0059] In step S1 and step S2, the N-type In2Se3 film obtained by mechanical stripping is transferred to the substrate, and the P-type SnSe film obtained by mechanical stripping is transferred to the N-type In2Se3 film. The mechanical stripping method used in the present invention is a conventional method in the art, and the present invention does not elaborate on this; the above transfer can be carried out by dry transfer or wet transfer, and the present invention has no special restrictions on this.

[0060] In step S3, a source electrode, a drain electrode and a gate electrode are deposited respectively. The deposition method of the present invention adopts the existing technology in the field, and the present invention has no special limitation on this, such as electron beam exposure technology and electron beam evaporation technology.

[0061] In one embodiment, when depositing the source electrode and the drain electrode, the deposition temperature is lower than the phase transition temperature of In2Se3, which is beneficial to prevent the phase transition of In2Se3 and improve the stability of the obtained junction field effect transistor. The deposition temperature is preferably less than 180°C.

[0062] It can be understood that in each heating step in the above-mentioned preparation method, such as the drying of the uniform coating and the heating of the deposited metal, the heating temperature is set to be lower than the phase transition temperature of In2Se3.

[0063] The present invention also provides an application of the junction field effect transistor as described above in an electronic device. The junction field effect transistor provided by the present invention not only has the advantages of high input impedance and low noise, but also has high integration, programmability and versatility, and has broad application prospects, especially in the fields of information perception and storage, programmable electronic devices and neuromorphic electronic devices.

[0064] Hereinafter, the junction field effect transistor and its preparation method and application will be further described through the following specific embodiments.

[0065] Example 1

[0066] The silicon substrate and the silicon dioxide substrate are cleaned with acetone, isopropanol and deionized water to ensure that the surface is smooth and free of pollution, and the silicon substrate and the silicon dioxide substrate are stacked; the N-type In2Se3 thin film is obtained by mechanical stripping and transferred to the silicon dioxide substrate; the P-type SnSe thin film is obtained by mechanical stripping and transferred to the N-type In2Se3 thin film layer, wherein the thickness of the N-type In2Se3 thin film layer is 40nm, the thickness of the P-type SnSe thin film layer is 60nm, and the width is 0.6μm.

[0067] The source electrode and the drain electrode are respectively plated on the two ends of the N-type In2Se3 thin film layer, and the gate electrode is plated on the P-type SnSe thin film layer by electron beam exposure and electron beam evaporation. The channel length formed by the source electrode and the drain electrode is 1 μm, the deposition temperature is 100°C, the first metal layer deposited on the source electrode, the drain electrode and the gate electrode is 10 nm thick chromium, and the second metal layer is 50 nm thick gold, to obtain a junction field effect transistor.

[0068] Example 2

[0069] The silicon substrate and the silicon dioxide substrate are cleaned with acetone, isopropanol and deionized water to ensure that the surface is smooth and free of pollution, and the silicon substrate and the silicon dioxide substrate are stacked; the N-type In2Se3 thin film is obtained by mechanical stripping and transferred to the silicon dioxide substrate, and the P-type SnSe thin film is obtained by mechanical stripping and transferred to the N-type In2Se3 thin film. The thickness of the N-type In2Se3 thin film layer is 30nm, the thickness of the P-type SnSe thin film layer is 60nm, and the width is 0.8μm.

[0070] The source electrode and the drain electrode are respectively plated on the two ends of the N-type In2Se3 thin film layer, and the gate electrode is plated on the P-type SnSe thin film layer by electron beam exposure and electron beam evaporation. The channel length formed by the source electrode and the drain electrode is 1 μm, the deposition temperature is 120°C, the first metal layer deposited on the source electrode, the drain electrode and the gate electrode is 3 nm thick titanium, and the second metal layer is 40 nm thick gold, to obtain a junction field effect transistor.

[0071] Example 3

[0072] The silicon substrate was cleaned with acetone, isopropanol and deionized water to ensure a smooth surface without contamination; an N-type In2Se3 thin film was obtained by mechanical stripping and transferred to a silicon substrate; a P-type SnSe thin film was obtained by mechanical stripping and transferred to an N-type In2Se3 thin film, wherein the thickness of the N-type In2Se3 thin film layer was 50 nm, the thickness of the P-type SnSe thin film layer was 90 nm, and the width was 0.6 μm.

[0073] The source electrode and the drain electrode are respectively plated on the two ends of the N-type In2Se3 thin film layer, and the gate electrode is plated on the P-type SnSe thin film layer by electron beam exposure and electron beam evaporation. The channel length formed by the source electrode and the drain electrode is 1.5μm, the deposition temperature is 100°C, the first metal layer deposited on the source electrode, the drain electrode and the gate electrode is 20nm thick chromium, and the second metal layer is 80nm thick copper, to obtain a junction field effect transistor.

[0074] Comparative Example 1

[0075] The difference between Comparative Example 1 and Example 1 is that the thickness of the N-type In2Se3 thin film layer is 20 nm, the thickness of the P-type SnSe thin film layer is 60 nm, and the width is 0.6 μm.

[0076] Comparative Example 2

[0077] The difference between Comparative Example 2 and Example 1 is that the thickness of the N-type In2Se3 thin film layer is 40 nm, the thickness of the P-type SnSe thin film layer is 120 nm, and the width is 0.6 μm.

[0078] Comparative Example 3

[0079] The difference between Comparative Example 3 and Example 1 is that N-type MoS2 is used instead of the N-type In2Se3 thin film layer, and the thickness of MoS2 is 20 nm.

[0080] The junction field effect transistors prepared in all the embodiments and comparative examples were subjected to performance tests, and the test indicators were transfer characteristics, output characteristics, resistive switching performance, long-range enhancement and suppression characteristics, and paired pulse facilitation performance.

[0081] All test results are shown in Table 1.

[0082] Table 1

[0083]

[0084] The transfer characteristic curve of Example 1 is as follows: Figure 2 As shown, it can be seen that the junction field effect transistor prepared in Example 1 has 106 The output characteristic curve of the junction field effect transistor prepared in Example 1 is as follows: Figure 3 and Figure 4 As shown, from Figure 3 It can be seen that the source and drain electrodes have good ohmic contact. Figure 4 The cut-off region, linear region and amplification region of a junction field effect transistor are shown, which has good transistor performance; Figure 5 The pulse voltage controlled resistive switching performance of the junction field effect transistor of Example 1 is shown, and it can be seen that the junction field effect transistor has excellent non-volatile characteristics; the long-range enhancement and suppression characteristics obtained in Example 1 are as follows Figure 6 As shown, it can be seen that it has neuromorphic characteristics; the double pulse facilitation characteristics of the junction field effect transistor prepared in Example 1 are shown Figure 7 As shown, it can be seen that it has synaptic characteristics.

[0085] In addition, according to the results in Table 1, the junction field effect transistor prepared in the embodiment of the present invention has excellent transfer performance, output performance, resistive switching performance, long-range enhancement and suppression performance, and paired pulse facilitation performance, which are significantly better than the junction field effect transistor prepared in the comparative example.

[0086] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A junction field effect transistor, characterized in that: The junction field effect transistor includes a substrate, an N-type In2Se3 thin film layer and a P-type SnSe thin film layer which are stacked in sequence, wherein a source electrode and a drain electrode are provided on a surface of the N-type In2Se3 thin film layer away from the substrate, a channel is formed between the source electrode and the drain electrode, the P-type SnSe thin film layer is provided in the channel and is isolated from the source electrode and the drain electrode, and a gate electrode is provided on the P-type SnSe thin film layer, wherein a thickness ratio of the N-type In2Se3 thin film layer to the P-type SnSe thin film layer is 1:1.5~1:

2.

2. The junction field effect transistor according to claim 1, characterized in that: The thickness of the N-type In2Se3 thin film layer is 30nm~50nm.

3. The junction field effect transistor according to claim 1, characterized in that: The thickness of the P-type SnSe thin film layer is 50nm-100nm.

4. The junction field effect transistor according to claim 1, characterized in that: The width of the P-type SnSe thin film layer accounts for more than 50% of the length of the channel.

5. The junction field effect transistor according to claim 1 or claim 4, characterized in that: The length of the channel is 1 μm to 2 μm.

6. The junction field effect transistor according to claim 1, characterized in that: The source electrode, the drain electrode and the gate electrode each include a first metal layer and a second metal layer stacked in layers, the first metal layer is selected from at least one of chromium, titanium, platinum and nickel, and the second metal layer is selected from at least one of gold, silver, copper, platinum and palladium; And / or, the substrate is selected from at least one of silicon, silicon dioxide, aluminum oxide, glass and polyethylene terephthalate.

7. The junction field effect transistor according to claim 6, characterized in that: The thickness of the first metal layer is 3nm-20nm, and the thickness of the second metal layer is 30nm-80nm.

8. A method for preparing a junction field effect transistor according to any one of claims 1 to 7, characterized in that: The steps include: The N-type In2Se3 thin film obtained by mechanical stripping is transferred to a substrate to form an N-type In2Se3 thin film layer; Transferring the P-type SnSe thin film obtained by mechanical stripping onto the N-type In2Se3 thin film layer to form a P-type SnSe thin film layer; A source electrode and a drain electrode are deposited on the surface of the N-type In2Se3 thin film layer, so that the P-type SnSe thin film layer is arranged between the source electrode and the drain electrode and isolated from the source electrode and the drain electrode, and a gate electrode is deposited on the P-type SnSe thin film layer to obtain the junction field effect transistor.

9. The method for preparing a junction field effect transistor according to claim 8, characterized in that: When depositing the source electrode and the drain electrode, the temperature is less than 180°C.

10. Use of the junction field effect transistor according to any one of claims 1 to 7 in an electronic device.

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