An array signal processing device and method for adaptive matrix decomposition of array elements

Abstract

The present invention relates to the fields of communication anti-interference baseband signal processing and navigation receiver anti-interference baseband signal processing, and in particular to an array signal processing device and method for adaptive matrix decomposition of array elements. The present invention can adaptively identify effective array element channels and count the number of effective array elements; adaptively configure matrix decomposition operation units to reduce power consumption and ensure normal operation results; adaptively balance delays, so that changes in array elements do not affect the matrix decomposition operation time, and the total delay of system operations remains unchanged. Therefore, the application scenarios of the present invention are more universal and the application robustness is higher. The present invention can be used for any multi-element signal processing equipment based on matrix decomposition, improve the availability of various communication and navigation equipment in complex electronic countermeasure environments, and has a high use value.

Description

Technical Field

[0001] The invention relates to the field of communication anti-interference baseband signal processing and navigation receiver anti-interference baseband signal processing, and in particular to an array signal processing device and method for array element adaptive matrix decomposition. Background Art

[0002] In real complex application environments, especially in hostile and battlefield application environments, electronic interference and confrontation are everywhere. Among them, electronic interference to navigation equipment or communication equipment includes but is not limited to narrowband suppression interference, broadband suppression interference, deception interference, pulse interference and flicker interference. The general solution is to use array antennas, collect data in parallel on multiple channels, and perform array signal processing to achieve anti-interference effect.

[0003] Array signal processing algorithms cannot do without the calculation of data matrices. QR decomposition, as a matrix decomposition method widely used in engineering, can decompose the matrix into the product of the orthogonal matrix Q and the upper triangular matrix R, which facilitates the engineering implementation of matrix calculations. As a key technology in array signal processing, QR decomposition is usually implemented using a systolic array, but its implementation architecture seriously affects the operating efficiency of the device in a real environment when applied in engineering.

[0004] The array antenna is composed of multiple antennas, and undergoes multiple levels of processing from the antenna to the digital front end. If the channel corresponding to a certain antenna is abnormal, the data on that channel cannot be used.

[0005] At present, the implementation method of multi-element signal processing based on matrix decomposition is mainly a fixed array element implementation method, that is, the array element channel corresponds to the matrix decomposition operation unit one by one; this method has obvious defects:

[0006] 1) When the system is working abnormally, it is necessary to manually confirm the validity of the array channel, which is a cumbersome and inefficient process;

[0007] 2) When the array element channel is abnormal, whether it is the antenna array or the internal array element channel, the calculation result is abnormal due to the one-to-one correspondence between the array element channel and the matrix decomposition operation unit, and the expected effect cannot be achieved;

[0008] 3) When the number of array elements changes, the matrix decomposition operation time will also change, resulting in different total system delays, affecting the debugging and application of back-end modules. In this regard, in order to further improve the availability of navigation and communication equipment in electronic countermeasure environments, the adaptive matrix decomposition architecture and array signal processing engine of the present invention are proposed. Summary of the invention

[0009] In order to solve one or several problems in the prior art, especially for the existing multi-element matrix decomposition architecture, when the array element channel is damaged, the channel mapping operation unit is fixed, resulting in abnormal operation results; and since the signal processing timing is fixed, the change in the number of array elements causes the total delay of the system operation to change, affecting the back-end signal processing.

[0010] In order to achieve the above-mentioned purpose of the invention, the present invention proposes to provide an array signal processing device and method of adaptive matrix decomposition with adaptive judgment of array element validity, adaptive configuration of matrix decomposition array elements, and adaptive adjustment of matrix decomposition processing delay.

[0011] Specifically, it is an array signal processing device for array element adaptive matrix decomposition, which includes the following units:

[0012] Data buffer unit: receives real-time sampling data of M array elements;

[0013] Adaptive array element integrity detection unit: sequentially process the data of the M array element data frames, perform three-dimensional judgment through energy detection, spectrum analysis and sampling point distribution probability statistics, and determine the validity of the real-time sampling data input by the M array elements; sequentially select and process the data of all the M array elements to complete the validity test of the M array elements; obtain information on valid array elements and the number of valid array elements N (N<=M); array element reloadable matrix decomposition unit: adopt a systolic array structure to realize array element matrix decomposition, and adaptively configure the operation units required for matrix decomposition according to the array element state logic circuit during operation; delay equalization unit: adaptively select delay parameters according to the valid array element number N output by the adaptive array element integrity detection unit, and transmit the delay parameters to the last operation unit under the longest operation path after matrix decomposition reload in combination with the configuration of the array element reloadable matrix decomposition unit to adjust the operation delay; wherein, M is a natural number greater than 1, and N is a natural number.

[0014] Furthermore, the matrix decomposition of the array element reloadable matrix decomposition unit is implemented using a systolic array structure. The M array elements have a total of M boundary units and (1+2+…+(M-1)) internal units. During the working process, the operation units required for matrix decomposition are adaptively configured according to the array element state logic circuit, and there may be two working modes according to the situation of the array element:

[0015] Working mode 1: When the M array elements belong to the same array element group, the array element state logic circuit adaptively configures the operation units required for matrix decomposition of the N valid array elements, where the N valid array elements include N boundary units and (1+2+…+(N-1)) internal units, and turns off idle operation units; according to the array element validity, the data of the valid array elements are rearranged and input in parallel into the configured operation units for matrix decomposition.

[0016] Working mode 2: When the M array elements are applied in groups, there are K array element groups in total, namely M1, M2, …, MK, where M1 + M2 + … + MK = M; after the array element validity detection, the numbers of valid array elements of the K array element groups are N1, N2, …, NK ((N1 + N2 + … + NK) <= M) respectively. The array element status logic circuit adaptively configures the arithmetic units required for matrix decomposition of the K array element groups. The sampling data of the K array element groups are input independently and in parallel for parallel matrix decomposition operation, and the idle arithmetic units are turned off; according to the validity of the array elements of the K array element groups, the K array element groups rearrange the data of the valid array elements, and the data of the K array element groups are input in parallel to the configured arithmetic units of the K array element groups for their respective matrix decomposition operations; where K is a natural number greater than 1.

[0017] Further, in the adaptive array element integrity detection unit: One array element's data is sequentially selected from the real-time sampling data of the M array elements, and at the same time, energy detection, spectrum analysis, and sampling point step-by-step probability statistics are performed. According to the operation results of the above three processing methods, it is judged whether the input data of the selected one array element is a constant, noise, or interference signal; after the operations of the M array elements are sequentially completed, the operation results of the input data of all the M array elements are summarized to judge whether the device is working in a non-interference environment or an interference environment, and the validity and the number of valid array elements N of each of the M array elements are obtained.

[0018] Further, according to the array element validity obtained by the adaptive array element integrity detection unit, channel data mapping is performed; in the real-time sampling data of the M array elements, the data of the invalid channels are removed, and the data of the valid channels are sequentially and parallelly mapped to the first-level arithmetic units of matrix decomposition.

[0019] When the M array elements belong to the same array element group, the number of valid array elements N obtained in the adaptive array element integrity detection unit satisfies N < M, and 2 When N > M, from the arithmetic units of matrix decomposition of the M array elements, the arithmetic units required for matrix decomposition of the N valid array elements are adaptively configured, including N boundary units and (1 + 2 + … + (N - 1)) internal units, and all the remaining unused arithmetic units are turned off. For the matrix decomposition operation of the N valid array elements, the real-time sampling data is sequentially input to the first-level arithmetic units of matrix decomposition.

[0020] When the M array elements are split into K array element groups for application, the number of effective array elements (N1+N2+…+NK) obtained in the adaptive array element integrity detection unit is less than or equal to M, and the operation units required for the matrix decomposition of different array elements of the K array element groups are adaptively configured from the operation units of the matrix decomposition of the M array elements, the sampling data of each of the K array element groups are independently input in parallel, the matrix decomposition of each of the K array element groups is parallelly calculated, and the remaining unused operation units are all closed, the matrix decomposition of the effective number NK of each of the K array element groups is parallelly calculated, and the data of the effective channels of each of the K array element groups are TN1, TN2, …, TNK respectively, and each group of real-time sampling data needs to be input into the first-level operation unit of the corresponding matrix decomposition operation unit of the K array element groups.

[0021] Furthermore, according to the effective array element number N obtained by the adaptive array element integrity detection unit, a matrix decomposition calculation delay parameter corresponding to the effective array element number N is adaptively obtained; according to the position of the operation unit configured in the array element overloadable matrix decomposition unit, a delay processing is performed on the completion signal of the configured operation unit, which is consistent with the matrix decomposition operation time in a normal state, so as to achieve the unchanged total processing delay of the system.

[0022] Furthermore, the array signal processing device is an engine architecture or an accelerator.

[0023] In order to achieve the above-mentioned object of the invention, the present invention also proposes an array signal processing method for array element adaptive matrix decomposition, which adopts the above-mentioned array signal processing device for array element adaptive matrix decomposition, and comprises the following steps:

[0024] S1: receiving real-time sampling data of M array elements through a data buffer unit;

[0025] S2: using the adaptive array element integrity detection unit to process the data of the M array element data frames in sequence, and determine the validity of the M array element input data by means of energy detection, spectrum analysis and sampling point distribution probability statistics; selecting and processing all array element data in sequence to complete the validity check of the M array elements; obtaining information of valid array elements and the number of valid array elements N (N<=M);

[0026] S3: The array element reloadable matrix decomposition unit adopts a systolic array structure to realize matrix decomposition. The M array elements have a total of M boundary units and (1+2+…+(M-1)) internal units. During the working process, the operation units required for matrix decomposition are adaptively configured according to the array element state logic circuit;

[0027] S4: According to the effective array element number N output by S2, the delay equalization unit adaptively selects the delay parameter, and transmits the delay parameter to the last operation unit under the longest operation path after the matrix decomposition is overloaded in combination with the configuration of the array element overloadable matrix decomposition unit.

[0028] Compared with the prior art, the present invention also has the advantages of:

[0029] The array signal processing device and method for adaptive matrix decomposition of array elements of the present invention can adaptively identify effective array element channels and count the number of effective array elements; adaptively configure matrix decomposition operation units to reduce power consumption and ensure normal operation results; adaptive delay equalization, array element changes do not affect the matrix decomposition operation time, and the total system operation delay remains unchanged. Therefore, the application scenarios of the present invention are more universal and the application robustness is higher. The present invention can be used for any multi-element signal processing equipment based on matrix decomposition, improve the availability of various communication and navigation equipment in complex electronic countermeasure environments, and has a high use value. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the architecture of the present invention;

[0031] Figure 2 It is a schematic diagram of the reconfiguration of array elements in a matrix decomposition operation of a single array element group;

[0032] Figure 3 It is a schematic diagram of the reconfiguration of array elements in the matrix decomposition operation of two array element groups;

[0033] Figure 4 It is a diagram showing an embodiment of the application of the present invention in a certain type of navigation anti-interference equipment. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0035] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Embodiment 1: Figure 1-2 As shown, an array signal processing engine architecture for array element adaptive matrix decomposition includes the following units:

[0037] Data buffer unit; receives real-time sampling data of M array elements, and continuously pipelines the data into the matrix decomposition engine in frames, with each frame length being T;

[0038] Adaptive array element integrity detection unit; sequentially processes the data of M array element data frames, and determines the validity of the array element input data through energy detection, spectrum analysis and sampling point distribution probability statistics through multi-dimensional judgment; sequentially selects and processes all array element data to complete the validity test of M array elements; obtains information on valid array elements and the number of valid array elements N (N<=M);

[0039] The array element can overload the matrix decomposition unit; the matrix decomposition is implemented using a systolic array structure. M array elements have a total of M boundary units and (1+2+…+(M-1)) internal units. During the working process, the operation units required for matrix decomposition are adaptively configured according to the array element state logic circuit;

[0040] When the M array elements belong to the same array element group, the logic circuit adaptively configures the operation units required for the matrix decomposition of the N array elements, including N boundary units and (1+2+…+(N-1)) internal units, and closes the idle operation units; according to the effectiveness of the array elements, the data of the effective array elements are rearranged and input in parallel into the configured operation units for matrix decomposition, such as Figure 2 As shown;

[0041] Delay equalization unit: According to the number of valid array elements output by the adaptive array element integrity detection unit, the delay parameter is adaptively selected, and combined with the configuration of the array element reloadable matrix decomposition unit, the delay parameter is transmitted to the last operation unit under the longest operation path after the matrix decomposition is reloaded, and the operation delay is adjusted to ensure that the total delay of the matrix decomposition operation is not affected by the change of the array element, and the robustness of the data processing delay of the entire system is better;

[0042] In a specific application example, the data cache unit inputs the real-time sampling data of M array elements, logically divides the data into segments according to the duration, and the three array element effectiveness analysis methods of energy detection, spectrum analysis and sampling point distribution probability statistics need to operate on the same data in parallel, and then make multi-dimensional judgments on the effectiveness of the array elements, and count the number of effective array elements; after the operation of the current data segment is completed, the operation of the next data segment is immediately carried out, and the cycle continues;

[0043] In a specific application example, the array element can overload the matrix decomposition unit, skip invalid array element channels according to the effective state of the array element channels, rearrange the effective array element channels in sequence, and input the data in parallel to the matrix decomposition operation unit; according to the effective number N of array element channels, adaptively configure the operation units required for the N-element matrix decomposition, including N boundary units and (1+2+…+(N-1)) internal units, and close the unused operation units;

[0044] In a specific application example, after obtaining the effective number of array elements, the delay equalization unit selects a delay parameter according to the number of array elements, and adjusts the delay of the longest operation path output in the matrix decomposition to be consistent with the output delay of the matrix decomposition operation when there are M array elements.

[0045] Embodiment 2: Figure 1-3 As shown, an array signal processing engine architecture for array element adaptive matrix decomposition includes the following units:

[0046] Data buffer unit; receives real-time sampling data of M array elements, and continuously pipelines the data into the matrix decomposition engine in frames, with each frame length being T;

[0047] Adaptive array element integrity detection unit; sequentially processes the data of M array element data frames, and determines the validity of the array element input data through energy detection, spectrum analysis and sampling point distribution probability statistics through multi-dimensional judgment; sequentially selects and processes all array element data to complete the validity test of M array elements; obtains information on valid array elements and the number of valid array elements N (N<=M);

[0048] The array element can overload the matrix decomposition unit; the matrix decomposition is implemented using a systolic array structure. M array elements have a total of M boundary units and (1+2+…+(M-1)) internal units. During the working process, the operation units required for matrix decomposition are adaptively configured according to the array element state logic circuit;

[0049] When M array elements are grouped for application, it is assumed that there are K array element groups, namely M1, M2, ..., MK, where M1+M2+...+MK=M; if after the array element validity detection, the number of valid array elements in each array element group is N1, N2, ..., NK ((N1+N2+...+NK)<=M), the logic circuit adaptively configures the operation units required for matrix decomposition of the K array element groups, the sampling data of each array element group is independently input in parallel, the matrix decomposition is performed in parallel, and the idle operation units are turned off; according to the validity of the array elements of each array element group, the data of the valid array elements of each array element group are rearranged, and the data of each array element group are input in parallel to the operation units configured for each array element group, and their respective matrix decomposition operations are performed; Figure 3 The matrix decomposition operation of two array elements under M array elements is shown in the figure;

[0050] Delay equalization unit: According to the number of valid array elements output by the adaptive array element integrity detection unit, the delay parameter is adaptively selected, and combined with the configuration of the array element reloadable matrix decomposition unit, the delay parameter is transmitted to the last operation unit under the longest operation path after the matrix decomposition is reloaded, and the operation delay is adjusted to ensure that the total delay of the matrix decomposition operation is not affected by the change of the array element, and the robustness of the data processing delay of the entire system is better;

[0051] In a specific application example, the data cache unit inputs the real-time sampling data of M array elements, logically divides the data into segments according to the duration, and the three array element effectiveness analysis methods of energy detection, spectrum analysis and sampling point distribution probability statistics need to operate on the same data in parallel, and then make multi-dimensional judgments on the effectiveness of the array elements, and count the number of effective array elements; after the operation of the current data segment is completed, the operation of the next data segment is immediately carried out, and the cycle continues;

[0052] In a specific application example, the array element can overload the matrix decomposition unit, skip invalid array element channels according to the effective state of the array element channels, rearrange the effective array element channels in sequence, and input the data in parallel to the matrix decomposition operation unit; according to the effective number N of array element channels, adaptively configure the operation units required for the N-element matrix decomposition, including N boundary units and (1+2+…+(N-1)) internal units, and close the unused operation units;

[0053] In a specific application example, after obtaining the effective number of array elements, the delay equalization unit selects a delay parameter according to the number of array elements, and adjusts the delay of the longest operation path output in the matrix decomposition to be consistent with the output delay of the matrix decomposition operation when there are M array elements.

[0054] Embodiment 3: Figure 3-4 As shown, it is an application example of the present invention on a certain type of navigation anti-interference equipment:

[0055] (1) This model system is designed with 32 array elements. When working in single array element group working mode, it supports matrix decomposition operations of input data of no more than 32 array element channels. In dual array element group working mode, each array element group supports matrix decomposition operations of input data of no more than 16 array element channels.

[0056] (2) After powering on, the host computer first configures the working parameters, such as the array data energy detection threshold, spectrum analysis range, sampling point distribution probability statistical threshold, array element working mode, minimum number of working array elements in the array element group, data processing frame length, etc. After the configuration is completed, data caching and processing are started;

[0057] (3) The real-time data collected by the 32 array elements enters the data cache unit after being processed by the front-end module such as down-conversion and filtering, and then is processed in two ways: direct and cache. Direct processing directly outputs the input data to the adaptive array element integrity detection unit; cache processing stores all array data in parallel in the cache area. When the cache data depth meets the data processing frame length, the data is read from the cache area in parallel by frame and input into the array element reloadable matrix decomposition unit.

[0058] (4) The adaptive array element integrity detection unit performs validity detection on all array elements in parallel, logically extracts all array data in parallel according to the detection cycle, and each array element simultaneously executes the detection algorithm of energy detection, spectrum analysis and sampling point distribution probability statistics, and judges the results of the three algorithms to determine whether the array element is in an interference input or non-interference input state; after all array elements are detected, the device working environment is determined to be an interference environment or a non-interference environment based on the parameter configuration of the minimum number of working array elements and the input status of each array element, and then determines the validity of each channel, counts the number of valid channels, and sends the detection results to the array element reloadable matrix decomposition unit;

[0059] (5) The array element reloadable matrix decomposition unit maps the array element effective channels to the input of the matrix decomposition operation unit in sequence, and maps out row enables and column enables according to the effective number of array elements to turn on or off the operation unit; in the single array element group working mode, only the row enables and column enables of the first array element group can be used to control the switches of all operation units, and the input data only needs to be mapped to the first-level operation unit of the 32-array element matrix decomposition systolic array; in the dual array element group working mode, the input of the first array element group is mapped to the first-level operation unit of the systolic array, and the second array element group needs to use independent row enables and column enables to realize the input and enable control of the matrix decomposition operation unit, and the input data needs to be mapped to a row in the systolic array; Figure 3 As shown;

[0060] (6) In matrix decomposition operation based on systolic array structure, the array data only needs to be piped in parallel to the first-level operation unit; the input of the remaining operation units is the result of the boundary unit and the result of the previous level operation. While saving their own operation results, they are also output to the next level. The operation units at each level perform piped operations from top to bottom and from left to right. Figure 2 It can be seen that the longest data operation path is located on the far right of the systolic array. After the operation unit at the bottom of the path is completed, the matrix decomposition is completed and the data of all operation units can be output;

[0061] (7) When the number of array elements changes, the matrix decomposition unit reloads the array elements, and the longest path for data operation changes accordingly. In fact, when the number of array elements decreases, the reloaded operation units decrease synchronously, the operation path becomes shorter, and the matrix decomposition will be completed in advance;

[0062] (8) Under normal conditions, the longest path of matrix decomposition data operation (i.e., the operation path from top to bottom on the far right) is used as a reference. The number of clocks that the matrix decomposition is completed in advance for different array elements is calculated as the delay adjustment parameter. It should be noted that the reference paths in the two working modes are different, and the delay parameters are also different. According to the number of effective channels obtained by the array element integrity detection unit, the delay adjustment parameter is selected to delay the completion flag of the operation unit at the lower right end of the matrix decomposition pulse array after the array element is overloaded, so that the matrix decomposition operation time is not affected by the change of the array element. The total delay of the system output is guaranteed to be unchanged, which is convenient for zero-value debugging of the system, reduces debugging time and debugging risks, and improves system work efficiency.

[0063] The above are preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be based on the attached claims.

[0064] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0065] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, device, article or method including the element.

Claims

1. An array signal processing device for array element adaptive matrix decomposition, characterized in that: include: Data buffer unit: receives real-time sampling data of M array elements; An adaptive array element integrity detection unit: sequentially processes the data frames of the real-time sampling data of the M array elements, performs three-dimensional judgment by energy detection, spectrum analysis and sampling point distribution probability statistics, and determines the validity of the real-time sampling data of the M array elements; Selecting and processing the real-time sampling data of all the M array elements in sequence to complete the validity test of all the M array elements; Obtain information of N valid array elements, where N<=M; Array element reloadable matrix decomposition unit: adopts systolic array structure to realize array element matrix decomposition, and the operation units required for matrix decomposition are adaptively configured according to the array element state logic circuit during the working process; Delay equalization unit: adaptively selects delay parameters according to the N valid array elements output by the adaptive array element integrity detection unit, transmits the delay parameters to the last operation unit under the longest operation path after matrix decomposition reloading in combination with the configuration of the array element reloadable matrix decomposition unit, and adjusts the operation delay; Wherein, M is a natural number greater than 1, and N is a natural number.

2. The array signal processing device for element adaptive matrix decomposition according to claim 1, characterized in that: The M array elements have a total of M boundary units and 1+2+…+ (M-1) internal units, and the M array elements belong to the same array element group. The array element state logic circuit adaptively configures the operation units required for matrix decomposition of the N effective array elements, and the N effective array elements include N boundary units and 1+2+…+ (N-1) internal units, and closes idle operation units; according to the effectiveness of the array elements, the data of the effective array elements are rearranged and input in parallel into the configured operation units for matrix decomposition.

3. The array signal processing device for element adaptive matrix decomposition according to claim 1, characterized in that: The M array elements have a total of M boundary units and 1+2+…+(M-1) internal units. The M array elements are applied in groups, and there are a total of K array element groups, which are M1, M2, …, MK, respectively, where M1+M2+…+MK=M; after the array element validity detection, the number of valid array elements in each of the K array element groups is N1, N2, …, NK, respectively, where (N1+N2+…+NK)<=M, the array element state logic circuit adaptively configures the operation units required for matrix decomposition of each of the K array element groups, the sampling data of each of the K array element groups are independently input in parallel, the matrix decomposition is parallelly calculated, and the idle operation units are closed; according to the array element validity of each of the K array element groups, the data of the valid array elements of each of the K array element groups are rearranged, and the data of each of the K array element groups are input in parallel to the operation units configured by each of the K array element groups, and their respective matrix decomposition operations are performed; wherein K is a natural number greater than 1.

4. The array signal processing device for adaptive matrix decomposition of array elements according to any one of claims 1 to 3, wherein in the adaptive array element integrity detection unit: data of one array element is selected from the real-time sampling data of the M array elements in sequence, and energy detection, spectrum analysis and sampling point step-by-step probability statistics are simultaneously performed, and according to the calculation results of the above three processing methods, the data of the selected array element is judged to be a constant, noise or interference signal; after the calculation of the M array elements is completed in sequence, the calculation results of all the M array data are summarized to judge whether the device is working in an interference-free environment or an interference environment, and the validity of each of the M array elements and the number of effective array elements N are obtained.

5. According to the array signal processing device for array element adaptive matrix decomposition according to claim 4, channel data mapping is performed according to the array element validity obtained by the adaptive array element integrity detection unit; in the real-time sampling data of the M array elements, the data of invalid channels are removed, and the data of valid channels are sequentially and parallelly mapped to the first-level operation unit of the matrix decomposition.

6. The array signal processing device for array element adaptive matrix decomposition according to claim 5, wherein in the array element reloadable matrix decomposition unit: The M array elements belong to the same array element group, and the number of valid array elements N obtained in the adaptive array element integrity detection unit satisfies N < M, and 2 When N > M, from the operation units of the matrix decomposition of the M array elements, the operation units required for the matrix decomposition of the N valid array elements are adaptively configured, including N boundary units and 1 + 2 + … + (N - 1) internal units, and all the remaining unused operation units are turned off. For the matrix decomposition operation of the N valid array elements, the real-time sampling data is sequentially input into the first-stage operation unit of the matrix decomposition.

7. The array signal processing device for array element adaptive matrix decomposition according to claim 5, wherein in the array element reloadable matrix decomposition unit: The M array elements are split into K array element groups for application, the effective array element number (N1+N2+…+NK) obtained in the adaptive array element integrity detection unit is less than or equal to M, and the operation units required for the matrix decomposition of different array elements of each of the K array element groups are adaptively configured from the operation units of the matrix decomposition of the M array elements, the sampling data of each of the K array element groups are independently input in parallel, the matrix decomposition of each of the K array element groups is parallelly calculated, and the remaining unused operation units are all closed, the matrix decomposition of the effective array element number NK of each of the K array element groups is parallelly calculated, and the data of the effective channels of each of the K array element groups are TN1, TN2, …, TNK respectively, and each group of real-time sampling data needs to be input into the first-level operation unit of the corresponding matrix decomposition operation unit of the K array element groups.

8. According to the array signal processing device for array element adaptive matrix decomposition of claim 5, according to the effective array element number N obtained by the adaptive array element integrity detection unit, the matrix decomposition calculation delay parameter corresponding to the effective array element number N is adaptively obtained; according to the position of the operation unit configured in the array element reloadable matrix decomposition unit, the completion signal of the configured operation unit is delayed to be consistent with the matrix decomposition operation time in a normal state, so as to achieve the unchanged total processing delay of the system. 9 . The array signal processing device for element adaptive matrix decomposition according to claim 5 , wherein the array signal processing device is an engine architecture or an accelerator.

10. An array signal processing method for array element adaptive matrix decomposition, which adopts the array signal processing device for array element adaptive matrix decomposition according to any one of claims 1 to 9, characterized in that: The following steps are involved: S1: receiving real-time sampling data of M array elements through a data buffer unit; S2: using the adaptive array element integrity detection unit to sequentially process the data frames of the real-time sampling data of the M array elements, and perform three-dimensional judgment by energy detection, spectrum analysis and sampling point distribution probability statistics to determine the validity of the real-time sampling data of the M array elements; Selecting and processing the data of all array elements in turn to complete the validity check of the M array elements; Obtain information of N valid array elements, where N<=M; S3: The array element reloadable matrix decomposition unit adopts a systolic array structure to realize matrix decomposition. The M array elements have a total of M boundary units and 1+2+…+(M-1) internal units. During the working process, the operation units required for matrix decomposition are adaptively configured according to the array element state logic circuit; S4: According to the N valid array elements output by S2, the delay equalization unit adaptively selects the delay parameter, and transmits the delay parameter to the last operation unit under the longest operation path after the matrix decomposition is overloaded in combination with the configuration of the array element overloadable matrix decomposition unit.

Images