A method, device, equipment and medium for protecting power integrity of computing unit

Abstract

The present invention discloses a method, device, equipment and medium for protecting the power integrity of a computing unit. The method is executed by a computing unit in a chip, including: performing local risk detection on a target computing unit through a local risk check subunit, and when it is determined that a local risk exists in the target computing unit, sending a local risk signal to a subsystem risk check subunit of each computing unit in the subsystem; when receiving a local risk signal from a target computing unit through a subsystem risk check subunit, updating a past risk counter and a synchronous risk counter respectively; performing corresponding protection operations according to the local risk signal and / or counter update result through a currently enabled local risk protection subunit and / or subsystem risk protection subunit. The above technical solution can avoid the current surge phenomenon of the chip in a short period of time and ensure the power integrity of the computing unit.

Description

Technical Field

[0001] The present invention relates to the field of chip protection technology, and in particular to a method, device, equipment and medium for protecting power integrity of a computing unit. Background Art

[0002] With the continuous iteration of artificial intelligence technology applications, developers' demand for the computing power of AI (Artificial Intelligence) chips is gradually increasing. Currently, increasing the parallel computing units in AI chips is an effective way to increase computing power.

[0003] However, when the number of computing units increases linearly, the current of the AI ​​chip will also increase linearly. When the AI ​​chip generates a current surge in a short period of time, it will destroy the power integrity of the computing unit, causing the computing frequency of the computing unit to decrease, thereby reducing or even offsetting the computing power improvement brought about by increasing the number of parallel computing units. Summary of the invention

[0004] The present invention provides a method, device, equipment and medium for protecting the power integrity of a computing unit, which can avoid the current surge phenomenon of a chip in a short period of time and ensure the power integrity of the computing unit.

[0005] According to one aspect of the present invention, a method for protecting power integrity of a computing unit is provided, which is executed by a computing unit in a chip and includes:

[0006] By means of the local risk checking subunit, a local risk detection is performed on the target computing unit according to the high power consumption instruction information of the target computing unit, and when it is determined that the target computing unit has a local risk, a local risk signal is sent to the subsystem risk checking subunit of each computing unit in the subsystem respectively;

[0007] When receiving the local risk signal of the target computing unit, the subsystem risk checking subunit updates the past risk counter and the synchronous risk counter according to the local risk signals sent by the remaining computing units in the subsystem;

[0008] The corresponding protection operation is performed according to the local risk signal and / or the counter update result through the currently enabled local risk protection subunit and / or subsystem risk protection subunit.

[0009] According to another aspect of the present invention, a computing unit power integrity protection device is provided, which is executed by a computing unit in a chip and includes:

[0010] A local risk checking module is used to perform local risk detection on a target computing unit according to the high power consumption instruction information of the target computing unit through a local risk checking subunit, and when it is determined that the target computing unit has a local risk, send a local risk signal to the subsystem risk checking subunit of each computing unit in the subsystem;

[0011] The subsystem risk checking module is used to update the past risk counter and the synchronous risk counter respectively according to the local risk signals sent by the remaining computing units in the subsystem through the subsystem risk checking subunit when receiving the local risk signal of the target computing unit;

[0012] The power integrity protection module is used to perform corresponding protection operations according to the local risk signal and / or the counter update result through the currently turned on local risk protection subunit and / or subsystem risk protection subunit.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the method for protecting the power integrity of a computing unit described in any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method for protecting the power integrity of a computing unit described in any embodiment of the present invention when executed.

[0018] The technical solution of the embodiment of the present invention utilizes a local risk checking subunit. When a local risk is detected in a target computing unit, a local risk signal is sent to the subsystem risk checking subunit of each computing unit in the subsystem. When the subsystem risk checking subunit receives the local risk signal of the target computing unit, the past risk counter and the synchronous risk counter are updated according to the local risk signals sent by the remaining computing units in the subsystem. The currently enabled local risk protection subunit and / or subsystem risk protection subunit are used to perform corresponding protection operations according to the local risk signal and / or the counter update result. The high-power consumption instruction situation of each computing unit in the chip can be monitored. When there is a risk of current surge due to too many high-power consumption instructions, low-power consumption instructions are inserted at appropriate locations. This can ensure the power integrity while maximizing the utilization of the computing units. Moreover, the computing units and subsystems can be protected separately or jointly, which is suitable for complex and changeable chip usage scenarios.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a flow chart of a method for protecting power integrity of a computing unit provided according to Embodiment 1 of the present invention;

[0022] Figure 2 is a schematic diagram of a subunit structure in a computing unit provided according to an embodiment of the present invention;

[0023] Figure 3 is a flow chart of another method for protecting power integrity of a computing unit provided according to Embodiment 2 of the present invention;

[0024] Figure 4 is a schematic diagram of the structure of a computing unit power integrity protection device provided according to Embodiment 3 of the present invention;

[0025] Figure 5 It is a structural schematic diagram of an electronic device that implements the method for protecting the power integrity of a computing unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] Embodiment 1

[0029] Figure 1 This is a flow chart of a method for protecting the power integrity of a computing unit provided in the first embodiment of the present invention. This embodiment is applicable to the case of protecting the power integrity of a computing unit in a chip. The method can be executed by a computing unit power integrity protection device. The computing unit power integrity protection device can be implemented in the form of hardware and / or software and can generally be configured in the computing unit of the chip. Figure 1 As shown, the method includes:

[0030] S110. Perform local risk detection on the target computing unit according to the high power consumption instruction information of the target computing unit through the local risk detection subunit, and when it is determined that the target computing unit has a local risk, send the local risk signal to the subsystem risk detection subunit of each computing unit in the subsystem.

[0031] Optionally, the computing unit is the part of the chip used to perform mathematical operations and logical operations. The computing unit can be used to implement specific functions of the chip. In the prior art, a large number of parallel computing units can be set in the chip to improve the computing power of the chip. As the number of parallel units increases and the number of high-power instructions in each parallel unit increases, the current of the power supply may increase. When the current is greater than a certain value, the power integrity may be reduced.

[0032] Optionally, a chip may include multiple computing units for parallel computing, and multiple computing units may form a subsystem. For example, when 60 computing units are configured in the chip and every 6 computing units form a subsystem, the chip can be divided into 10 subsystems.

[0033] Optionally, in an embodiment of the present invention, the subsystem includes multiple computing units, and each computing unit is configured with a local risk check subunit, a subsystem risk check subunit, a local risk protection subunit and a subsystem risk protection subunit for performing joint protection operations on the computing unit.

[0034] Optionally, each computing unit in the chip respectively executes the computing unit integrity protection method as described in the embodiment of the present invention. The target computing unit may refer to any computing unit in the chip, and each computing unit in the chip may execute the same computing unit integrity protection operation as described in the embodiment of the invention.

[0035] Optionally, in the local risk check subunit of the target computing unit, multiple high-power consumption instruction statistics windows can be configured, and the high-power consumption instruction statistics windows include a future high-power consumption instruction statistics window, a current high-power consumption instruction statistics window, a first past high-power consumption instruction statistics window, and a second past high-power consumption instruction statistics window.

[0036] Figure 2 FIG. 1 is a schematic diagram of a subunit structure in an optional computing unit. Figure 2 As shown, the solid line represents the subunit in the target computing unit, and the dotted line represents the subunit of other computing units in the same subsystem. Here, only two computing units in the subsystem are shown for explanation. In fact, a subsystem generally includes multiple computing units. Each computing unit in the subsystem can receive and execute instructions in the instruction emission sequence. After obtaining the instruction emission sequence of the computing unit, it can be sent to the local risk check subunit in the computing unit first, so as to determine whether the computing unit has a local risk when receiving the current instruction through the local risk check subunit.

[0037] Optionally, the local risk check subunit of the target computing unit can use the future high-power consumption instruction statistics window, the current high-power consumption instruction statistics window, the first past high-power consumption instruction statistics window and the second past high-power consumption instruction statistics window to respectively count the high-power consumption instructions in different time periods of the target computing unit and determine whether there is a local risk in the target computing unit based on the statistical results.

[0038] Optionally, in the future high power consumption instruction statistics window, when the number of future high power consumption instructions of the target computing unit is greater than or equal to the future high power consumption instruction threshold, it is determined that the future high power consumption instruction statistics window meets the risk condition;

[0039] In the current high-power-consumption instruction statistics window, when it is determined that the current instruction of the target computing unit is a high-power-consumption instruction, it is determined that the current high-power-consumption instruction statistics window meets the risk condition;

[0040] In the first past high power consumption instruction statistics window, when the number of past high power consumption instructions of the target computing unit is greater than or equal to the first past high power consumption instruction threshold, it is determined that the first past high power consumption instruction statistics window meets the risk condition;

[0041] In the second past high power consumption instruction statistics window, when the number of past high power consumption instructions of the target computing unit is less than or equal to the second past high power consumption instruction threshold, it is determined that the second past high power consumption instruction statistics window meets the risk condition.

[0042] Optionally, the high power consumption instruction information of the target computing unit may include whether the current instruction of the target computing unit is a high power consumption instruction, the number of past high power consumption instructions before the current instruction, and the number of future high power consumption instructions after the current instruction.

[0043] Optionally, the first past high power consumption instruction threshold and the second past high power consumption instruction threshold are both preset values, which can be the same value or different values. In order to reduce the amount of calculation, only high power consumption instructions are counted in the local risk inspection subunit, but in fact, low power consumption instructions also need to be monitored. Since there are only instructions in two states, high power consumption instructions and low power consumption instructions, in the computing unit, it is determined in the second past high power consumption instruction statistics window whether the number of past high power consumption instructions is less than or equal to the second past high power consumption instruction threshold. If so, it means that the number of past low power consumption instructions is greater than or equal to the second past high power consumption instruction threshold.

[0044] Optionally, when the future high-power consumption instruction statistical window, the current high-power consumption instruction statistical window, the first past high-power consumption instruction statistical window, and the second past high-power consumption instruction statistical window simultaneously meet the risk conditions, it is determined that there is a local risk in the target computing unit, a local risk signal is generated, and the local risk signal of the target computing unit is sent to the subsystem risk inspection unit of each computing unit in the subsystem.

[0045] S120. When receiving the local risk signal from the target computing unit, the subsystem risk checking subunit updates the past risk counter and the synchronous risk counter respectively according to the local risk signals sent by the remaining computing units in the subsystem.

[0046] Optionally, after the subsystem risk checking subunit of the target computing unit receives the local risk signal of the target computing unit, statistics are respectively performed on the past risk counter and the synchronous risk counter through the risk signal statistics window in the subsystem risk checking subunit.

[0047] Optionally, the past risk counter and the synchronous risk counter can serve as configurable risk signal inspection windows in the subsystem risk inspection subunit. The past risk counter and the synchronous risk counter can monitor and count risk signals in the target time period before the current moment. The target time period can be freely configured through the window. For example, the past risk counter can count the number of local risk signals sent by the remaining computing units in the subsystem during the time period from the last time the target computing unit generated a local risk signal to the current time the local risk signal was generated. The synchronous risk counter can count the number of local risk signals synchronously generated by the remaining computing units in the subsystem when the target computing unit generates a local risk signal, but is not limited to the time periods mentioned above.

[0048] S130. Execute corresponding protection operations according to the local risk signal and / or the counter update result through the currently enabled local risk protection subunit and / or subsystem risk protection subunit.

[0049] Optionally, according to preset configuration information, the enable switch of the local risk protection subunit and the enable switch of the subsystem risk protection subunit can be configured separately, so that the local risk protection subunit and the subsystem risk protection subunit can perform protection operations separately or jointly according to the configuration information.

[0050] In such Figure 2 In the example shown, after detection by the subsystem risk inspection subunit, the protection operation can be performed via the local risk protection subunit and the subsystem risk protection subunit, or via any one of the local risk protection subunit and the subsystem risk protection subunit.

[0051] Optionally, when the local risk protection subunit is turned on, if a local risk signal is generated, the local risk protection operation is initiated; when the subsystem risk protection subunit is turned on, the subsystem risk protection unit receives the count values ​​of the past risk counter and the synchronous risk counter sent by the subsystem risk detection subunit, and determines whether a subsystem risk protection operation is needed based on the count values.

[0052] Optionally, when the subsystem risk protection subunit is turned on, the subsystem risk protection subunit calculates the sum of the count values ​​of the past risk counter and the synchronous risk counter, obtains the subsystem risk count value, and determines whether the subsystem risk count value is greater than a preset subsystem risk threshold. If so, it is determined that the subsystem risk protection condition is met, and the subsystem risk protection subunit executes the subsystem risk protection operation.

[0053] Optionally, the local risk protection operation includes: whenever a first number of consecutive target high-power consumption instructions are detected, a second number of low-power consumption instructions are inserted after the last target high-power consumption instruction, and the above-mentioned local risk protection operation is executed in a loop for a specified number of times, wherein the first number, the second number and the specified number of loop executions are all preset values.

[0054] In an optional example, the local risk protection subunit can detect continuous high-power consumption instructions of the target computing unit. When M continuous target high-power consumption instructions are detected, N low-power consumption instructions are inserted after the Mth target high-power consumption instruction, and the above operation is performed K times, where M, N and K are all preset values.

[0055] Optionally, the subsystem risk protection operation includes: determining the number of low-power instructions to be inserted based on the count value of the past risk counter, the count value of the synchronous risk counter, and the preset past risk insertion number and synchronous risk insertion number, and inserting the matching number of low-power instructions before the first future high-power instruction.

[0056] Optionally, the low power consumption instruction may be a Stall instruction, but is not limited to a Stall instruction.

[0057] The technical solution of the embodiment of the present invention utilizes a local risk checking subunit. When a local risk is detected in a target computing unit, a local risk signal is sent to the subsystem risk checking subunit of each computing unit in the subsystem. When the subsystem risk checking subunit receives the local risk signal of the target computing unit, the past risk counter and the synchronous risk counter are updated according to the local risk signals sent by the remaining computing units in the subsystem. The currently enabled local risk protection subunit and / or subsystem risk protection subunit are used to perform corresponding protection operations according to the local risk signal and / or the counter update result. The high-power consumption instruction situation of each computing unit in the chip can be monitored. When there is a risk of current surge due to too many high-power consumption instructions, low-power consumption instructions are inserted at appropriate locations. This can ensure the power integrity while maximizing the utilization of the computing units. Moreover, the computing units and subsystems can be protected separately or jointly, which is suitable for complex and changeable chip usage scenarios.

[0058] Embodiment 2

[0059] Figure 3 This is a flow chart of a method for protecting the power integrity of a computing unit provided in the second embodiment of the present invention. This embodiment specifically describes the method for protecting the power integrity of a computing unit based on the above embodiment. Figure 3 As shown, the method includes:

[0060] S210 , using a local risk checking subunit, respectively counting high power consumption instructions of a target computing unit in different time periods in a plurality of high power consumption instruction statistics windows.

[0061] Optionally, the high power consumption instructions in different time periods may include future high power consumption instructions, current instructions, and past high power consumption instructions, wherein for the current instruction, it is only necessary to determine whether the current instruction is a high power consumption instruction.

[0062] S220. Through the local risk check sub-unit, in each high-power instruction statistics window, based on the high-power instruction statistics results of the window and the high-power instruction threshold matching the window, detect whether the window meets the risk condition, and when all high-power instruction statistics windows meet the risk condition, determine that the target computing unit has a local risk.

[0063] S230. Through the subsystem risk inspection subunit, when a local risk signal from a target computing unit is received, the number of local risk signals sent by the remaining computing units within the target time period before the current moment is determined, and the past risk counter is updated; as well as the number of local risk signals sent by the remaining computing units at the current moment is determined, and the synchronous risk counter is updated.

[0064] Optionally, after the subsystem risk checking subunit updates the synchronization risk counter and the past risk counter, when the subsystem risk protection subunit enable switch is turned on, the updated count value is sent to the subsystem risk protection subunit for the subsystem risk protection subunit to determine whether to turn on subsystem risk protection.

[0065] S240. When the local risk protection subunit is turned on and receives a local risk signal sent by the local risk checking subunit, the local risk protection subunit inserts a first low-power instruction at a target position in the to-be-executed instruction of the target computing unit according to a preset low-power instruction insertion rule.

[0066] Optionally, the first low power consumption instruction may refer to a low power consumption instruction inserted by the local risk protection subunit when the local risk protection is enabled.

[0067] Continuing with the previous example, if the local risk protection strategy is: when M consecutive target high-power instructions are detected, N low-power instructions are inserted after the Mth target high-power instruction, and the above operation is performed K times, and the target position is after the Mth target high-power instruction.

[0068] S250. When the subsystem risk protection subunit is turned on, the subsystem risk protection subunit determines the subsystem risk count value based on the count values ​​of the past risk counter and the synchronous risk counter sent by the subsystem risk checking subunit, and determines whether to turn on the subsystem risk protection operation based on the subsystem risk count value and the preset subsystem risk threshold.

[0069] Optionally, the subsystem risk counter value is the sum of the count values ​​of the past risk counter and the synchronous risk counter.

[0070] Optionally, when the subsystem risk count value is greater than a preset subsystem risk threshold, it is determined to enable the subsystem risk operation; otherwise, the subsystem risk protection operation is not performed.

[0071] S260. Through the subsystem risk protection subunit, when it is determined to start the subsystem risk protection operation, the number of second low power instructions is determined according to the count values ​​of the past risk counter and the synchronous risk counter, and the second low power instruction is inserted before the first instruction to be executed of the target computing unit.

[0072] Optionally, the second low power consumption instruction may refer to a low power consumption instruction inserted by the subsystem risk protection subunit when enabling subsystem risk protection.

[0073] Optionally, the number of past risk insertions and the number of synchronous risk insertions can be preset, and the number of second power consumption instructions can be calculated by the following formula: Subsystem_stall_num = past_risk_counter * past_risk_stall_num + concurrent_risk_counter * concurrent_risk_stall_num; wherein, Subsystem_stall_num is the number of second power consumption instructions, past_risk_counter is the count value of the past risk counter, past_risk_stall_num is the number of past risk insertions, concurrent_risk_counter is the count value of the synchronous risk counter, and concurrent_risk_stall_num is the number of synchronous risk insertions.

[0074] The technical solution of the embodiment of the present invention utilizes a local risk checking subunit. When a local risk is detected in a target computing unit, a local risk signal is sent to the subsystem risk checking subunit of each computing unit in the subsystem. When the subsystem risk checking subunit receives the local risk signal of the target computing unit, the past risk counter and the synchronous risk counter are updated according to the local risk signals sent by the remaining computing units in the subsystem. The currently enabled local risk protection subunit and / or subsystem risk protection subunit are used to perform corresponding protection operations according to the local risk signal and / or the counter update result. The high-power consumption instruction situation of each computing unit in the chip can be monitored. When there is a risk of current surge due to too many high-power consumption instructions, low-power consumption instructions are inserted at appropriate locations. This can ensure the power integrity while maximizing the utilization of the computing units. Moreover, the computing units and subsystems can be protected separately or jointly, which is suitable for complex and changeable chip usage scenarios.

[0075] Embodiment 3

[0076] Figure 4 This is a schematic diagram of the structure of a computing unit power integrity protection device provided in Embodiment 3 of the present invention. Figure 4 As shown, the device includes: a local risk checking module 310 , a subsystem risk checking module 320 and a power integrity protection module 330 .

[0077] The local risk check module 310 is used to perform local risk detection on the target computing unit according to the high power consumption instruction information of the target computing unit through the local risk check subunit, and when it is determined that the target computing unit has a local risk, send the local risk signal to the subsystem risk check subunit of each computing unit in the subsystem.

[0078] The subsystem risk checking module 320 is used to update the past risk counter and the synchronous risk counter respectively according to the local risk signals sent by the remaining computing units in the subsystem through the subsystem risk checking subunit when receiving the local risk signal of the target computing unit.

[0079] The power integrity protection module 330 is used to perform corresponding protection operations according to the local risk signal and / or the counter update result through the currently enabled local risk protection subunit and / or subsystem risk protection subunit.

[0080] The technical solution of the embodiment of the present invention utilizes a local risk checking subunit. When a local risk is detected in a target computing unit, a local risk signal is sent to the subsystem risk checking subunit of each computing unit in the subsystem. When the subsystem risk checking subunit receives the local risk signal of the target computing unit, the past risk counter and the synchronous risk counter are updated according to the local risk signals sent by the remaining computing units in the subsystem. The currently enabled local risk protection subunit and / or subsystem risk protection subunit are used to perform corresponding protection operations according to the local risk signal and / or the counter update result. The high-power consumption instruction situation of each computing unit in the chip can be monitored. When there is a risk of current surge due to too many high-power consumption instructions, low-power consumption instructions are inserted at appropriate locations. This can ensure the power integrity while maximizing the utilization of the computing units. Moreover, the computing units and subsystems can be protected separately or jointly, which is suitable for complex and changeable chip usage scenarios.

[0081] Based on the above embodiments, the local risk checking module 310 can be specifically used for:

[0082] By using a local risk checking subunit, statistics are collected on high-power instructions of a target computing unit in different time periods in a plurality of high-power instruction statistics windows;

[0083] Through the local risk check sub-unit, in each high-power instruction statistical window, based on the high-power instruction statistical results of the window and the high-power instruction threshold matching the window, it is detected whether the window meets the risk condition; and when all high-power instruction statistical windows meet the risk condition, it is determined that the target computing unit has a local risk.

[0084] On the basis of the above embodiments, the high power consumption instruction statistics window includes a future high power consumption instruction statistics window, a current high power consumption instruction statistics window, a first past high power consumption instruction statistics window and a second past high power consumption instruction statistics window;

[0085] Wherein, in the future high power consumption instruction statistics window, when the number of future high power consumption instructions of the target computing unit is greater than or equal to the future high power consumption instruction threshold, it is determined that the future high power consumption instruction statistics window meets the risk condition;

[0086] In the current high-power-consumption instruction statistics window, when it is determined that the current instruction of the target computing unit is a high-power-consumption instruction, it is determined that the current high-power-consumption instruction statistics window meets the risk condition;

[0087] In the first past high power consumption instruction statistics window, when the number of past high power consumption instructions of the target computing unit is greater than or equal to the first past high power consumption instruction threshold, it is determined that the first past high power consumption instruction statistics window meets the risk condition;

[0088] In the second past high power consumption instruction statistics window, when the number of past high power consumption instructions of the target computing unit is less than or equal to the second past high power consumption instruction threshold, it is determined that the second past high power consumption instruction statistics window meets the risk condition.

[0089] Based on the above embodiments, the subsystem risk checking module 320 can be specifically used for:

[0090] Through the subsystem risk inspection subunit, when a local risk signal from a target computing unit is received, the number of local risk signals sent by the remaining computing units within the target time period before the current moment is determined, and the past risk counter is updated, as well as the number of local risk signals sent by the remaining computing units at the current moment is determined, and the synchronous risk counter is updated.

[0091] Based on the above embodiments, the power integrity protection module 330 may include a local risk protection submodule and a subsystem risk protection submodule;

[0092] The local risk protection submodule can be used specifically for:

[0093] When the local risk protection subunit is turned on and receives a local risk signal sent by the local risk checking subunit, the local risk protection subunit inserts a first low-power instruction at a target position in the to-be-executed instruction of the target computing unit according to a preset low-power instruction insertion rule.

[0094] Based on the above embodiments, the subsystem risk protection submodule can be specifically used for:

[0095] When the subsystem risk protection subunit is turned on, the subsystem risk protection subunit determines the subsystem risk count value according to the count values ​​of the past risk counter and the synchronous risk counter sent by the subsystem risk checking subunit, and determines whether to turn on the subsystem risk protection operation according to the subsystem risk count value and the preset subsystem risk threshold;

[0096] Through the subsystem risk protection subunit, when it is determined to start the subsystem risk protection operation, the number of second low power instructions is determined according to the count values ​​of the past risk counter and the synchronous risk counter, and the second low power instruction is inserted before the first instruction to be executed of the target computing unit.

[0097] On the basis of the above embodiments, the subsystem includes a plurality of computing units, each of which is configured with a local risk checking subunit, a subsystem risk checking subunit, a local risk protection subunit and a subsystem risk protection subunit for performing a joint protection operation on the computing unit;

[0098] Among them, according to the preset configuration information, the enabling switch of the local risk protection subunit and the enabling switch of the subsystem risk protection subunit can be configured separately.

[0099] The computing unit power integrity protection device provided in the embodiment of the present invention can execute the computing unit power integrity protection method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0100] Embodiment 4

[0101] Figure 5 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0102] like Figure 5 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. The input / output (I / O) interface 15 is also connected to the bus 14.

[0103] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0104] The processor 11 may be any general and / or dedicated processing component with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the method for protecting the power integrity of the computing unit as described in any embodiment of the present invention. That is:

[0105] By means of the local risk checking subunit, a local risk detection is performed on the target computing unit according to the high power consumption instruction information of the target computing unit, and when it is determined that the target computing unit has a local risk, a local risk signal is sent to the subsystem risk checking subunit of each computing unit in the subsystem respectively;

[0106] When receiving the local risk signal of the target computing unit, the subsystem risk checking subunit updates the past risk counter and the synchronous risk counter according to the local risk signals sent by the remaining computing units in the subsystem;

[0107] The corresponding protection operation is performed according to the local risk signal and / or the counter update result through the currently enabled local risk protection subunit and / or subsystem risk protection subunit.

[0108] In some embodiments, the protection method of the power integrity of the computing unit may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the protection method of the power integrity of the computing unit described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the protection method of the power integrity of the computing unit in any other appropriate manner (for example, by means of firmware).

[0109] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0110] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0111] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0112] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0113] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0114] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0115] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0116] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for protecting the power integrity of a computing unit, executed by a computing unit in a chip, characterized in that: include: By means of the local risk checking subunit, a local risk detection is performed on the target computing unit according to the high power consumption instruction information of the target computing unit, and when it is determined that the target computing unit has a local risk, a local risk signal is sent to the subsystem risk checking subunit of each computing unit in the subsystem respectively; When receiving the local risk signal of the target computing unit, the subsystem risk checking subunit updates the past risk counter and the synchronous risk counter according to the local risk signals sent by the remaining computing units in the subsystem; Execute corresponding protection operations according to the local risk signal and / or the counter update result through the currently enabled local risk protection subunit and / or subsystem risk protection subunit; The subsystem includes a plurality of computing units, each of which is configured with a local risk check subunit, a subsystem risk check subunit, a local risk protection subunit and a subsystem risk protection subunit for performing joint protection operations on the computing unit; Among them, the past risk counter counts the number of local risk signals sent by the remaining computing units in the subsystem during the time period from the last time the target computing unit generated a local risk signal to the time the local risk signal is generated this time, and the synchronous risk counter counts the number of local risk signals synchronously generated by the remaining computing units in the subsystem when the target computing unit generates a local risk signal; Among them, when the subsystem risk protection subunit is turned on, the subsystem risk protection subunit calculates the sum of the count values ​​of the past risk counter and the synchronous risk counter, obtains the subsystem risk count value, and determines whether the subsystem risk count value is greater than the preset subsystem risk threshold. If so, it is determined that the subsystem risk protection condition is met, and the subsystem risk protection subunit executes the subsystem risk protection operation.

2. The method according to claim 1, characterized in that The local risk detection subunit performs local risk detection on the target computing unit according to the high power consumption instruction information of the target computing unit, including: By using a local risk checking subunit, statistics are collected on high-power-consumption instructions of a target computing unit in different time periods in a plurality of high-power-consumption instruction statistics windows; Through the local risk check sub-unit, in each high-power instruction statistical window, based on the high-power instruction statistical results of the window and the high-power instruction threshold matching the window, it is detected whether the window meets the risk condition; and when all high-power instruction statistical windows meet the risk condition, it is determined that the target computing unit has a local risk.

3. The method according to claim 2, characterized in that The high power consumption instruction statistics window includes a future high power consumption instruction statistics window, a current high power consumption instruction statistics window, a first past high power consumption instruction statistics window, and a second past high power consumption instruction statistics window; Wherein, in the future high power consumption instruction statistics window, when the number of future high power consumption instructions of the target computing unit is greater than or equal to the future high power consumption instruction threshold, it is determined that the future high power consumption instruction statistics window meets the risk condition; In the current high-power-consumption instruction statistics window, when it is determined that the current instruction of the target computing unit is a high-power-consumption instruction, it is determined that the current high-power-consumption instruction statistics window meets the risk condition; In the first past high power consumption instruction statistics window, when the number of past high power consumption instructions of the target computing unit is greater than or equal to the first past high power consumption instruction threshold, it is determined that the first past high power consumption instruction statistics window meets the risk condition; In the second past high power consumption instruction statistics window, when the number of past high power consumption instructions of the target computing unit is less than or equal to the second past high power consumption instruction threshold, it is determined that the second past high power consumption instruction statistics window meets the risk condition.

4. The method according to claim 1, characterized in that: When receiving the local risk signal of the target computing unit, the subsystem risk checking subunit updates the past risk counter and the synchronous risk counter according to the local risk signals sent by the remaining computing units in the subsystem, including: Through the subsystem risk inspection subunit, when a local risk signal from a target computing unit is received, the number of local risk signals sent by the remaining computing units within the target time period before the current moment is determined, and the past risk counter is updated, as well as the number of local risk signals sent by the remaining computing units at the current moment is determined, and the synchronous risk counter is updated.

5. The method according to claim 4, characterized in that Through the currently enabled local risk protection subunit and / or subsystem risk protection subunit, corresponding protection operations are performed according to the local risk signal and / or counter update result, including: When the local risk protection subunit is turned on and receives a local risk signal sent by the local risk checking subunit, the local risk protection subunit inserts a first low-power instruction at a target position in the to-be-executed instruction of the target computing unit according to a preset low-power instruction insertion rule.

6. The method according to claim 5, characterized in that Executing corresponding protection operations according to the local risk signal and / or the counter update result through the currently enabled local risk protection subunit and / or the subsystem risk protection subunit, further comprising: When the subsystem risk protection subunit is turned on, the subsystem risk protection subunit determines the subsystem risk count value according to the count values ​​of the past risk counter and the synchronous risk counter sent by the subsystem risk checking subunit, and determines whether to turn on the subsystem risk protection operation according to the subsystem risk count value and the preset subsystem risk threshold; Through the subsystem risk protection subunit, when it is determined to start the subsystem risk protection operation, the number of second low power instructions is determined according to the count values ​​of the past risk counter and the synchronous risk counter, and the second low power instruction is inserted before the first instruction to be executed of the target computing unit.

7. The method according to any one of claims 1 to 6, characterized in that: According to the preset configuration information, the enabling switch of the local risk protection subunit and the enabling switch of the subsystem risk protection subunit can be configured separately.

8. A computing unit power integrity protection device, executed by a computing unit in a chip, characterized in that: include: A local risk checking module is used to perform local risk detection on a target computing unit according to the high power consumption instruction information of the target computing unit through a local risk checking subunit, and when it is determined that the target computing unit has a local risk, send a local risk signal to the subsystem risk checking subunit of each computing unit in the subsystem; The subsystem risk checking module is used to update the past risk counter and the synchronous risk counter respectively according to the local risk signals sent by the remaining computing units in the subsystem through the subsystem risk checking subunit when receiving the local risk signal of the target computing unit; A power integrity protection module, configured to perform corresponding protection operations according to a local risk signal and / or a counter update result through a currently enabled local risk protection subunit and / or a subsystem risk protection subunit; The subsystem includes a plurality of computing units, each of which is configured with a local risk check subunit, a subsystem risk check subunit, a local risk protection subunit and a subsystem risk protection subunit for performing joint protection operations on the computing unit; Among them, the past risk counter counts the number of local risk signals sent by the remaining computing units in the subsystem during the time period from the last time the target computing unit generated a local risk signal to the time the local risk signal is generated this time, and the synchronous risk counter counts the number of local risk signals synchronously generated by the remaining computing units in the subsystem when the target computing unit generates a local risk signal; Among them, when the subsystem risk protection subunit is turned on, the subsystem risk protection subunit calculates the sum of the count values ​​of the past risk counter and the synchronous risk counter, obtains the subsystem risk count value, and determines whether the subsystem risk count value is greater than the preset subsystem risk threshold. If so, it is determined that the subsystem risk protection condition is met, and the subsystem risk protection subunit executes the subsystem risk protection operation.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the method for protecting the power integrity of a computing unit according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method for protecting the power integrity of a computing unit according to any one of claims 1 to 7 when the processor executes the computer instructions.

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