Data flow graph making method, computer device and storage medium

Abstract

The present disclosure provides a method for making a data flow graph, a computer device and a storage medium. The method includes: obtaining a chip design layout; determining at least one first connection number with any element as an output end and at least one second connection number with any element as an input end according to the chip design layout; screening at least one first connection number and at least one second connection number according to a set threshold, respectively, retaining the first data stream corresponding to the first connection number or the second connection number that passes the screening; swapping the output end and the input end of the first data stream, and re-screening the first data stream according to the set threshold, determining the second data stream that passes the screening; outputting the first data stream and the second data stream, so as to make a data flow graph according to the first data stream and the second data stream.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to a data flow graph production method, a computer device and a storage medium. Background Art

[0002] As a core tool for chip design data flow analysis and processing in the EDA (Electronic Design Automation) industry, the importance of data flow graphs is self-evident. However, as the complexity of chip design continues to increase, data flow graphs have also become larger and more complex, containing a large number of nodes and complex connection relationships. This high degree of complexity not only greatly increases the difficulty of direct analysis, but also significantly prolongs the analysis cycle, becoming a key factor restricting the efficiency of data analysis and design decision-making in the EDA field. Summary of the invention

[0003] In view of this, the present disclosure proposes a data flow graph production method, a computer device and a storage medium to solve or partially solve the above-mentioned problems.

[0004] Based on the above objectives, in a first aspect, the present disclosure provides a method for producing a data flow graph, comprising:

[0005] Obtain chip design layout;

[0006] According to the chip design layout, determining at least one first connection number with any element as an output end, and at least one second connection number with any element as an input end;

[0007] Screening the at least one first connection number and the at least one second connection number respectively according to a set threshold, and retaining the first data flow corresponding to the first connection number or the second connection number that passes the screening;

[0008] swapping the output end and the input end of the first data stream, and re-screening the first data stream according to the set threshold value to determine a second data stream that passes the screening;

[0009] The first data stream and the second data stream are output to produce a data flow graph according to the first data stream and the second data stream.

[0010] In a second aspect of the present disclosure, a computer device is provided, comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to the first aspect.

[0011] According to a third aspect of the present disclosure, a non-volatile computer-readable storage medium containing a computer program is provided. When the computer program is executed by one or more processors, the processors execute the method described in the first aspect.

[0012] As can be seen from the above, the present disclosure provides a data flow diagram production method, computer equipment and storage medium. The present disclosure first determines the components in the chip design layout, counts the number of connections of the components as output terminals or input terminals, screens the number of connections, retains the more important data streams with more connections, and removes the data streams with fewer connections; then reversely screens the remaining data streams again to prevent missing reverse data streams, and finally draws the data flow diagram according to the results after the two screenings, so that the critical path in the EDA data flow diagram can be clearly highlighted, helping users to quickly and accurately grasp the key points in the data flow diagram, accurately identify the critical path and potential performance bottlenecks, thereby significantly improving the efficiency and accuracy of data analysis and design decisions. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0014] Figure 1 A schematic diagram of the hardware structure of an exemplary computer device provided in an embodiment of the present disclosure is shown.

[0015] Figure 2 A basic structural diagram of an EDA tool according to an embodiment of the present disclosure is shown.

[0016] Figure 3 A schematic diagram showing a basic execution flow of a calculation command of an EDA tool according to an embodiment of the present disclosure is shown.

[0017] Figure 4 A flow chart of an exemplary method provided according to an embodiment of the present application is shown.

[0018] Figure 5 A schematic diagram of a data flow diagram of an exemplary method provided in an embodiment of the present application before adjustment is performed is shown.

[0019] Figure 6 A schematic diagram of a data flow diagram after adjustment according to the exemplary method provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of this specification more clear, this specification is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements, objects or method steps appearing before the word cover the elements, objects or method steps listed after the word and their equivalents, without excluding other elements, objects or method steps. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] Figure 1 The schematic diagram of the structure of a computer device 100 provided by an embodiment of the present disclosure is shown. The computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other in communication within the device through the bus 110.

[0023] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this disclosure. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0024] The memory 104 may be configured to store data (eg, instruction sets, computer codes, intermediate data, etc.). Figure 1As shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solution of the present disclosure) and data to be processed. The processor 102 may also access the stored program instructions and data, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0025] The network interface 106 can be configured to provide the computer device 100 with communication with other external devices via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0026] The peripheral interface 108 may be configured to connect the computer device 100 to one or more peripheral devices to implement information input and output. For example, the peripheral devices may include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0027] The bus 110 may be configured to transmit information between various components of the computer device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0028] It should be noted that, although the above device only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present disclosure, and does not necessarily include all the components shown in the figure.

[0029] Figure 2 A basic structural diagram of an EDA tool 200 according to an embodiment of the present disclosure is shown.

[0030] like Figure 2As shown, the part above the dotted line is the user part; the part below the dotted line is the EDA tool 200, which can be Figure 1 The device 100 shown is implemented. In some embodiments, the EDA tool 200 can be implemented as EDA software. More specifically, the EDA tool 200 can be software for performing placement and routing based on chip design. The simulation tool 200 may include a Tcl command (or a graphic / window interface) module 204, various calculation modules (e.g., a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc.) and a database system 212. The user 202 can operate the EDA tool 200 by entering relevant commands in the Tcl command (or graphic / window interface) module 204.

[0031] The Tcl command module 204 mainly performs the functions of message transmission or command transmission. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can distribute and transmit the instructions to the corresponding computing modules to perform specific tasks according to the specific contents of the instructions.

[0032] According to different computing tasks, each computing module can be divided into, for example, a Place computing module 206, a Route computing module 208, an Optimization computing module 210, etc. The Place computing module 206 can be used to calculate a reasonable placement position for all components, the Route computing module 208 can be used to calculate a reasonable wire connection method between each component, and the Optimization computing module 210 can be used to optimize the placement position and wire connection method between each component. The computing process of these computing modules can be, for example, Figure 1 is performed in the processor 102.

[0033] The database system 212 can be used to completely and comprehensively record and store all information of the chip being simulated or designed (such as location, direction, size, structure, wire connection method, etc.). This information, for example, can be stored in Figure 1 in the memory 104.

[0034] Figure 3 FIG. 3 shows a basic execution flow 300 of a calculation command of the EDA tool 200 according to an embodiment of the present disclosure. Figure 3As shown, in step 302, the user 202 can issue a command (e.g., do_place command) to the EDA tool 200 through the command interface or graphical user interface (GUI) provided by the Tcl command module 204. Then, in step 304, the Tcl command module 204 parses this command and distributes it to the corresponding calculation module (e.g., Place calculation module 206). In step 306, each calculation module performs the specific calculation required by each. During this period, as shown in step 308, each calculation module needs to (high frequency, repeatedly) retrieve data from the database system 212 for calculation. After the calculation is completed, as shown in step 310, each calculation module can write the calculation result into the database system 212 and return the calculation result to the Tcl command module 204. In step 312, the Tcl command module 204 returns the calculation result to the user 202 through the command interface or graphical user interface (GUI), and the EDA tool 200 ends the processing process of a calculation command. In step 314, the user can evaluate according to the calculation result and then determine the next plan.

[0035] In some embodiments, when the user has basically completed the chip design layout using EDA, it may be necessary to analyze the data flow of the chip design to make more detailed adjustments, which requires the use of a data flow diagram that draws chip components (generally represented as nodes in the data flow diagram) and data flows. However, as the complexity of chip design continues to increase, the data flow diagram has also become larger and more complex, containing a large number of nodes and complex connection relationships. Figure 5 As shown in the figure, it is a partial schematic diagram of a data flow graph. It can be seen that even a partial data flow graph contains a lot of data flows, which are relatively messy, and users cannot grasp the key parts of the data flow graph. Among them, each component of the chip is represented by p, and p1 to p8 in the figure are eight components; the I terminal is the total input terminal, and the O terminal is the total output terminal.

[0036] After that, other fields also have corresponding methods for processing or managing data flows. However, traditional data analysis methods are particularly difficult to process data flow graphs of such scale, and they often find it difficult to accurately and efficiently extract critical paths in a huge ocean of data. This is because other fields or traditional data analysis methods do not need to process such large and complex data flows, and for data flows in other fields, there is generally not much distinction between nodes and the weights are similar for each node in the data flow graph. However, in the field of chip design, for the data flow graph summarized in the chip design layout, most of the data flows are processed through fewer nodes, such as "90% of the data flows are processed through 10% of the nodes". Such nodes can be understood as key nodes or key points of the data flow graph in the EDA scenario, and their paths are the critical paths. As the core context in the data flow graph, the critical path plays an irreplaceable role in deeply understanding the data flow, accurately analyzing the data processing logic, and optimizing the chip design performance. However, due to the complex structure of data flow graphs and the diversity of connections between nodes, traditional methods often find it difficult to accurately locate these key paths, resulting in analysis results that are not comprehensive or in-depth enough, and it is difficult to meet the EDA industry's needs for high-precision and high-efficiency analysis.

[0037] Due to the complexity of data flow graphs, it is often difficult for users to identify which nodes and connections are the focus of analysis at the first time, so it is impossible to conduct detailed analysis from the key data to the surrounding areas, which further increases the difficulty and uncertainty of the analysis.

[0038] In view of this, the present disclosure proposes a method for making a data flow graph. The present disclosure first determines the components in the chip design layout, counts the number of connections of the components as output terminals or input terminals, screens the number of connections, retains the more important data flows with more connections, and removes the data flows with fewer connections; then, reversely screens the remaining data flows again to prevent missing reverse data flows, and finally draws a data flow graph based on the results of the two screenings, so that the critical path in the EDA data flow graph can be clearly highlighted, helping users to quickly and accurately grasp the key points in the data flow graph, accurately identify the critical path and potential performance bottlenecks, and thus significantly improve the efficiency and accuracy of data analysis and design decisions.

[0039] Figure 4 FIG. 4 is a flow chart of an exemplary method 400 provided by an embodiment of the present disclosure. The method 400 may be Figure 1 The computer device 100 is implemented and can be implemented as Figure 2 A portion of the functionality of the EDA tool 200. Figure 4 As shown, the method 400 may further include the following steps.

[0040] Step 402, obtaining a chip design layout.

[0041] Generally, the chip design layout includes each layer structure of chip processing, specific transistor layout, wiring, routing, channel via interlayer connection position, etc. According to the chip design layout, the chip processing service provider can directly run and carry out batch processing and production of chips. Furthermore, the chip design layout itself is drawn step by step, accompanied by various optimizations, and finally the entire chip design layout is completed. In the early stage of the chip design layout, it may only indicate the functional information of the hierarchy, such as a certain layer is a routing layer, a certain layer is an insulation layer, etc.; or only various functional components are set, indicating the position, size and other information of each functional component. After that, EDA tools are used to carry out step-by-step design and optimization, and finally a complete version of the chip design layout is formed. Here, the components can be standard processing units, modules or hard cores, input / output terminals, registers, etc. in the chip.

[0042] In this step, since the data flow graph is being produced, it is generally necessary to determine which components are included in the chip design layout, the initial positions of these components, and the required connection relationships between these components, etc. In specific application scenarios, the initial data information such as the hierarchical structure and component positions can be obtained through the DEF (Design Exchange File, physical information of the design library) file and / or LEF (Library Exchange File, physical information of the process library) file of the chip design layout.

[0043] In addition, in this step, the chip design layout can be local (for example, the entire design layout is divided into a large number of sub-areas) or overall.

[0044] Step 404: Determine, based on the chip design layout, at least one first connection number using any component as an output terminal and at least one second connection number using any component as an input terminal.

[0045] In this step, after obtaining the chip design layout, the initial data flows can be determined according to the markings therein. These data flows generally reach the end position after passing through at least one element from the starting position, and the elements are the nodes in this data flow.

[0046] Afterwards, for any data stream, if it is segmented at each node, multiple data stream segments can be obtained, which are referred to as data segments here. Furthermore, for a data segment, it only includes the node as the output end (starting end) and the node as the input end (ending end), as well as the data segment between the two nodes. In this way, by counting all or part of the data stream, at least one first connection number and at least one second connection number of any node (element) as the output end and as the input end can be determined. For example, after sorting and counting, node A will transmit data to nodes B, C, and D respectively as the output end, wherein there are 200 data segments from node A to node B, 100 data segments to node C, and 220 data segments to node D, then the first connection number of node A is 200, 100, and 220 respectively. Of course, in some embodiments, the segmentation of the data segment can be performed as a step, or it can be used only as an operation mode, directly analyzing all the data streams involved, and then forming the first connection number and the second connection number of any element. The number of connections here is the number of connections formed. If there is one data segment between node A and node B, the number of connections is 1; if there are ten data segments, the number of connections is 10.

[0047] In some embodiments, the data stream can be segmented in steps, and the data segments can be determined, and finally the first connection number and the second connection number of any element can be counted based on the data segments. That is, in some embodiments, before determining at least one first connection number with any element as the output end, the method also includes: determining at least one data stream in the chip design layout; segmenting the at least one data stream into data segments to generate at least one data segment; wherein the data segment is the result of segmenting the at least one data stream based on the element, and the data segment only contains one element as the output end and one element as the input end; and counting the at least one first connection number and the at least one second connection number through the at least one data segment.

[0048] In the specific process of counting the first connection number or the second connection number, for a certain element, when it is used as an output end, the number of data segments of other different elements as input ends is counted respectively, so as to determine at least one first connection number of the element. Similarly, when it is used as an input end, the number of data segments of other different elements as output ends is counted respectively, so as to determine at least one second connection number of the element. In combination with the above example, after completing the segmentation of the data segment, the data transmission of node A as the output end will be counted to nodes B, C, and D respectively, and the first connection number of node A is 200, 100, and 220 respectively; similarly, the data transmission of node A as the output end will be counted to nodes E, F, and G respectively, where there are 300 data segments from node E to node A, 250 data segments from node F to node A, and 400 data segments from node G to node A, then the second connection number of node A is 300, 250, and 400 respectively.

[0049] In some embodiments, the chip design layout generally contains a large number of components and numerous data flows. In order to facilitate the observation of the data flow, the data flow diagram can be made for only one area or part of the components at a time, that is, the data flow is determined only for the set or user-selected target area, and finally the data flow diagram is generated. That is, in some embodiments, the determination of at least one data flow in the chip design layout includes: determining the target area in the chip design layout; and counting the data flow in the target area to determine the at least one data flow.

[0050] Step 406: Screen the at least one first connection number and the at least one second connection number according to the set threshold, and retain the first data flow corresponding to the first connection number or the second connection number that passes the screening.

[0051] In this step, for any component, the first connection number and the second connection number can be screened respectively, and both screenings can be performed based on a set threshold.

[0052] Since the purpose of this embodiment is to retain important data paths and eliminate unimportant data paths. Therefore, when screening, screening can be performed based on whether the first connection number or the second connection number exceeds a certain value, or the first connection number or the second connection number can be screened in a decreasing manner according to a certain proportion among all first connection numbers or all second connection numbers, etc. For decreasing screening, taking the first connection number as an example, the one with the largest number of connections can be selected from multiple first connection numbers of an element, such as 400; then, calculation is performed according to a set threshold (such as 90%), that is, 400*90% is 360, then for all data segments corresponding to the first connection numbers, data segments with more than 360 connections are retained, and data segments with less than 360 connections are removed. In this way, the data segments corresponding to the second connection number are processed in the same or similar manner, and the retained ones are the first data streams.

[0053] That is, in some embodiments, the screening of the at least one first connection number according to the set threshold value includes: determining a first maximum value among the at least one first connection number, determining a first value that passes the screening according to the first maximum value and the set threshold value; and determining that a value greater than or equal to the first value passes the screening among the at least one first connection number. The screening of the at least one second connection number according to the set threshold value includes: determining a second maximum value among the at least one second connection number, determining a second value that passes the screening according to the second maximum value and the set threshold value; and determining that a value greater than or equal to the second value passes the screening among the at least one second connection number. The first value and the second value are the values ​​set according to the aforementioned method. The connection value that can pass the screening is determined by the maximum first connection number or the second connection number.

[0054] Step 408: swap the output end and the input end of the first data stream, and re-screen the first data stream according to the set threshold value to determine a second data stream that passes the screening.

[0055] In this step, it is determined whether the reverse data flow of the first data flow that has passed the screening needs to be supplemented. In general data flow processing methods or fields, for a data flow, it is almost bidirectional. For example, in general scenarios, most data flows are in "question and answer" mode, that is, the sender sends a request to the receiver, and then the receiver replies with a response to the sender based on the request. It can be seen that this makes the general data flow in both directions generally have the same weight, and it is usually an interactive process. In the EDA field, it is completely different. In the chip field, general data flows are unidirectional, flowing from node A to node B, and then to node C, and there is generally no interactive process. Furthermore, this is also one of the reasons why ordinary data analysis methods are not ideal when applied to the chip field.

[0056] In this embodiment, for the first data stream filtered by step 406, in some special scenarios, it may be necessary to perform a process of filling the gaps in the reverse direction of the data segments in the first data stream. That is, this step is a supplement to the first data stream filtered out by step 406. In the specific execution process, the screening process is similar to that in step 406, and the same set threshold can be applied. The only difference is that the output end and the input end of the data segment are swapped, and the screening benchmark is changed from all data segments to data segments belonging to the first data stream. In this way, the data segments that were previously filtered out in the reverse direction may meet the screening requirements again in this step, thereby forming a second data stream.

[0057] Step 410, outputting the first data stream and the second data stream to produce a data flow graph according to the first data stream and the second data stream.

[0058] In this step, the screened first data flow and the second data flow are the sorted data flows that are more important in the EDA scenario, and the other less critical ones are directly removed. Then, a data flow graph can be produced based on these refined data flows, so that the produced data flow graph can clearly highlight the key points, help users quickly and accurately grasp the key points in the data flow graph, accurately identify critical paths and potential performance bottlenecks, thereby significantly improving the efficiency and accuracy of data analysis and design decisions.

[0059] Afterwards, the first data stream and the second data stream, or the prepared data flow diagram, can be displayed and output on the corresponding device to give the operator corresponding feedback. Of course, in other embodiments, the output method for the above data to be output may not be limited to output display, and it can also be used to store, display, use or reprocess the data to be output. According to different application scenarios and implementation needs, the specific output method for the data to be output can be flexibly selected.

[0060] For example, for an application scenario in which the method of this embodiment is executed on a single device, the data that needs to be output can be directly output in a displayed manner on the display component (display, projector, etc.) of the current device, so that the operator of the current device can directly see the content of the data that needs to be output from the display component.

[0061] For another example, for an application scenario where the method of this embodiment is executed on a system composed of multiple devices, the data to be output can be sent to other preset devices as receivers in the system, that is, synchronization terminals, through any data communication method (wired connection, NFC, Bluetooth, wifi, cellular mobile network, etc.), so that the synchronization terminal can process it later. Optionally, the synchronization terminal can be a preset server, which is generally set up in the cloud as a data processing and storage center, which can store and distribute the data to be output; wherein the recipient of the distribution is the terminal device, and the holder or operator of these terminal devices can be the chip designer, planner, regulator, superior supervisor, etc.

[0062] For another example, in an application scenario where the method of this embodiment is executed on a system composed of multiple devices, the data to be output can be sent directly to a preset terminal device through any data communication method, and the terminal device can be one or more of the ones listed in the preceding paragraphs.

[0063] In some embodiments, the designer or operator will specify some special nodes (elements). These special nodes may be more important nodes during design, but the number of connections in their data streams is not necessarily very high. Therefore, for these special nodes, all their connections and data segments can be directly retained, that is, the screening process is skipped and all of them are retained. That is, in some embodiments, before outputting the first data stream and the second data stream, the method also includes: determining whether there are designated elements in the chip design layout; in response to the existence of the designated element, all data streams with the designated element as the input or output end are retained and merged with the first data stream and / or the second data stream. The designated element is the aforementioned special node (element). In a more specific scenario, there are generally not many such nodes, for example, there are only 10 or even fewer such elements in the entire chip design layout.

[0064] Later, in some more specific embodiments, the first data stream and the second data stream are generally used to make a data flow graph. In the process of making a data flow graph, in order to more clearly indicate the number of data streams specifically included in each line segment, the specific number of connections can be marked on the corresponding line segment. Figure 6 As shown, Figure 5 The data flow shown is a data flow diagram formed after the data flow is screened according to this embodiment, in which each line segment is marked with a specific number of connections (that is, the number of connections between two adjacent components in a data flow). At the same time, each component of the chip is represented by p, such as Figure 5 or Figure 6As shown, p1 to p8 are eight elements. That is, in some embodiments, after outputting the first data stream and the second data stream, the method further includes: generating a data flow graph according to the first data stream and the second data stream, and indicating the number of connections between adjacent elements in the data flow graph; wherein adjacent elements are adjacent elements in any data stream in the data flow graph.

[0065] Furthermore, for a data flow graph, it is also necessary to indicate the total input end and the total output end of the data, so as to form a complete data flow graph. Figure 6 As shown, the total input end and the total output end of all data flows can be determined, that is, the "I" module (in module, indicating the total input end) and the "O" module (out module, indicating the total output end) located at the left and right ends of the figure, so as to form a complete data flow graph. That is, in some embodiments, the generating of the data flow graph includes: determining the total input end and the total output end of the data flow graph according to the first data flow and the second data flow, and marking the total input end and the total output end at the set position of the data flow graph.

[0066] In a more specific scenario, combined with Figure 5 and Figure 6 To explain, Figure 5 This is the data flow diagram before processing. Figure 6 is the processed data flow graph. After that, the specific processing process is as follows: (1) Preprocess the data flow and organize it into a node-to-node directed graph. Each node is (2)Do the first analysis and analyze For any , there may be multiple As the starting point of the connection, or This is the connection to the end point. The end point is called input. As the starting point, it is called output. (3) For any The input and output are based on the threshold Descending filtering, in which case the input and output are filtered separately. In this case, a single connection is called , filter according to the above conditions, and remove those that do not meet the conditions All are filtered out. (4) Bidirectional connection supplement, for the filtered , the starting point is pstart, the end point is pend, and the reverse connection is , through the screening Based on the positive screening method, Screening is performed, and those that pass the screening are supplemented (5) Special module supplement, if a is marked as a special module, then All connections are preserved. In practice, The number is very small, usually not more than 10. (6) At this point, the screening has been completed. For the generated data flow diagram, the points in the diagram that represent i / o in the original case are recorded as pi and po. Pi has only output, and po has only input. The two are used as the starting point and end point of the diagram. (7) Triggering from pi, recursively find the longest connection chain to po. It is easy to find that this chain must exist, and the number is >= 1. At this time, after place&routing (component position placement and connection between each other) for the modified diagram, you can get a clear visual schematic diagram containing only key information, allowing users to quickly find key points. (8) Finally, use the corresponding tools (such as FlowView, etc.) to display the processed data flow diagram.

[0067] As can be seen from the above, the disclosure provided by the embodiment of the present application provides a method for making a data flow graph. The disclosure first determines the components in the chip design layout, counts the number of connections of the components as output terminals or input terminals, screens the number of connections, retains the more important data streams with more connections, and removes the data streams with fewer connections; then, reversely screens the remaining data streams again to prevent missing reverse data streams, and finally draws a data flow graph based on the results after two screenings, so that the critical path in the EDA data flow graph can be clearly highlighted in this way, helping users to quickly and accurately grasp the key points in the data flow graph, accurately identify critical paths and potential performance bottlenecks, thereby significantly improving the efficiency and accuracy of data analysis and design decisions.

[0068] It should be noted that the method of the embodiment of the present disclosure can be performed by a single device, such as a computer or a server. The method of the embodiment of the present disclosure can also be applied in a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present disclosure, and the multiple devices will interact with each other to complete the described method.

[0069] It should be noted that the above is a description of a specific embodiment of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0070] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a non-volatile computer-readable storage medium containing a computer program, wherein the non-volatile computer-readable storage medium containing a computer program stores computer instructions, and the computer instructions are used to enable the computer to execute method 400 described in any of the above embodiments.

[0071] The computer-readable storage medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0072] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the method 400 described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0073] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a computer program product, which includes a computer program. In some embodiments, the computer program is executable by one or more processors so that the processors execute the described method 400. Corresponding to the execution subject corresponding to each step in each embodiment of the method 400, the processor that executes the corresponding step may belong to the corresponding execution subject.

[0074] The computer program product of the above embodiment is used to enable the processor to execute the method 400 described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0075] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0076] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power / ground connections to the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device may be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0077] Although the present application has been described in conjunction with specific embodiments of the present application, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the discussed embodiments.

[0078] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A method for making a data flow graph, characterized in that: include: Obtain chip design layout; According to the chip design layout, determining at least one first connection number using any element as an output end, and at least one second connection number using any element as an input end; wherein the output end and the input end are different elements; Screening the at least one first connection number and the at least one second connection number respectively according to a set threshold, and retaining the first data flow corresponding to the first connection number or the second connection number that passes the screening; swapping the output end and the input end of the first data stream, and re-screening the first data stream according to the set threshold value to determine a second data stream that passes the screening; The first data stream and the second data stream are output to produce a data flow graph according to the first data stream and the second data stream.

2. The method according to claim 1, characterized in that Before determining at least one first connection number in which any element is an output terminal, the method further includes: Determining at least one data flow in the chip design layout; Segmenting the at least one data stream into data segments to generate at least one data segment; wherein the data segment is a result of segmenting the at least one data stream based on an element, and the data segment only includes one element as an output end and one element as an input end; Statistics of the at least one first connection number and the at least one second connection number are performed using the at least one data segment.

3. The method according to claim 2, characterized in that The determining of at least one first connection number with any element as an output terminal and at least one second connection number with any element as an input terminal comprises: For any of the components as output ends, respectively counting the number of data segments of other different components as input ends, so as to generate the at least one first connection number; For any of the components as input ends, the number of data segments of other different components as output ends is counted respectively, so as to generate the at least one second connection number.

4. The method according to claim 2, characterized in that: The determining of at least one data stream in the chip design layout includes: Determine the target area in the chip design layout; Statistics are collected on the data flows in the target area to determine the at least one data flow.

5. The method according to claim 1, characterized in that The screening of the at least one first connection number according to the set threshold comprises: Determine a first maximum value among the at least one first connection number, and determine a first value that passes screening according to the first maximum value and the set threshold; Determine whether the at least one first connection number is greater than or equal to the first value and passes the screening.

6. The method according to claim 1, characterized in that The screening of the at least one second connection number according to the set threshold comprises: Determine a second maximum value among the at least one second connection number, and determine a second value that passes screening according to the second maximum value and the set threshold; Determine whether the at least one second connection number is greater than or equal to the second value and passes the screening.

7. The method according to claim 1, characterized in that Before outputting the first data stream and the second data stream, the method further includes: Determine whether there is a specified component in the chip design layout; In response to the existence of the designated element, all data streams having the designated element as an input terminal or an output terminal are reserved and merged with the first data stream and / or the second data stream.

8. The method according to claim 1, characterized in that After outputting the first data stream and the second data stream, the method further includes: A data flow graph is generated according to the first data flow and the second data flow, and the number of connections between adjacent elements is indicated in the data flow graph; wherein adjacent elements are adjacent elements in any data flow in the data flow graph.

9. The method according to claim 8, characterized in that The generating of the data flow graph comprises: According to the first data flow and the second data flow, the total input end and the total output end of the data flow graph are determined, and the total input end and the total output end are marked at the set position of the data flow graph.

10. A computer device comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to any one of claims 1 to 9.

11. A non-volatile computer-readable storage medium containing a computer program, which, when executed by one or more processors, causes the processors to perform the method of any one of claims 1 to 9.

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