Chip packaging structure

Abstract

The present application provides a chip packaging structure, including a first heat-conducting layer, a second heat-conducting layer, a sealing layer, and metal leads electrically connected to the wafer layer. The first heat-conducting layer wraps the wafer layer, the thickness of the wafer layer is 0.4-0.6mm, and the thickness of the first heat-conducting layer is 0.08-0.12mm; the second heat-conducting layer does not completely wrap the first heat-conducting layer, and the area covered by the second heat-conducting layer is greater than 90% of the area of ​​the first heat-conducting layer itself, and the thickness of the second heat-conducting layer is 0.18-0.22mm; the thermal conductivity of the second heat-conducting layer is greater than the thermal conductivity of the first heat-conducting layer; the thickness of the sealing layer is 0.2-0.4mm. Furthermore, the first heat-conducting layer includes a first upper heat-conducting layer and a first lower heat-conducting layer of unequal thicknesses, which improves the heat dissipation efficiency from the wafer layer to the first heat-conducting layer, thereby improving the heat dissipation effect of the chip packaging structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure. Background Art

[0002] Currently, high-power chip packaging devices can be used in aerospace, microwave communications, electronic components and other fields. As devices develop towards multifunctional integration, miniaturization and lightweight, traditional chip packaging is difficult to meet the reliability requirements of current devices.

[0003] The traditional chip packaging process is to install the shell of semiconductor integrated circuit chips, which plays the role of placing, fixing, sealing, protecting the chip and enhancing the electrical and thermal performance. The chip packaging is divided into wafer cutting, patching, wire bonding, injection molding, packaging and testing. Figure 1 As shown in the figure, after the metal leads are sealed with epoxy resin during injection molding, the heat dissipation of the chip wafer layer 01 is mainly concentrated in the epoxy resin part 02 and the lead metal part 03. However, since the area of ​​the lead metal part 03 is too small, the heat dissipation is mainly concentrated in the epoxy resin part 02. Since the thermal conductivity of epoxy resin is only 0.21W / (m·K), relying solely on the epoxy resin part 02 and the lead metal part 03 for heat dissipation is far from meeting the heat dissipation requirements of high-power chip packaging devices. Summary of the Invention

[0004] In view of this, the present application provides a chip packaging structure, comprising a first heat-conducting layer, a second heat-conducting layer, a sealing layer, and metal leads electrically connected to the wafer layer. On the one hand, the first heat-conducting layer completely wraps the wafer layer, so that the heat in the wafer layer is transferred out through the first heat-conducting layer at the first time. On the other hand, a second heat-conducting layer with a higher thermal conductivity is arranged outside the first heat-conducting layer, which can further quickly transfer the heat out, and the provision of the sealing layer can insulate the metal leads. Therefore, compared with the prior art, the heat dissipation area of ​​the chip packaging structure involved in the present application is greatly increased, and the heat dissipation effect is significantly enhanced.

[0005] The technical solutions provided in this application are as follows:

[0006] In a set of embodiments of the present application, a chip packaging structure is provided, comprising: a first heat-conducting layer, a second heat-conducting layer, a sealing layer, and metal leads electrically connected to the wafer layer, disposed on the periphery of the wafer layer;

[0007] Viewed from a cross section of the chip packaging structure, the first heat-conducting layer wraps the wafer layer, and the thickness T1 of the wafer layer is 0.4-0.6 mm;

[0008] The first heat-conducting layer includes a first upper heat-conducting layer and a first lower heat-conducting layer; the metal lead is connected to the wafer layer and is led out from the position where the first upper heat-conducting layer and the first lower heat-conducting layer contact each other, and the thickness T2 of the first heat-conducting layer is 0.08-0.12 mm;

[0009] The second heat-conducting layer does not completely wrap the first heat-conducting layer, and the area covered by the second heat-conducting layer is greater than 90% of the area of ​​the first heat-conducting layer itself, and the thickness T3 of the second heat-conducting layer is 0.18-0.22 mm;

[0010] The sealing layer is filled in the position where the second heat-conducting layer does not completely cover the first heat-conducting layer, the thickness T4 of the sealing layer is 0.2-0.4 mm, and the diameter of the metal lead is 0.08-0.12 mm;

[0011] The thermal conductivity of the second heat-conducting layer is greater than the thermal conductivity of the first heat-conducting layer, and the absolute value of the difference between the thermal expansion coefficient of the first heat-conducting layer and the thermal expansion coefficient of the wafer layer is smaller than the absolute value of the difference between the thermal expansion coefficient of the second heat-conducting layer and the thermal expansion coefficient of the wafer layer.

[0012] In one embodiment, the first upper heat-conducting layer includes a first upper main body portion and two first upper wrapping portions provided on both sides of the first upper main body portion. The first upper heat-conducting layer is integrally formed. The length of the first upper main body portion is equal to the length of the wafer layer. The length L1 of the first upper wrapping portion is 0.08-0.12 mm.

[0013] The first lower heat-conducting layer includes a first lower main body part and two first lower wrapping parts respectively arranged on both sides of the first lower main body part. The first lower heat-conducting layer is integrally formed, and the length of the first lower main body part is equal to the length of the wafer layer; the length L1 of the first lower wrapping part is 0.08-0.12mm.

[0014] In one embodiment, the surface of the first heat-conducting layer away from the wafer layer further includes: two filling layers, the two filling layers being a first filling layer and a second filling layer; the first filling layer being arranged above the first upper heat-conducting layer, the second filling layer being arranged below the first lower heat-conducting layer, and the filling layers being in contact with the first heat-conducting layer and the second heat-conducting layer, respectively, and the length of the filling layer being L2, L0<L2<(L0+2*L1);

[0015] The first heat-conducting layer includes a total of four retaining wall structures, which are respectively arranged on the two first upper wrapping parts and the two first lower wrapping parts, and the filling layer is fully in contact with the first upper main body part and the first lower main body part respectively. The retaining wall structure is used to limit the material of the filling layer between the first heat-conducting layer and the second heat-conducting layer.

[0016] In one embodiment, the chip packaging structure further includes: two first insertion layers, respectively disposed in the first upper heat conducting layer and the first lower heat conducting layer;

[0017] The thermal conductivity of the first insertion layer is greater than that of the first heat-conducting layer, the thickness of the first insertion layer is T5, 0.25*T2≤T5≤0.3*T2, and the vertical distance from the first insertion layer to the wafer layer is less than the vertical distance from the first insertion layer to the second heat-conducting layer.

[0018] In one embodiment, the second heat-conducting layer includes: a second upper heat-conducting layer in contact with the first upper heat-conducting layer and a second lower heat-conducting layer in contact with the first lower heat-conducting layer;

[0019] The thermal conductivity of the first insertion layer is equal to the thermal conductivity of the second heat conducting layer;

[0020] The chip packaging structure further includes: four first through-holes, wherein two of the first through-holes are respectively provided on the first upper heat-conducting layer, and one end of the two first through-holes is respectively connected to the second upper heat-conducting layer, and the other end of the two first through-holes is respectively connected to the first insertion layer provided on the first upper heat-conducting layer;

[0021] The other two first through-holes are respectively arranged in the first lower heat conducting layer, and one ends of the other two first through-holes are respectively connected to the second lower heat conducting layer, and the other ends of the other two first through-holes are respectively connected to the first insertion layer arranged in the first lower heat conducting layer.

[0022] In one embodiment, the chip packaging structure further includes: two second insertion layers, respectively disposed in the second upper heat conducting layer and the second lower heat conducting layer;

[0023] The thermal conductivity of the second insertion layer is greater than the thermal conductivity of the second heat-conducting layer, the length of the second insertion layer is L3, the length of the second heat-conducting layer is L4, (L0+2*L1)<L3<L4; the thickness of the second insertion layer is T6, 0.25*T3≤T6≤0.3*T3, and the vertical distance from the second insertion layer to the first heat-conducting layer is less than the vertical distance from the second insertion layer to the outer edge of the second heat-conducting layer.

[0024] In one embodiment, the chip packaging structure further includes: four second through-holes, wherein two of the second through-holes are respectively provided on the second upper heat-conducting layer, and one end of the two second through-holes is respectively connected to the outer surface of the entire chip packaging structure through the second upper heat-conducting layer, and the other end of the two second through-holes is respectively connected to the second insertion layer provided on the second upper heat-conducting layer;

[0025] The other two second through-holes are respectively arranged on the second lower heat-conducting layer, and one ends of the other two second through-holes are respectively connected to the outer surface of the entire chip packaging structure through the second lower heat-conducting layer, and the other ends of the other two second through-holes are respectively connected to the second insertion layer arranged on the second lower heat-conducting layer.

[0026] In another set of embodiments of the present application, a chip packaging structure is provided, comprising: a first heat-conducting layer, a second heat-conducting layer, a sealing layer, and metal leads electrically connected to the wafer layer, disposed on the periphery of the wafer layer;

[0027] Viewed from a cross section of the chip packaging structure, the first heat-conducting layer wraps the wafer layer, and the thickness T1 of the wafer layer is 0.4-0.6 mm;

[0028] The first heat-conducting layer includes a first upper heat-conducting layer and a first lower heat-conducting layer; the metal lead is connected to the wafer layer and is led out from a position where the first upper heat-conducting layer and the first lower heat-conducting layer contact each other; the thickness of the first upper heat-conducting layer is T21, the thickness of the first lower heat-conducting layer is T22, T22>T21, and the thickness T21 of the first heat-conducting layer is 0.08-0.12 mm;

[0029] The second heat-conducting layer does not completely wrap the first heat-conducting layer, and the area covered by the second heat-conducting layer is greater than 90% of the area of ​​the first heat-conducting layer itself, and the thickness T3 of the second heat-conducting layer is 0.18-0.22 mm;

[0030] The sealing layer is filled in the position where the second heat-conducting layer does not completely cover the first heat-conducting layer, the thickness T4 of the sealing layer is 0.18-0.22 mm, and the diameter of the metal lead is 0.08-0.12 mm;

[0031] The thermal conductivity of the second heat-conducting layer is greater than the thermal conductivity of the first heat-conducting layer, and the absolute value of the difference between the thermal expansion coefficient of the first heat-conducting layer and the thermal expansion coefficient of the wafer layer is smaller than the absolute value of the difference between the thermal expansion coefficient of the second heat-conducting layer and the thermal expansion coefficient of the wafer layer.

[0032] In one embodiment, the second heat-conducting layer includes: a second upper heat-conducting layer in contact with the first upper heat-conducting layer and a second lower heat-conducting layer in contact with the first lower heat-conducting layer, the second upper heat-conducting layer has a thickness of T31, the second lower heat-conducting layer has a thickness of T32, T31>T32, and T32 is 0.08-0.12 mm;

[0033] The chip packaging structure includes:

[0034] a first insertion layer, disposed on the first lower heat-conducting layer, wherein the thermal conductivity of the first insertion layer is greater than the thermal conductivity of the first heat-conducting layer, the thickness of the first insertion layer is T5, 0.25*T22≤T5≤0.3*T22, and the vertical distance from the first insertion layer to the wafer layer is less than the vertical distance from the first insertion layer to the second heat-conducting layer;

[0035] Two first through-holes are provided on both sides of the first insertion layer in the length direction of the first insertion layer, the two first through-holes are respectively provided in the first lower heat-conducting layer, and one end of the two first through-holes is respectively connected to the second lower heat-conducting layer, and the other end of the two first through-holes is respectively connected to the first insertion layer;

[0036] a second insertion layer disposed on the second upper heat-conducting layer, wherein the thermal conductivity of the second insertion layer is greater than the thermal conductivity of the second heat-conducting layer, the thickness of the second insertion layer is T6, 0.25*T31≤T6≤0.3*T31, and the vertical distance from the second insertion layer to the first heat-conducting layer is less than the vertical distance from the second insertion layer to the outer edge of the second heat-conducting layer; and

[0037] The second through-holes are arranged on both sides of the second insertion layer in the length direction of the second insertion layer, and the two second through-holes are respectively arranged in the second upper heat-conducting layer, and one end of the two second through-holes is respectively connected to the second upper heat-conducting layer, and the other end of the two second through-holes is respectively connected to the second insertion layer.

[0038] In one embodiment, the first upper heat-conducting layer includes a first upper main body portion and two first upper wrapping portions provided on both sides of the first upper main body portion. The first upper heat-conducting layer is integrally formed. The length of the first upper main body portion is equal to the length of the wafer layer. The length L1 of the first upper wrapping portion is 0.08-0.12 mm.

[0039] The first lower heat-conducting layer includes a first lower main body portion and two first lower wrapping portions provided on both sides of the first lower main body portion. The first lower heat-conducting layer is integrally formed. The length of the first lower main body portion is equal to the length of the wafer layer. The length L1 of the first lower wrapping portion is 0.08-0.12 mm.

[0040] The area of ​​each of the first lower wrapping parts is greater than the area of ​​each of the first upper wrapping parts.

[0041] In one embodiment, the surface of the first heat-conducting layer away from the wafer layer further includes: two filling layers, the two filling layers being a first filling layer and a second filling layer; the first filling layer being arranged above the first upper heat-conducting layer, the second filling layer being arranged below the first lower heat-conducting layer, and the filling layers being in contact with the first heat-conducting layer and the second heat-conducting layer, respectively, and the length of the filling layer being L2, L0<L2<(L0+2*L1);

[0042] The first heat-conducting layer includes a total of four retaining wall structures, which are respectively arranged on the two first upper wrapping parts and the two first lower wrapping parts, and the filling layer is fully in contact with the first upper main body part and the first lower main body part respectively. The retaining wall structure is used to limit the material of the filling layer between the first heat-conducting layer and the second heat-conducting layer.

[0043] In one embodiment, the chip packaging structure further includes: two first insertion layers, respectively disposed in the first upper heat conducting layer and the first lower heat conducting layer;

[0044] The thermal conductivity of the first insertion layer is greater than that of the first heat-conducting layer, the thickness of the first insertion layer is T5, 0.25*T21≤T5≤0.3*T21, and the vertical distance from the first insertion layer to the wafer layer is less than the vertical distance from the first insertion layer to the second heat-conducting layer.

[0045] In one embodiment, the second heat-conducting layer includes: a second upper heat-conducting layer in contact with the first upper heat-conducting layer and a second lower heat-conducting layer in contact with the first lower heat-conducting layer, the second upper heat-conducting layer has a thickness of T31, the second lower heat-conducting layer has a thickness of T32, and T31>T32;

[0046] The thermal conductivity of the first insertion layer is equal to the thermal conductivity of the second heat conducting layer;

[0047] The chip packaging structure further includes: four first through-holes, wherein two of the first through-holes are respectively provided on the first upper heat-conducting layer, and one end of the two first through-holes is respectively connected to the second upper heat-conducting layer, and the other end of the two first through-holes is respectively connected to the first insertion layer provided on the first upper heat-conducting layer;

[0048] The other two first through-holes are respectively arranged in the first lower heat conducting layer, and one ends of the other two first through-holes are respectively connected to the second lower heat conducting layer, and the other ends of the other two first through-holes are respectively connected to the first insertion layer arranged in the first lower heat conducting layer.

[0049] In one embodiment, the chip packaging structure further includes: two second insertion layers, respectively disposed in the second upper heat conducting layer and the second lower heat conducting layer;

[0050] The thermal conductivity of the second insertion layer is greater than the thermal conductivity of the second heat-conducting layer, the length of the second insertion layer is L3, the length of the second heat-conducting layer is L4, (L0+2*L1)<L3<L4; the thickness of the second insertion layer is T6, 0.25*T32≤T6≤0.3*T32, and the vertical distance from the second insertion layer to the first heat-conducting layer is less than the vertical distance from the second insertion layer to the outer edge of the second heat-conducting layer.

[0051] In one embodiment, the chip packaging structure further includes:

[0052] The chip packaging structure further includes: four second through-holes, wherein two of the second through-holes are respectively provided on the second upper heat-conducting layer, and one end of the two second through-holes is respectively connected to the outer surface of the entire chip packaging structure through the second upper heat-conducting layer, and the other end of the two second through-holes is respectively connected to the second insertion layer provided on the second upper heat-conducting layer;

[0053] The other two second through-holes are respectively arranged on the second lower heat-conducting layer, and one ends of the other two second through-holes are respectively connected to the outer surface of the entire chip packaging structure through the second lower heat-conducting layer, and the other ends of the other two second through-holes are respectively connected to the second insertion layer arranged on the second lower heat-conducting layer.

[0054] In one embodiment, the second heat-conducting layer is a ceramic material;

[0055] The chip packaging structure further includes: a metal heat sink and a heat dissipation metal lead connected to the metal heat sink; the metal heat sink is arranged outside the second heat conducting layer, and the wafer layer is insulated from the metal heat sink; the heat dissipation metal lead is connected to the metal lead.

[0056] Beneficial effect: In one embodiment of the present application, a chip packaging structure is provided, comprising a first heat-conducting layer, a second heat-conducting layer, a sealing layer, and metal leads electrically connected to the wafer layer. The first heat-conducting layer wraps the wafer layer, the thickness T1 of the wafer layer is 0.4-0.6mm, and the thickness T2 of the first heat-conducting layer is 0.08-0.12mm; the second heat-conducting layer does not completely wrap the first heat-conducting layer, and the area covered by the second heat-conducting layer is greater than 90% of the area of ​​the first heat-conducting layer itself, and the thickness T3 of the second heat-conducting layer is 0.18-0.22mm; the thermal conductivity of the second heat-conducting layer is greater than the thermal conductivity of the first heat-conducting layer; the thickness T4 of the sealing layer is 0.2-0.4mm. The special structural size design of the above-mentioned film layers, the special thermal conductivity gradient design, and the special thermal expansion coefficient design, the combined effect can improve the overall heat dissipation effect of the chip packaging structure. Specifically, on the one hand, the first heat-conducting layer completely wraps the wafer layer, so that the heat in the wafer layer is transferred out through the first heat-conducting layer in a timely manner. The first heat-conducting layer can be set to high thermal conductivity silicone and high thermal conductivity material. On the other hand, a second heat-conducting layer with a higher thermal conductivity coefficient is set outside the first heat-conducting layer to further transfer the heat in the first heat-conducting layer to the outside away from the wafer layer. The second heat-conducting layer can be set to metal or ceramic to prevent aging of the first heat-conducting layer. In addition, a partial gap is set when the second heat-conducting layer surrounds the first heat-conducting layer, and the gap is filled by a sealing layer. The sealing layer can be set to a material such as epoxy resin. The sealing layer can seal the metal lead to achieve insulation between the wafer layer and the second heat-conducting layer. Compared with the prior art, the heat dissipation area of ​​the chip packaging structure involved in this application is greatly increased, and the heat dissipation effect is significantly enhanced. Furthermore, the first heat-conducting layer includes a first upper heat-conducting layer and a first lower heat-conducting layer of different thicknesses, and the thickness T22 of the first lower heat-conducting layer is greater than the thickness T21 of the first upper heat-conducting layer, thereby improving the heat dissipation efficiency from the wafer layer to the first heat-conducting layer, thereby improving the heat dissipation effect of the chip packaging structure.

[0057] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 A schematic diagram of a chip packaging structure provided in the prior art;

[0060] Figure 2 A first schematic diagram of a chip packaging structure provided by the first group of embodiments of the present application;

[0061] Figure 3 A second schematic diagram of the chip packaging structure provided by the first group of embodiments of the present application;

[0062] Figure 4 A third schematic diagram of the chip packaging structure provided in the first group of embodiments of the present application;

[0063] Figure 5 A fourth schematic diagram of the chip packaging structure provided in the first group of embodiments of the present application;

[0064] Figure 6 A fifth schematic diagram of the chip packaging structure provided in the first group of embodiments of the present application;

[0065] Figure 7 A sixth schematic diagram of the chip packaging structure provided in the first group of embodiments of the present application;

[0066] Figure 8 A seventh schematic diagram of the chip packaging structure provided in the first group of embodiments of the present application;

[0067] Figure 9 An eighth schematic diagram of the chip packaging structure provided by the first group of embodiments of the present application;

[0068] Figure 10 A top view of the chip packaging structure provided by the first group of embodiments of the present application;

[0069] Figure 11 A first schematic diagram of a chip packaging structure provided in the second embodiment of the present application;

[0070] Figure 12 A second schematic diagram of a chip packaging structure provided in the second embodiment of the present application;

[0071] Figure 13 A third schematic diagram of a chip packaging structure provided in the second embodiment of the present application;

[0072] Figure 14 A fourth schematic diagram of a chip packaging structure provided in the second group of embodiments of the present application;

[0073] Figure 15 A fifth schematic diagram of a chip packaging structure provided in the second embodiment of the present application;

[0074] Figure 16 A sixth schematic diagram of a chip packaging structure provided in the second group of embodiments of the present application;

[0075] Figure 17 A seventh schematic diagram of a chip packaging structure provided in the second embodiment of the present application;

[0076] Figure 18 An eighth schematic diagram of a chip packaging structure provided in the second group of embodiments of the present application;

[0077] Figure 19 Graphs showing the relationship between chip surface temperature and time for five chip packaging structures in the prior art and this application.

[0078] Reference numerals:

[0079] Chip wafer layer 01, epoxy resin part 02, lead metal part 03, heat sink 04.

[0080] Chip packaging structure 100:

[0081] Wafer layer 10, metal lead 11, first heat conducting layer 12, second heat conducting layer 13, sealing layer 14, filling layer 15, first filling layer 151, second filling layer 152, metal heat sink 16, heat dissipation metal lead 17;

[0082] A first upper heat-conducting layer 121, a first upper main body portion 121a, a first upper wrapping portion 121b, a first lower heat-conducting layer 122, a first lower main body portion 122a, a first lower wrapping portion 121b, a retaining wall structure 12a, a first insertion layer 12b, and a first through portion 12c;

[0083] The second upper heat conducting layer 131 , the second lower heat conducting layer 132 , the second insertion layer 13 a , and the second through portion 13 b . DETAILED DESCRIPTION

[0084] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the scope of protection of the present application.

[0085] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0086] See also Figure 2 In the first schematic diagram of the chip packaging structure 100 provided in the first group of embodiments of the present application, the chip packaging structure 100 includes: a wafer layer 10, a metal lead 11, a first heat-conducting layer 12, a second heat-conducting layer 13 and a sealing layer 14. The wafer layer 10 is connected to the metal lead 11. The wafer layer 10 can be a high-power chip. The shape of the wafer layer 10 is not limited. It can be a long strip or have an irregular structure. For example, the wafer layer 10 can be arched or have multiple protruding structures. The thickness of the wafer layer 10 is between 0.3 mm and 0.6 mm. Generally, the thickness T1 of a high-power chip is 0.5 mm.

[0087] like Figure 2 As shown, from a cross-section of the chip packaging structure 100, the first heat-conducting layer 12 wraps the wafer layer 10. The first heat-conducting layer 12 can be set as an insulating material. The first heat-conducting layer 12 can include a first upper heat-conducting layer 121 and a first lower heat-conducting layer 122. The first heat-conducting layer 12 can be integrally formed or formed in two steps. The first upper heat-conducting layer 121 and the first lower heat-conducting layer 122 are respectively arranged on the first surface and the second surface of the wafer layer 10, and the first surface and the second surface are two opposite surfaces of the wafer layer 10. The first heat-conducting layer 12 can be formed by dispensing, coating, liquid perfusion or thin film pressing. The specific shape of the first heat-conducting layer 12 is not limited and needs to be changed according to the change of the shape of the wafer layer 10. The thermal conductivity of the first heat-conducting layer 12 can be set at 6-13W / (m·K), and the thickness T2 of the first heat-conducting layer 12 can be set at 0.08mm-0.12mm, preferably it can be set to 0.1mm. The side length (L1) of the first heat-conducting layer 12 can be set to 0.08 mm-0.12 mm, preferably 0.1 mm. The first heat-conducting layer 12 can be made of heat-conducting silica gel.

[0088] The second heat-conducting layer 13 does not completely wrap the first heat-conducting layer 12, and the area covered by the second heat-conducting layer 13 on the first heat-conducting layer 12 is greater than 90% of the area of ​​the first heat-conducting layer 12 itself. The second heat-conducting layer 13 is made of a material that is more conducive to heat dissipation. The thermal conductivity of the second heat-conducting layer 13 can be set at 100-300 W / (m·K), and the thickness T3 of the second heat-conducting layer 13 can be set at 0.1mm-0.3mm, preferably can be set to 0.2mm. The second heat-conducting layer 13 can be made of metal or ceramic material. The second heat-conducting layer 13 includes a second upper heat-conducting layer and a second lower heat-conducting layer. The second heat-conducting layer 13 can be integrally formed or formed in two steps. The second upper heat-conducting layer is arranged on the side of the first upper heat-conducting layer 121 away from the wafer layer 10, and the second lower heat-conducting layer is arranged on the side of the first lower heat-conducting layer 122 away from the wafer layer 10. The second heat-conducting layer 13 can also be formed by dispensing, coating, liquid perfusion or sheet lamination.

[0089] The areas where the second thermally conductive layer 13 does not completely enclose the first thermally conductive layer 12 are filled with a sealing layer 14. The thickness T4 of the sealing layer 14 is 0.1-0.3 mm, preferably 0.2 mm. The diameter of the metal lead 11 is 0.08-0.12 mm, preferably 0.1 mm. The sealing layer 14 contacts the first thermally conductive layer 12, the second thermally conductive layer 13, and the metal lead 11, respectively. The sealing layer 14 is used to enclose the metal lead 11, ensuring that the metal lead 11 is sealed. The sealing layer 14 can be made of epoxy resin.

[0090] The thermal conductivity of the second heat-conducting layer 13 is greater than that of the first heat-conducting layer 12. Furthermore, the thermal expansion coefficients of the layers satisfy the following requirement: the absolute value of the difference between the thermal expansion coefficients of the first heat-conducting layer 12 and the wafer layer 10 is less than the absolute value of the difference between the thermal expansion coefficients of the second heat-conducting layer 13 and the wafer layer 10. As long as there is a temperature difference within an object or between objects, heat will spontaneously transfer from a higher temperature to a lower temperature.

[0091] In this embodiment, a heat-conducting structure consisting of a first heat-conducting layer 12 and a second heat-conducting layer 13 of a high thermal conductivity material is used, so that the heat in the wafer layer 10 can be transferred out stably and efficiently, significantly improving the heat dissipation efficiency of the chip. On the one hand, the first heat-conducting layer 12 completely wraps the wafer layer 10, so that the heat in the wafer layer 10 can be transferred out in time through the first heat-conducting layer 12. On the other hand, a second heat-conducting layer 13 with a higher thermal conductivity is provided outside the first heat-conducting layer 12 to further transfer the heat in the first heat-conducting layer 12 to a place away from the wafer layer 10. In addition, a partial gap is provided when the second heat-conducting layer 13 surrounds the first heat-conducting layer 12, and the gap is filled by a sealing layer 14. The sealing layer 14 can seal the metal lead 11 to achieve insulation between the wafer layer 10 and the outside world. Compared with the prior art, the heat dissipation area of ​​the chip packaging structure 100 involved in this application is greatly increased, and the heat dissipation effect is significantly enhanced. The heat dissipation effect of the chip packaging structure 100 is significantly enhanced, which can effectively improve the service life of the semiconductor chip 10.

[0092] See also Figure 3 In the second schematic diagram of the chip packaging structure 100 provided in the first group of embodiments of the present application, the first upper heat-conducting layer 121 includes a first upper main body portion 121a and two first upper wrapping portions 121b respectively provided on both sides of the first upper main body portion 121a. The first upper heat-conducting layer 121 is integrally formed. The length of the first upper main body portion 121a is equal to the length of the wafer layer 10 (the lengths are as shown in FIG. Figure 3 The length L1 of the first upper wrapping portion 121b is 0.08-0.12 mm, and preferably can be set to 0.1 mm.

[0093] The first lower heat conducting layer 122 includes a first lower main body portion 122a and two first lower wrapping portions 121b provided on both sides of the first lower main body portion 122a. The first lower heat conducting layer 122 is formed as a whole. The length of the first lower main body portion 122a is equal to the length of the wafer layer 10 (the lengths are both as shown in FIG. Figure 3 The length L1 of the first lower wrapping portion 121b is 0.08-0.12 mm, and preferably can be set to 0.1 mm.

[0094] In this embodiment, the specific structures of the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122 are further defined. The heat-conducting layers formed integrally can simplify the preparation process of the chip packaging structure 100. The specific structural dimensions of the heat-conducting layers can be closer to the specific structure of the wafer layer 10, and the sealing of the metal lead 11 can also be better achieved.

[0095] See also Figure 4 In the third schematic diagram of the chip packaging structure 100 provided in the first group of embodiments of the present application, the surface of the first heat-conducting layer 12 away from the wafer layer 10 also includes: two filling layers. The material of the filling layer can be thermal grease. The two filling layers are the first filling layer 151 and the second filling layer 152; the first filling layer 151 is arranged on the first upper heat-conducting layer 121, and the second filling layer 152 is arranged below the first lower heat-conducting layer 122. (The filling layer mentioned below can be understood as the first filling layer 151 and / or the second filling layer 152.) And the filling layer is in contact with the first heat-conducting layer 12 and the second heat-conducting layer 13 respectively, and the length of the filling layer is L2, L0<L2<(L0+2*L1). The projection of the filling layer onto the wafer layer 10 covers the entire length of the wafer layer 10. The center of the wafer layer 10 in the length direction is on the same straight line as the center of the filling layer in the length direction. The thickness of the filling layer is <0.35*T2.

[0096] The first heat-conducting layer 12 includes a total of four retaining wall structures 12a. The retaining wall structure 12a includes a protruding retaining angle, which can be an acute angle or a right angle. The retaining wall structure 12a can be formed by grooving the first heat-conducting layer 12. The thickness of the retaining wall structure 12a can be equal to 1 / 2 of the thickness of the filling layer. The retaining wall structure 12a is respectively arranged on the two first upper wrapping parts 121b and the two first lower wrapping parts 121b, and the filling layer is respectively in full contact with the first upper main body part 121a and the first lower main body part 122a. The retaining wall structure 12a is used to limit the material of the filling layer between the first heat-conducting layer 12 and the second heat-conducting layer 13.

[0097] In this embodiment, the chip packaging structure 100 provided further includes a filling layer and a retaining wall structure 12a. When the first heat-conducting layer 12 is a thermally conductive silicone, there are gaps on the surface of the thermally conductive silicone, that is, the holes, cracks, or protrusions on the surface of the silicone affect the surface morphology and performance. In this embodiment, the setting of the filling layer (silicone grease) can fill the surface gaps of the thermally conductive silicone (first heat-conducting layer 12). In addition, due to the extrusion phenomenon and thixotropy of the thermally conductive silicone grease, the filling layer (thermal conductive silicone grease) needs to be limited by the retaining wall structure 12a, and further completely wrapped by the first heat-conducting layer 12 and the second heat-conducting layer 13.

[0098] During the installation of the filling layer and retaining wall structure 12a, it is important to note that the filling layer is primarily positioned at the corresponding location on the wafer layer 10. The length L1 of the first thermally conductive layer 12 on the left and right sides of the wafer layer 10 can be appropriately widened to ensure sufficient contact area between the filling layer and the first upper thermally conductive layer 121. The use of thermally conductive silicone grease in the filling layer ensures good contact with the metal or ceramic of the second thermally conductive layer 13, preventing deformation. Furthermore, the overall thickness of the chip package structure 100 is extremely thin.

[0099] The preparation process for the filling layer and retaining wall structure 12a includes: grooving the first thermally conductive layer 12 to form the retaining wall structure 12a. Annealing the first thermally conductive layer 12 at a relatively high temperature to form the filling layer (thermal grease), ensuring close and stable contact between the thermally conductive silicone and the thermally conductive grease. The temperature during the filling layer formation should be kept low, generally below 150°C.

[0100] See also Figure 5 In the fourth schematic diagram of the chip packaging structure 100 provided in the first group of embodiments of the present application, the chip packaging structure 100 further includes: two first insertion layers 12b, which are respectively arranged in the first upper heat conducting layer 121 and the first lower heat conducting layer 122.

[0101] The thermal conductivity of the first insertion layer 12b is greater than that of the first thermally conductive layer 12. The thickness of the first insertion layer 12b is T5, and 0.25*T2≤T5≤0.3*T2. The first insertion layer 12b is located in the half of the first thermally conductive layer 12 closer to the wafer layer 10. The vertical distance from the first insertion layer 12b to the wafer layer 10 is less than the vertical distance from the first insertion layer 12b to the second thermally conductive layer 13. If the first thermally conductive layer 12 is evenly cut along a direction perpendicular to the thickness, the first insertion layer 12b is located in the half of the first thermally conductive layer 12 closer to the wafer layer 10.

[0102] In this embodiment, a first insertion layer 12b with a higher thermal conductivity is inserted into the first thermally conductive layer 12. Specifically, a material with a higher thermal conductivity, such as metal particles or metal flakes, can be added to the thermally conductive silicone layer to increase heat dissipation. Specifically, the first insertion layer 12b can reduce the thermal resistance of the first thermally conductive layer 12, thereby accelerating heat dissipation from the overall chip package structure 100 and improving the heat dissipation efficiency of the high-power chip package structure.

[0103] See also Figure 6 In the fifth schematic diagram of the chip package structure 100 provided in the first group of embodiments of the present application, the second heat-conducting layer 13 includes a second upper heat-conducting layer 131 in contact with the first upper heat-conducting layer 121 and a second lower heat-conducting layer 132 in contact with the first lower heat-conducting layer 122. The thermal conductivity of the first insertion layer 12b is equal to the thermal conductivity of the second heat-conducting layer 13. The material of the first insertion layer 12b can be the same as that of the second heat-conducting layer 13.

[0104] The chip packaging structure 100 also includes: four first through-hole portions 12c, wherein two first through-hole portions 12c are respectively arranged on the first upper heat-conducting layer 121, and one end of the two first through-hole portions 12c are respectively connected to the second upper heat-conducting layer 131, and the other end of the two first through-hole portions 12c are respectively connected to the first insertion layer 12b arranged on the first upper heat-conducting layer 121.

[0105] The other two first through-holes 12c are respectively arranged on the first lower heat-conducting layer 122, and one ends of the other two first through-holes 12c are respectively connected to the second lower heat-conducting layer 132, and the other ends of the other two first through-holes 12c are respectively connected to the first insertion layer 12b arranged on the first lower heat-conducting layer 122.

[0106] In this embodiment, the addition of the first through portion 12c can more conveniently conduct heat accumulated in the first heat-conducting layer 12 to the second heat-conducting layer 13. The heat in the first heat-conducting layer 12 can be quickly conducted to the second heat-conducting layer 13 along the first through portion 12c, thereby improving the heat conduction effect.

[0107] See also Figure 7 In the sixth schematic diagram of the chip packaging structure 100 provided in the first group of embodiments of the present application, the chip packaging structure 100 further includes: two second insertion layers 13a, which are respectively arranged in the second upper heat conducting layer 131 and the second lower heat conducting layer 132.

[0108] The thermal conductivity of the second insertion layer 13a is greater than that of the second heat-conducting layer 13. The length of the second insertion layer 13a is L3, and the length of the second heat-conducting layer 13 is L4, where (L0+2*L1)<L3<L4. The projection of the second insertion layer 13a onto the wafer layer 10 covers the entire length of the wafer layer 10. The center of the wafer layer 10 in the length direction is on the same straight line as the center of the second insertion layer 13a in the length direction. The thickness of the second insertion layer 13a is T6, where 0.25*T3≤T6≤0.3*T3. The second insertion layer 13a is located within the 1 / 2 position closer to the first heat-conducting layer 12. The vertical distance from the second insertion layer 13a to the first heat-conducting layer 12 is less than the vertical distance from the second insertion layer 13a to the outer edge of the second heat-conducting layer 13. If the second heat-conducting layer 13 is evenly cut in a direction perpendicular to the thickness direction, the second insertion layer 13a is located in the half of the second heat-conducting layer 13 closer to the first heat-conducting layer 12.

[0109] In this embodiment, a second insertion layer 13a with higher thermal conductivity is inserted into the second thermally conductive layer 13. Specifically, a graphene material with higher thermal conductivity can be added to the metal layer as the second insertion layer to improve heat dissipation. Specifically, the second insertion layer 13a can reduce the thermal resistance of the second thermally conductive layer 13, thereby accelerating the heat dissipation of the overall chip package structure 100 and improving the heat dissipation efficiency of the high-power chip package structure.

[0110] See also Figure 8 In the seventh schematic diagram of the chip packaging structure 100 provided in the first group of embodiments of the present application, the chip packaging structure 100 further includes: four second through-holes 13b, wherein two second through-holes 13b are respectively arranged on the second upper heat-conducting layer 131, and one end of the two second through-holes 13b is respectively connected to the outer surface of the entire chip packaging structure 100 through the second upper heat-conducting layer 131, and the other ends of the two second through-holes 13b are respectively connected to the second insertion layer 13a arranged on the second upper heat-conducting layer 131.

[0111] The other two second through-holes 13b are respectively arranged on the second lower heat-conducting layer 132, and one ends of the other two second through-holes 13b are respectively connected to the outer surface of the entire chip packaging structure 100 through the second lower heat-conducting layer 132, and the other ends of the other two second through-holes 13b are respectively connected to the second insertion layer 13a arranged on the second lower heat-conducting layer 132.

[0112] In this embodiment, the second through-hole 13b is added to more conveniently conduct heat accumulated in the second heat-conducting layer 13 to a location away from the wafer layer 10. The heat in the second heat-conducting layer 13 can be quickly conducted away from the wafer layer 10 along the second through-hole 13b, thereby improving the heat conduction effect.

[0113] See also Figure 9In the eighth schematic diagram of the chip packaging structure 100 provided in the first group of embodiments of the present application, the second heat conducting layer 13 is made of ceramic material. Figure 9 The chip package structure 100 shown in FIG. 1 further includes a metal heat sink 16 and heat dissipation metal leads 17 connected to the metal heat sink 16. The metal heat sink 16 is disposed outside the second thermally conductive layer 13, and the wafer layer 10 is insulated from the metal heat sink 16. The heat dissipation metal leads 17 are connected to the metal leads 11.

[0114] In this embodiment, a metal heat sink 16 and a heat dissipation metal lead 17 are added, which can not only ensure the wire bonding of the wafer layer 10 (implemented by the metal lead 11), but also increase the heat dissipation area through the metal heat sink 16 and increase the heat dissipation path through the heat dissipation metal lead 17.

[0115] Figure 10 This is a top view of the chip packaging structure 100 provided in the first group of embodiments of the present application. Figure 10 Multiple metal heat sinks 16 are arranged at intervals (each metal heat sink 16 corresponds to a pin of the chip led out of the wafer layer 10), and multiple heat dissipation metal leads 17 are led out from the multiple metal heat sinks 16. Figure 10 In the top view of the chip package structure 100 , the metal heat sinks 16 are disconnected, thereby avoiding electrical connection between the chip pins.

[0116] See also Figure 11 In the first schematic diagram of the chip packaging structure 100 provided in the second group of embodiments of the present application, the chip packaging structure 100 includes: a first heat-conducting layer 12, a second heat-conducting layer 13, a sealing layer 14, and a metal lead 11 electrically connected to the wafer layer 10.

[0117] From a cross-section of the chip packaging structure 100, the first heat-conducting layer 12 wraps the wafer layer 10, and the thickness T1 of the wafer layer 10 is 0.4-0.6mm, preferably 0.5mm. The first heat-conducting layer 12 includes a first upper heat-conducting layer 121 and a first lower heat-conducting layer 122. The metal lead 11 is connected to the wafer layer 10 and is led out from the position where the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122 contact. The thickness of the first upper heat-conducting layer 121 is T21, and the thickness of the first lower heat-conducting layer 122 is T22, T22>T21, and the thickness T21 of the first heat-conducting layer 12 is 0.08-0.12mm, preferably 0.1mm. For example, in one embodiment, T21 is 0.08-0.12mm, preferably 0.1mm, and T22 is 0.2mm-0.3mm, preferably 0.24mm.

[0118] The second heat conducting layer 13 does not completely wrap the first heat conducting layer 12, and the area covered by the second heat conducting layer 13 is greater than 90% of the area of ​​the first heat conducting layer 12 itself, and the thickness T3 of the second heat conducting layer 13 is 0.18-0.22 mm, preferably can be set to 0.2 mm.

[0119] The portion where the second heat-conducting layer 13 does not completely enclose the first heat-conducting layer 12 is filled with a sealing layer 14. The thickness T4 of the sealing layer 14 is 0.18-0.22 mm, preferably 0.2 mm. The diameter of the metal lead 11 is 0.08-0.12 mm, preferably 0.1 mm. The thermal conductivity of the second heat-conducting layer 13 is greater than that of the first heat-conducting layer 12.

[0120] In this embodiment, the thicknesses of the first upper heat conducting layer 121 and the first lower heat conducting layer 122 on both sides of the wafer layer 10 are different, that is, Figure 11 T21≠T22 indicated in the figure, please refer to Figure 11 As shown, the thickness T21 of the first upper heat-conducting layer 121 is less than the thickness T22 of the first lower heat-conducting layer 122. The specific definition of the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122 is only provided for the purpose of distinction. In practical applications, the difference in thickness between the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122 is within the scope of protection of the embodiments of the present application. Figure 11 Rotating 180° in the plane, the thickness of the first upper heat-conducting layer is greater than the thickness of the first lower heat-conducting layer.

[0121] In the second set of embodiments of the present application, the inventors' calculations show that when T21 ≠ T22, the heat dissipation effect of the entire chip package structure 100 is more significant. This is specifically reflected in the following process: the thermal conductivity of the chip package structure 100 is calculated according to Q = KA * (dT / dx). Where Q is the heat flux, K is the thermal conductivity, A is the heat transfer area, dT represents the temperature difference between the two sides of the micro-element thickness, and dx represents the micro-element thickness.

[0122] The thickness from the wafer layer 10 to the upper surface of the first upper heat-conducting layer 121 is a, and the thickness from the wafer layer 10 to the lower surface of the first lower heat-conducting layer 122 is b. The total heat transferred outward by the wafer layer 10 is Qtotal = KA*(dT / a)+KA*(dT / b)=KAdT[(a+b) / ab]. The maximum value of Qtotal, that is, the maximum value of [(a+b) / ab], is when a+b is a constant value C and ab is minimum, and Qtotal is maximum. ab=a(Ca). Since a is a length value, Qtotal is maximum when a=0 or a=C. Therefore, when the first heat-conducting layers on both sides of the wafer layer are set asymmetrically (when T21≠T22, the heat dissipation effect of the entire chip packaging structure 100 is more obvious), the heat dissipation speed is faster. Specifically, it can be set to 1.5*T21=T22, 2*T21=T22, 2.5*T21=T22 or other multiple relationships.

[0123] In this embodiment, based on the first group of embodiments, the structure of the first heat-conducting layer 12 is further improved, thereby improving the heat dissipation efficiency from the wafer layer 10 to the first heat-conducting layer 12, thereby enhancing the heat dissipation effect of the chip packaging structure 100. Figure 19 The effect diagram shown. Figure 19 The figure shows the relationship between chip surface temperature and time for five chip packaging structures. Figure 1 The chip packaging structure shown is a solution adopted in the prior art, and its heat dissipation effect is poor. It can be clearly seen in the figure that after the chip is used for 8-9 minutes, the chip surface temperature will reach above 85℃ and remain at 80℃-90℃, which will seriously shorten the chip life and reduce the chip reliability. Figure 2 The symmetrical basic heat dissipation chip packaging structure shown, Figure 5 The symmetrical upgraded heat dissipation chip packaging structure shown, Figure 11 The asymmetric basic heat dissipation chip packaging structure shown and Figure 12 The asymmetric upgraded heat dissipation chip packaging structure shown has significantly improved heat dissipation. Specifically, the figure shows that after 4-5 minutes of use, the chip surface temperature reaches between 55°C and 65°C, and can be maintained at a relatively low temperature for a long time. This shows that the overall heat dissipation effect of the chip packaging structure formed using the technical solution of this application has been significantly enhanced.

[0124] See also Figure 12In the second schematic diagram of the chip package structure 100 provided in the second embodiment of the present application, the second heat-conducting layer 13 includes: a second upper heat-conducting layer 131 in contact with the first upper heat-conducting layer 121, and a second lower heat-conducting layer 132 in contact with the first lower heat-conducting layer 122. The second upper heat-conducting layer 131 has a thickness T31, and the second lower heat-conducting layer 132 has a thickness T32, where T31>T32. T32 is 0.08-0.12 mm, and can preferably be set to 0.1 mm. T32 is 0.2-0.3 mm, and can preferably be set to 0.26 mm. For example, in one embodiment, T32 is 0.1 mm, and T31 is 0.28 mm.

[0125] The chip packaging structure 100 includes: a first insertion layer 12b, which is arranged on the first lower heat-conducting layer 122, the thermal conductivity of the first insertion layer 12b is greater than the thermal conductivity of the first heat-conducting layer 12, the thickness of the first insertion layer 12b is T5, 0.25*T22≤T5≤0.3*T22, and the vertical distance from the first insertion layer 12b to the wafer layer 10 is less than the vertical distance from the first insertion layer 12b to the second heat-conducting layer 13.

[0126] The two first through-holes 12c are arranged on both sides of the first insertion layer 12b in the length direction of the first insertion layer 12b, and the two first through-holes 12c are respectively arranged in the first lower heat-conducting layer 122, and one end of the two first through-holes 12c is respectively connected to the second lower heat-conducting layer 132, and the other end of the two first through-holes 12c is respectively connected to the first insertion layer 12b.

[0127] The second insertion layer 13a is arranged on the second upper heat-conducting layer 131. The thermal conductivity of the second insertion layer 13a is greater than the thermal conductivity of the second heat-conducting layer 13. The thickness of the second insertion layer 13a is T6, 0.25*T31≤T6≤0.3*T31, and the vertical distance from the second insertion layer 13a to the first heat-conducting layer 12 is less than the vertical distance from the second insertion layer 13a to the outer edge of the second heat-conducting layer 13.

[0128] The second through-holes 13b are arranged on both sides of the second insertion layer 13a in the length direction of the second insertion layer 13a. The two second through-holes 13b are respectively arranged in the second upper heat-conducting layer 131, and one end of the two second through-holes 13b is respectively connected to the second upper heat-conducting layer 131, and the other end of the two second through-holes 13b is respectively connected to the second insertion layer 13a.

[0129] In this embodiment, based on the first and second schematic diagrams of the first and second groups of embodiments (based on the asymmetric design of the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122, and / or the asymmetric design of the second upper heat-conducting layer 131 and the first lower heat-conducting layer 132), the structural arrangement of the second heat-conducting layer 13 is further improved, thereby improving the efficiency of heat transfer from the first heat-conducting layer 12 to the second heat-conducting layer 13, thereby enhancing the heat dissipation effect of the chip packaging structure 100. In this embodiment, when the second upper heat-conducting layer 131 and the second lower heat-conducting layer 132 are arranged asymmetrically (when T31 ≠ T32, the heat dissipation effect of the entire chip packaging structure 100 is more significant), the heat dissipation speed is faster. Similarly, in actual applications, different thicknesses of the second upper heat-conducting layer 131 and the second lower heat-conducting layer 132 are within the scope of protection of the embodiments of this application.

[0130] See also Figure 13 In the third schematic diagram of the chip packaging structure 100 provided in the second embodiment of the present application, the first upper heat-conducting layer 121 includes a first upper main body portion 121a and two first upper wrapping portions 121b respectively provided on both sides of the first upper main body portion 121a. The first upper heat-conducting layer 121 is integrally formed. The length of the first upper main body portion 121a is equal to the length of the wafer layer 10 (the lengths are as shown in FIG. Figure 13 The length L1 of the first upper wrapping portion 121b is 0.08-0.12 mm, and preferably can be set to 0.1 mm.

[0131] The first lower heat conducting layer 122 includes a first lower main body portion 122a and two first lower wrapping portions 121b provided on both sides of the first lower main body portion 122a. The first lower heat conducting layer 122 is formed as a whole. The length of the first lower main body portion 122a is equal to the length of the wafer layer 10 (the lengths are both as shown in FIG. Figure 13 The length L1 of the first lower wrapping portion 121b is 0.08-0.12 mm, and preferably can be set to 0.1 mm.

[0132] The area of ​​each first lower wrapping portion 121b is greater than the area of ​​each first upper wrapping portion 121b.

[0133] In this embodiment, based on the asymmetric design of the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122, and / or the asymmetric design of the second upper heat-conducting layer 131 and the first lower heat-conducting layer 132, the specific structures of the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122 are further defined. The integrally formed heat-conducting layers can simplify the preparation process of the chip packaging structure 100, the specific structural dimensions of the heat-conducting layers can be closer to the specific structure of the wafer layer 10, and the metal lead 11 can be better sealed.

[0134] See also Figure 14In the fourth schematic diagram of the chip packaging structure 100 provided in the second group of embodiments of the present application, the chip packaging structure 100 further includes: two filling layers on the surface of the first heat-conducting layer 12 away from the wafer layer 10, the two filling layers being a first filling layer 151 and a second filling layer 152; the first filling layer 151 is arranged above the first upper heat-conducting layer 121, and the second filling layer 152 is arranged below the first lower heat-conducting layer 122. (The filling layers mentioned below can be understood as the first filling layer 151 and / or the second filling layer 152.) And the filling layers are in contact with the first heat-conducting layer 12 and the second heat-conducting layer 13, respectively, and the length of the filling layer is L2, L0<L2<(L0+2*L1). In this group of embodiments, the structure and position of the filling layer can be set to be consistent with the structure and position in the first group of embodiments.

[0135] The first heat-conducting layer 12 includes four retaining wall structures 12a, which are respectively provided on the two first upper wrapping portions 121b and the two first lower wrapping portions 121b. The filling layer is in full contact with the first upper main portion 121a and the first lower main portion 122a, respectively. The retaining wall structures 12a are used to limit the material of the filling layer between the first heat-conducting layer 12 and the second heat-conducting layer 13. Specifically, the thickness of the two filling layers can be equal or unequal.

[0136] In this embodiment, based on the asymmetric design of the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122, and / or the asymmetric design of the second upper heat-conducting layer 131 and the first lower heat-conducting layer 132, the chip packaging structure 100 provided is further limited to also include a filling layer and a retaining wall structure 12a. When the first heat-conducting layer 12 is thermally conductive silicone, there are gaps on the surface of the thermally conductive silicone, that is, the holes, cracks or protrusions on the surface of the silicone affect the surface morphology and performance. In this embodiment, the setting of the filling layer (silicone grease) can fill the surface gaps of the thermally conductive silicone (first heat-conducting layer 12). In addition, due to the extrusion phenomenon and thixotropy of thermally conductive silicone grease, the filling layer (thermal conductive silicone grease) needs to be limited by the retaining wall structure 12a, and further completely wrapped by the first heat-conducting layer 12 and the second heat-conducting layer 13.

[0137] See also Figure 15 In the fifth schematic diagram of the chip packaging structure 100 provided in the second group of embodiments of the present application, the chip packaging structure 100 further includes: two first insertion layers 12b, which are respectively arranged in the first upper heat conducting layer 121 and the first lower heat conducting layer 122.

[0138] The thermal conductivity of the first insertion layer 12b is greater than that of the first thermally conductive layer 12. The thickness of the first insertion layer 12b is T5, where 0.25*T21≤T5≤0.3*T21. The vertical distance between the first insertion layer 12b and the wafer layer 10 is less than the vertical distance between the first insertion layer 12b and the second thermally conductive layer 13. If the first thermally conductive layer 12 is evenly cut along a direction perpendicular to the thickness, the first insertion layer 12b is located on the half of the first thermally conductive layer 12 closer to the wafer layer 10.

[0139] Specifically, the thickness of the first insertion layer 12b in the first lower heat conducting layer 122 may be equal to the thickness of the first insertion layer 12b in the first upper heat conducting layer 121. The thickness of the first insertion layer 12b in the first lower heat conducting layer 122 may be greater than the thickness of the first insertion layer 12b in the first upper heat conducting layer 121, that is, the thickness of the first insertion layer 12b in the first lower heat conducting layer 122 may be greater than T5 and less than T22.

[0140] In this embodiment, based on the asymmetric design of the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122, and / or the asymmetric design of the second upper heat-conducting layer 131 and the first lower heat-conducting layer 132, a first insertion layer 12b with a higher thermal conductivity is further inserted into the first heat-conducting layer 12. Specifically, a material with a higher thermal conductivity, such as metal particles or metal flakes, can be added to the thermally conductive silicone layer to increase heat dissipation. Specifically, the first insertion layer 12b can reduce the thermal resistance of the first heat-conducting layer 12, thereby accelerating the heat dissipation of the overall chip package structure 100 and improving the heat dissipation efficiency of the high-power chip package structure.

[0141] See also Figure 16 In the sixth schematic diagram of the chip package structure 100 provided in the second set of embodiments of the present application, the second heat-conducting layer 13 includes a second upper heat-conducting layer 131 in contact with the first upper heat-conducting layer 121 and a second lower heat-conducting layer 132 in contact with the first lower heat-conducting layer 122. The second upper heat-conducting layer 131 has a thickness T31, and the second lower heat-conducting layer 132 has a thickness T32, where T31>T32. For example, in one embodiment, T32 is 0.1 mm, and T31 is 0.25 mm.

[0142] The thermal conductivity of the first insertion layer 12b is equal to the thermal conductivity of the second heat-conducting layer 13. It can be set that the material of the first insertion layer 12b is consistent with the material of the second heat-conducting layer 13.

[0143] The chip packaging structure 100 also includes: four first through-hole portions 12c, wherein two first through-hole portions 12c are respectively arranged on the first upper heat-conducting layer 121, and one end of the two first through-hole portions 12c are respectively connected to the second upper heat-conducting layer 131, and the other end of the two first through-hole portions 12c are respectively connected to the first insertion layer 12b arranged on the first upper heat-conducting layer 121.

[0144] The other two first through-holes 12c are respectively arranged on the first lower heat-conducting layer 122, and one ends of the other two first through-holes 12c are respectively connected to the second lower heat-conducting layer 132, and the other ends of the other two first through-holes 12c are respectively connected to the first insertion layer 12b arranged on the first lower heat-conducting layer 122.

[0145] In this embodiment, based on the asymmetric design of the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122, and / or the asymmetric design of the second upper heat-conducting layer 131 and the first lower heat-conducting layer 132, the first through-hole portion 12c is further provided to more conveniently conduct heat accumulated in the first heat-conducting layer 12 to the second heat-conducting layer 13. The heat in the first heat-conducting layer 12 can be quickly conducted to the second heat-conducting layer 13 along the first through-hole portion 12c, thereby improving the heat conduction effect.

[0146] See also Figure 17 In the seventh schematic diagram of the chip packaging structure 100 provided in the second group of embodiments of the present application, the chip packaging structure 100 further includes: two second insertion layers 13a, which are respectively arranged in the second upper heat conducting layer 131 and the second lower heat conducting layer 132.

[0147] The thermal conductivity of the second insertion layer 13a is greater than that of the second thermally conductive layer 13. The length of the second insertion layer 13a is L3, and the length of the second thermally conductive layer 13 is L4, where (L0 + 2*L1) < L3 < L4. The thickness of the second insertion layer 13a is T6, where 0.25*T32 ≤ T6 ≤ 0.3*T32. The vertical distance from the second insertion layer 13a to the first thermally conductive layer 12 is less than the vertical distance from the second insertion layer 13a to the outer edge of the second thermally conductive layer 13. If the second thermally conductive layer 13 is evenly cut along a direction perpendicular to its thickness, the second insertion layer 13a is located on the half of the second thermally conductive layer 13 closer to the first thermally conductive layer 12.

[0148] Specifically, the thickness of the second insertion layer 13a in the second lower heat conducting layer 132 may be equal to the thickness of the second insertion layer 13a in the second upper heat conducting layer 131. The thickness of the second insertion layer 13a in the second upper heat conducting layer 131 may be greater than the thickness of the second insertion layer 13a in the second lower heat conducting layer 132, that is, the thickness of the second insertion layer 13a in the second upper heat conducting layer 131 may be greater than T6 and less than T31.

[0149] In this embodiment, based on the asymmetric design of the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122, and / or the asymmetric design of the second upper heat-conducting layer 131 and the first lower heat-conducting layer 132, a second insertion layer 13a with a higher thermal conductivity is further inserted into the second heat-conducting layer 13. Specifically, a graphene material with a higher thermal conductivity can be added to the metal layer as the second insertion layer to improve heat dissipation. Specifically, the second insertion layer 13a can reduce the thermal resistance of the second heat-conducting layer 13, thereby accelerating the heat dissipation of the overall chip package structure 100 and improving the heat dissipation efficiency of the high-power chip package structure.

[0150] See also Figure 18 In the eighth schematic diagram of the chip packaging structure 100 provided in the second group of embodiments of the present application, the chip packaging structure 100 further includes: four second through-holes 13b, wherein two of the second through-holes 13b are respectively arranged on the second upper heat-conducting layer 131, and one end of the two second through-holes 13b is respectively connected to the outer surface of the entire chip packaging structure 100 through the second upper heat-conducting layer 131, and the other ends of the two second through-holes 13b are respectively connected to the second insertion layer 13a arranged on the second upper heat-conducting layer 131.

[0151] The other two second through-holes 13b are respectively arranged on the second lower heat-conducting layer 132, and one ends of the other two second through-holes 13b are respectively connected to the outer surface of the entire chip packaging structure 100 through the second lower heat-conducting layer 132, and the other ends of the other two second through-holes 13b are respectively connected to the second insertion layer 13a arranged on the second lower heat-conducting layer 132.

[0152] In this embodiment, based on the asymmetric design of the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122, and / or the asymmetric design of the second upper heat-conducting layer 131 and the first lower heat-conducting layer 132, the second through-hole portion 13b is added to more conveniently conduct heat accumulated in the second heat-conducting layer 13 to a location away from the wafer layer 10. The heat in the second heat-conducting layer 13 can be quickly conducted away from the wafer layer 10 along the second through-hole portion 13b, thereby improving the heat conduction effect.

[0153] In one embodiment, the above Figure 9 and Figure 10 The metal heat sink 16 and heat dissipation metal lead 17 added in the first group of embodiments involved in the present invention can also be arranged Figures 11-18 In the chip package structure 100 of the second embodiment involved in Figures 11-18The chip packaging structure 100 of the second embodiment described above is provided with a metal heat sink 16 and heat-dissipating metal leads 17. This not only ensures wire bonding of the wafer layer 10 (implemented by the metal leads 11), but also increases the heat dissipation area through the metal heat sink 16 and the heat-dissipating metal leads 17. Furthermore, multiple metal heat sinks 16 are spaced apart (each metal heat sink 16 corresponds to a pin of the chip extending from the wafer layer 10), and multiple heat-dissipating metal leads 17 extend from the multiple metal heat sinks 16. The metal heat sinks 16 are disconnected from each other, thus preventing electrical connection between the chip pins.

[0154] In one embodiment, the present application further provides a method for preparing a chip package structure 100, comprising the following steps:

[0155] S01 , providing a wafer layer 10 , and electrically connecting the wafer layer 10 to a metal lead 11 .

[0156] S02, forming a first heat-conducting layer 12 on the first surface and the second surface of the wafer layer 10 by dispensing, coating, liquid perfusion or sheet lamination. From a cross-section of the chip packaging structure 100, the first heat-conducting layer 12 wraps the wafer layer 10. The first heat-conducting layer 12 can be set to an insulating material, such as thermally conductive silicone. In some embodiments, the first heat-conducting layer 12 may include a first upper heat-conducting layer 121 and a first lower heat-conducting layer 122 (the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122 may be symmetrical structures, or the first upper heat-conducting layer 121 and the first lower heat-conducting layer 122 may be asymmetric structures). In some embodiments, a filling layer may be provided on the outer surface of the first heat-conducting layer 12 away from the wafer layer 10. In some embodiments, a first insertion layer 12b may be provided in the first heat-conducting layer 12. In some embodiments, a first through portion 12 may also be provided in the first heat-conducting layer 12 to reduce thermal resistance and improve heat dissipation efficiency.

[0157] S03, by dispensing, coating, liquid perfusion or sheet lamination, a second heat-conducting layer 13 is formed on the outside of the first heat-conducting layer 12. The second heat-conducting layer 13 does not completely wrap the first heat-conducting layer 12. And the area covered by the second heat-conducting layer 13 on the first heat-conducting layer 12 is greater than 90% of the area of ​​the first heat-conducting layer 12 itself. The second heat-conducting layer 13 can be set to a metal or ceramic material. In some embodiments, the second heat-conducting layer 13 may include a second upper heat-conducting layer 131 and a second lower heat-conducting layer 132 (the second upper heat-conducting layer 131 and the second lower heat-conducting layer 132 may be a symmetrical structure, or the second upper heat-conducting layer 131 and the second lower heat-conducting layer 132 may be an asymmetric structure. In some embodiments, the structural dimensions of the second upper heat-conducting layer 131 and the second lower heat-conducting layer 132 may be set to an asymmetric form. In some embodiments, a second insertion layer 13a may be provided in the second heat-conducting layer 13. In some embodiments, a second through portion 13b may also be provided in the second heat-conducting layer 13 to reduce thermal resistance and improve heat dissipation efficiency.

[0158] S04: Form a sealing layer 14 at the position where the second heat-conducting layer 13 does not completely cover the first heat-conducting layer 12. The sealing layer 14 can be set as epoxy resin. The sealing layer 14 can seal the metal lead 11 to achieve insulation between the wafer layer 10 and the outside world.

[0159] In some embodiments, the above steps may further include, S05, forming a plurality of metal heat sinks 16 outside the second heat conducting layer 13 (in this case, the second heat conducting layer 13 is made of a ceramic material). And, S06, forming heat dissipation metal leads 17 near the metal heat sinks 16 near the metal leads 11. The heat dissipation metal leads 17 are connected to the metal leads 11. The wafer layer 10 is insulated from the metal heat sinks 16.

[0160] In this embodiment, a preparation method of each structure in the above two groups of embodiments is provided to form a chip packaging structure 100 with good heat dissipation performance.

[0161] The foregoing description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

[0162] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, comprising: A first heat-conducting layer, a second heat-conducting layer, a sealing layer, and metal leads electrically connected to the wafer layer are arranged on the periphery of the wafer layer; It is characterized in that, viewed from a cross section of the chip packaging structure, the first heat-conducting layer wraps the wafer layer, and the thickness T1 of the wafer layer is 0.4-0.6 mm; The first heat-conducting layer includes a first upper heat-conducting layer and a first lower heat-conducting layer; the metal lead is connected to the wafer layer and is led out from a position where the first upper heat-conducting layer and the first lower heat-conducting layer contact each other; the thickness of the first upper heat-conducting layer is T21, the thickness of the first lower heat-conducting layer is T22, T22>T21, and the thickness T21 of the first heat-conducting layer is 0.08-0.12 mm; The second heat-conducting layer does not completely wrap the first heat-conducting layer, and the area covered by the second heat-conducting layer is greater than 90% of the area of ​​the first heat-conducting layer itself, and the thickness T3 of the second heat-conducting layer is 0.18-0.22 mm; The sealing layer is filled in the position where the second heat-conducting layer does not completely cover the first heat-conducting layer, the thickness T4 of the sealing layer is 0.2-0.4 mm, and the diameter of the metal lead is 0.08-0.12 mm; The thermal conductivity of the second heat-conducting layer is greater than the thermal conductivity of the first heat-conducting layer, and the absolute value of the difference between the thermal expansion coefficient of the first heat-conducting layer and the thermal expansion coefficient of the wafer layer is smaller than the absolute value of the difference between the thermal expansion coefficient of the second heat-conducting layer and the thermal expansion coefficient of the wafer layer.

2. The chip packaging structure according to claim 1, wherein: The second heat-conducting layer includes: a second upper heat-conducting layer in contact with the first upper heat-conducting layer and a second lower heat-conducting layer in contact with the first lower heat-conducting layer, the second upper heat-conducting layer has a thickness of T31, and the second lower heat-conducting layer has a thickness of T32, T31>T32, and T32 is 0.08-0.12 mm; The chip packaging structure includes: a first insertion layer, disposed on the first lower heat-conducting layer, wherein the thermal conductivity of the first insertion layer is greater than the thermal conductivity of the first heat-conducting layer, the thickness of the first insertion layer is T5, 0.25*T22≤T5≤0.3*T22, and the vertical distance from the first insertion layer to the wafer layer is less than the vertical distance from the first insertion layer to the second heat-conducting layer; Two first through-holes are provided on both sides of the first insertion layer in the length direction of the first insertion layer, the two first through-holes are respectively provided in the first lower heat-conducting layer, and one end of the two first through-holes is respectively connected to the second lower heat-conducting layer, and the other end of the two first through-holes is respectively connected to the first insertion layer; a second insertion layer disposed on the second upper heat-conducting layer, wherein the thermal conductivity of the second insertion layer is greater than the thermal conductivity of the second heat-conducting layer, the thickness of the second insertion layer is T6, 0.25*T31≤T6≤0.3*T31, and the vertical distance from the second insertion layer to the first heat-conducting layer is less than the vertical distance from the second insertion layer to the outer edge of the second heat-conducting layer; and The second through-holes are arranged on both sides of the second insertion layer in the length direction of the second insertion layer, and the two second through-holes are respectively arranged in the second upper heat-conducting layer, and one end of the two second through-holes is respectively connected to the second upper heat-conducting layer, and the other end of the two second through-holes is respectively connected to the second insertion layer.

3. The chip packaging structure according to claim 2, wherein: The first upper heat-conducting layer includes a first upper main body portion and two first upper wrapping portions provided on both sides of the first upper main body portion. The first upper heat-conducting layer is integrally formed. The length of the first upper main body portion is equal to the length of the wafer layer. The length L1 of the first upper wrapping portion is 0.08-0.12 mm. The first lower heat-conducting layer includes a first lower main body portion and two first lower wrapping portions provided on both sides of the first lower main body portion. The first lower heat-conducting layer is integrally formed. The length of the first lower main body portion is equal to the length of the wafer layer. The length L1 of the first lower wrapping portion is 0.08-0.12 mm. The area of ​​each of the first lower wrapping parts is greater than the area of ​​each of the first upper wrapping parts.

4. The chip packaging structure according to claim 3, wherein: The surface of the first heat-conducting layer away from the wafer layer further includes: two filling layers, the two filling layers being a first filling layer and a second filling layer; the first filling layer being arranged above the first upper heat-conducting layer, the second filling layer being arranged below the first lower heat-conducting layer, and the filling layers being in contact with the first heat-conducting layer and the second heat-conducting layer respectively, and the length of the filling layer being L2, L0<L2<(L0+2*L1); The first heat-conducting layer includes a total of four retaining wall structures, which are respectively arranged on the two first upper wrapping parts and the two first lower wrapping parts, and the filling layer is fully in contact with the first upper main body part and the first lower main body part respectively. The retaining wall structure is used to limit the material of the filling layer between the first heat-conducting layer and the second heat-conducting layer.

5. The chip packaging structure according to claim 4, wherein: The chip packaging structure further includes: two first insertion layers, respectively disposed in the first upper heat conducting layer and the first lower heat conducting layer; The thermal conductivity of the first insertion layer is greater than that of the first heat-conducting layer, the thickness of the first insertion layer is T5, 0.25*T21≤T5≤0.3*T21, and the vertical distance from the first insertion layer to the wafer layer is less than the vertical distance from the first insertion layer to the second heat-conducting layer.

6. The chip packaging structure according to claim 5, characterized in that: The chip packaging structure further includes: two second insertion layers, respectively disposed in the second upper heat conducting layer and the second lower heat conducting layer; The thermal conductivity of the second insertion layer is greater than the thermal conductivity of the second heat-conducting layer, the length of the second insertion layer is L3, the length of the second heat-conducting layer is L4, (L0+2*L1)<L3<L4; the thickness of the second insertion layer is T6, 0.25*T32≤T6≤0.3*T32, and the vertical distance from the second insertion layer to the first heat-conducting layer is less than the vertical distance from the second insertion layer to the outer edge of the second heat-conducting layer.

7. The chip packaging structure according to claim 6, wherein: The chip packaging structure further includes: The chip packaging structure further includes: four second through-holes, wherein two of the second through-holes are respectively provided on the second upper heat-conducting layer, and one end of the two second through-holes is respectively connected to the outer surface of the entire chip packaging structure through the second upper heat-conducting layer, and the other end of the two second through-holes is respectively connected to the second insertion layer provided on the second upper heat-conducting layer; The other two second through-holes are respectively arranged on the second lower heat-conducting layer, and one ends of the other two second through-holes are respectively connected to the outer surface of the entire chip packaging structure through the second lower heat-conducting layer, and the other ends of the other two second through-holes are respectively connected to the second insertion layer arranged on the second lower heat-conducting layer.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The second heat-conducting layer is made of ceramic material; The chip packaging structure further includes: a metal heat sink and a heat dissipation metal lead connected to the metal heat sink; the metal heat sink is arranged outside the second heat conducting layer, and the wafer layer is insulated from the metal heat sink; the heat dissipation metal lead is connected to the metal lead.

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