Chip detection method, system, electronic device and computer readable storage medium

Abstract

The application is suitable for the chip testing technical field, and provides a chip detection method, a system, an electronic device and a computer readable storage medium. The method comprises the following steps: obtaining a test value of each first chip in a plurality of first chips passing the test, and the plurality of first chips correspond to the same test limit value; determining at least one potential defective chip from the plurality of first chips according to the test values of the plurality of first chips and the test limit value; determining a margin value of each potential defective chip, and the margin value indicates a difference degree between any potential defective chip and a test value of each chip of at least one adjacent chip in a chip test graph; the chip test graph comprises test values of a plurality of chips, and the plurality of chips comprise at least one potential defective chip; and determining a test result of any potential defective chip according to a size relationship between the margin value and a preset threshold. In this way, the probability of chip failure is reduced, and the reliability and accuracy of chip testing are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip testing, and particularly relates to a chip detection method and system, an electronic device and a computer readable storage medium. BACKGROUND

[0002] The development of the semiconductor industry chain is an important cornerstone of contemporary technology industry, and its application has penetrated into various industries. As an important branch of the semiconductor industry, the importance of automotive chips is increasingly prominent. Automotive chips are integrated circuits used in cars, which integrate various electronic components to achieve specific functions such as car entertainment systems, car communication systems, car navigation systems, and car control systems. These chips not only improve the intelligence level of cars, but also directly affect the performance and safety of cars.

[0003] However, although the design and manufacturing process of automotive chips has undergone strict testing, the existing chip testing method still has certain limitations. In actual application, there are still problems of quality defects in chips after chip manufacturers deliver tested automotive chips to customers, which brings trouble and economic loss to chip manufacturers.

[0004] Therefore, how to screen out chips that may have chip failure problems from tested automotive chips, reduce the probability of chip failure, and improve the reliability and accuracy of chip testing has become a technical problem that needs to be solved at present. SUMMARY

[0005] The embodiments of the application provide a chip detection method and system, an electronic device and a computer readable storage medium, which can solve the problem of how to screen out chips that may have chip failure problems from tested automotive chips, reduce the probability of chip failure, and improve the reliability and accuracy of chip testing.

[0006] In a first aspect, the embodiments of the application provide a chip detection method, comprising:

[0007] determining at least one potentially defective chip from a plurality of first chips according to test values of the plurality of first chips and test limits;

[0008] determining a margin value of each potentially defective chip, the margin value indicating a difference between any potentially defective chip and each chip of at least one adjacent chip in a chip test graph; the chip test graph comprises test values of a plurality of chips, and the plurality of chips comprises at least one potentially defective chip;

[0009] re-determining a test result of any potentially defective chip according to a size relationship between the margin value and a preset threshold.

[0010] In some embodiments, the margin value of each potential defective chip is determined, including:

[0011] A chip test graph corresponding to each potential defective chip is obtained, and the chip test graph corresponding to any potential defective chip includes test values of one or more chips and test values of the potential defective chip.

[0012] According to the chip test graph corresponding to any potential defective chip, the margin value of the potential defective chip is determined.

[0013] In some embodiments, the margin value of any potential defective chip is determined according to the chip test graph corresponding to the potential defective chip, including:

[0014] According to the chip test graph corresponding to any potential defective chip, a detection area is determined, and the detection area includes the potential defective chip and at least one chip adjacent to the potential defective chip in the chip test graph.

[0015] According to the test values of each chip in the detection area, the margin value of the potential defective chip is determined.

[0016] In some embodiments, at least one potential defective chip is selected from a plurality of first chips according to test values of the plurality of first chips and a test limit value, including:

[0017] According to the test limit value and the plurality of test values, a first normal distribution curve is determined, the first normal distribution curve includes at least part of the plurality of test values, and a first mean value and a standard deviation value determined based on the at least part of the test values and the test limit value.

[0018] The abscissa of the first normal distribution curve is divided into a plurality of interval ranges based on the first mean value as a reference and the standard deviation value as an interval, and the abscissa is used to indicate the at least part of the test values.

[0019] The first chip corresponding to the test value of the plurality of test values of the plurality of first chips located in a preset interval range is determined as a potential defective chip, and the preset interval range is one of the plurality of interval ranges.

[0020] In some embodiments, the test limit value includes an upper limit value and a lower limit value, and the first normal distribution curve is determined according to the test limit value and the plurality of test values, including:

[0021] An ideal mean value is determined according to the upper limit value and the lower limit value.

[0022] The plurality of test values are subjected to normal distribution analysis to obtain an actual normal distribution curve, and the actual normal distribution curve includes the plurality of test values and an actual mean value determined based on the plurality of test values.

[0023] If the deviation between the actual mean value and the ideal mean value is within the preset range, the actual normal distribution curve is determined as the first normal distribution curve;

[0024] If the deviation between the actual mean value and the ideal mean value exceeds the preset range, a processing operation is performed on the plurality of test values to update the actual normal distribution curve and the actual mean value, so that the deviation between the updated actual mean value and the ideal mean value is within the preset range; the processing operation includes deleting at least one test value in the plurality of test values;

[0025] The updated actual normal distribution curve is determined as the first normal distribution curve.

[0026] In some embodiments, according to the test value of each chip in the to-be-inspected region, a margin value of any potential defective chip is determined, including:

[0027] A second mean value of the test value of each chip in the to-be-inspected region except any potential defective chip is determined;

[0028] A difference between the test value of any potential defective chip and the second mean value is determined as the margin value.

[0029] In some embodiments, in a chip test image corresponding to any potential defective chip, a to-be-inspected region is determined, including:

[0030] Based on coordinate information of each chip in the chip test image corresponding to any potential defective chip, a chip adjacent to any potential defective chip is determined, and a to-be-inspected region is composed of any potential defective chip and the determined chip.

[0031] In some embodiments, the method further includes:

[0032] At least one set of chip combinations is obtained from the data classification analysis device, a plurality of chips in the same chip combination have the same test limit value, test limit values corresponding to different chip combinations are different, and all chips in at least one set of chip combinations are test-passing chips; the plurality of first chips belong to any chip combination.

[0033] In a second aspect, the embodiments of the present application provide a chip detection device, the device includes:

[0034] The obtaining module is configured to obtain a test value of each first chip in the plurality of test-passing first chips, and the plurality of first chips correspond to the same test limit value;

[0035] The first determining module is configured to determine at least one potential defective chip from the plurality of first chips according to the test values of the plurality of first chips and the test limit value;

[0036] a second determining module configured to determine a margin value of each potential defective chip, the margin value indicating a difference degree between any potential defective chip and each chip in at least one adjacent chip of the chip test diagram; the chip test diagram comprises test values of a plurality of chips, and the plurality of chips comprises at least one potential defective chip;

[0037] a third determining module configured to determine a test result of any potential defective chip according to a size relationship between the margin value and a preset threshold.

[0038] As an example, the chip detection apparatus can be a functional circuit or a controller or a chip applied to a chip detection system, or the chip detection apparatus is the chip detection system, and the embodiments of the present application do not limit this.

[0039] In a third aspect, the embodiments of the present application provide a chip detection system, which comprises:

[0040] an automatic detection subsystem configured to respectively test a plurality of to-be-tested chips based on at least one test item, and output test information of each to-be-tested chip under the at least one test item, the test information comprising a test value, a test result and a test limit value corresponding to each to-be-tested chip under each test item;

[0041] a data classification and analysis apparatus connected to the automatic detection subsystem and configured to test information of each to-be-tested chip under the at least one test item; group a plurality of chips that pass the test in the plurality of to-be-tested chips, at least one chip combination, at least one chip in a same chip combination has a same test limit value, and different chip combinations correspond to different test limit values;

[0042] a chip detection apparatus configured to determine a margin value of each potential defective chip, and output whether the potential defective chip passes the test based on a size relationship between the margin value and a preset threshold;

[0043] a re-marking engine configured to mark a test result of any potential defective chip as test failure or test pass according to a result output by the chip detection apparatus.

[0044] In a fourth aspect, the embodiments of the present application provide an electronic device, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the chip detection method according to any one of the embodiments of the first aspect when executing the computer program.

[0045] In a fifth aspect, the embodiments of the present application provide a computer readable storage medium, which stores a computer program, and the computer program is executable on a processor to implement the chip detection method according to any one of the embodiments of the first aspect.

[0046] In a sixth aspect, an embodiment of the present application provides a computer program product, which, when running on a terminal device, causes the terminal device to perform the chip detection method in any of the embodiments of the first aspect.

[0047] Compared with the prior art, the embodiment of the present application has the beneficial effects that the potential defective chip which may have a chip failure risk is determined from a plurality of first chips which have passed the test and have the same test limit, and the margin value of each potential defective chip is determined based on the chip test map including at least one potential defective chip, the margin value indicating the difference degree between any potential defective chip and each chip of at least one adjacent chip in the chip test map, so that the secondary analysis of the chips which have passed the test is realized while the spatial relationship between the chips is also considered, the determined margin value can more reasonably and accurately reflect the difference degree between the potential defective chip and the test value of each adjacent chip, and then based on the size relationship between the difference degree and the preset threshold, the possibility of chip failure of the potential defective chip can be reasonably and accurately predicted, so that the test result of the potential defective chip is re-determined. The chips which may have a chip failure problem are screened from the chips which have passed the test, such as automotive chips, the probability of chip failure is reduced, the reliability and accuracy of chip testing are improved, and the economic loss of the chip manufacturer is also reduced.

[0048] It can be understood that the beneficial effects of the second aspect to the sixth aspect can be referred to the related description in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0050] Figure 1 is a schematic diagram of a normal distribution curve to which the test value of the chip conforms in chip detection

[0051] Figure 2 is a schematic diagram of a chip detection system provided by an embodiment of the present application;

[0052] Figure 3 is a flowchart of a chip detection method provided by an embodiment of the present application;

[0053] Figure 4 is a schematic diagram of a first normal distribution curve in an embodiment of the present application;

[0054] Figure 5is a flowchart of a chip detection method provided by an embodiment of the present application;

[0055] Figure 6 is a flowchart of a residual value determination of any potential defective chip in an embodiment of the present application;

[0056] Figure 7 is a flowchart of a determination of whether to update a test result of any potential defective chip in an application scenario;

[0057] Figure 8 is a structural diagram of a device provided by an embodiment of the present application;

[0058] Figure 9 is a structural diagram of a chip detection device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0059] In the following description, specific details are set forth, such as particular system configurations, techniques, etc., in order to provide a thorough understanding of the present application. However, persons having ordinary skill in the art will appreciate that the present application can be practiced without these specific details. In other instances, well-known structures and techniques have not been shown in detail in order not to obscure the understanding of this application.

[0060] It should be understood that the term "comprises" when used in this specification and the appended claims specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0061] It should also be understood that the term "and / or" when used in this specification and the appended claims, such as in the phrases "A and / or B" and "A and B" means that the associated term can be one or the other or both.

[0062] As used in this specification and the appended claims, the term "if' can be construed to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be construed to mean "upon determining" or "in response to determining" or "upon [the described condition or event] being detected" or "in response to [the described condition or event] being detected," depending on the context.

[0063] In addition, the terms "first", "second", "third", etc. are used herein only to distinguish one element from another, and do not imply or suggest relative importance.

[0064] Reference within this specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in some embodiments" in various places within specified

[0065] The semiconductor industry chain has developed to the present, and various products have been applied in all aspects of daily life. With the change of consumer groups and the continuous market demand, the demand for high-level chips such as automotive chips and military chips is also increasing.

[0066] In the face of market demand, semiconductor chip manufacturers will mass-produce high-level chips such as automotive chips, but semiconductor manufacturers often face a dilemma when producing chips. Before the chips are handed over to the customers, even if the production of the chips strictly follows the standard operation process, the chips have been subjected to various quality tests, and the electrical characteristics of the chips have been checked 100%. However, there are still a large number of chip quality problems fed back from the customers, which brings economic losses to the chip manufacturers.

[0067] Moreover, with the development of intelligent vehicles, the industry's requirements for automotive chips are also increasing. For example, the Automotive Electronics Council (AEC) in the promulgated AEC-Q001 provisions, the average test method (Part average testing, PAT) as a strategic test tool, the method in the ZPAT (Z-axis Part Average Testing, Z-axis average test), DPAT (Dynamic Part Average Testing, dynamic average test), SPAT (Static Part Average Testing, static average test), GDBN (Good Die in Bad Neighborhood, Good Die in Bad Neighborhood) and NNR (Nearest Neighbor Residual, Nearest Neighbor Residual algorithm) and other test items are included in the certification content of automotive chips.

[0068] This leads to the need for authentication of a wide range of data in the production process of automotive chips, and the collection method of each kind of data and the authentication method are required to be strict, resulting in great difficulty in chip production, which is one of the reasons for the slow development of domestic automotive electronic chips. Moreover, although the PAT average test method can effectively detect defective parts with abnormal test parameters in a large number of products, this method still cannot solve the problems faced by chip manufacturers in chip production.

[0069] In the face of the above problems of chip manufacturers, an innovative chip detection method is urgently needed to reduce the probability of quality defect problems of automotive chips that have passed the test after chip testing, improve the reliability and accuracy of chip testing.

[0070] Research has found that in the mass production testing of semiconductor chips such as automotive chips, the test values obtained usually conform to a normal distribution, and similarly, using the PAT average test method for batch chip testing can obtain a normal distribution curve as shown in Figure 1 For chips that pass the test, about 93.3% of the chips have test values within the interval [-3σ, +3σ], and about 6.7% of the chips have test values within the limit interval, i.e. [-6σ, -3σ] and [+3σ, +6σ], but the test values of the chips within the limit interval are closer to the test limits, i.e. the lower limit value (Lower Specification Limit, LSL) and the upper limit value (Upper Specification Limit, USL) in Figure 1 The chips in this interval have a higher probability of chip failure problems.

[0071] Therefore, the present application provides a chip detection method, which can determine potential defective chips that may have chip failure risks from a plurality of first chips that have passed the test and have the same test limits, and perform secondary analysis on the test values of the potential defective chips to identify chips that will actually have chip failure from the potential defective chips, helping test personnel to eliminate chips that will have quality problems later from the chips that have passed the test, greatly reducing the number of "false test passed chips" that will have quality problems in the chips that have passed the test, reducing the probability of quality defect problems of automotive chips, improving the reliability and accuracy of chip testing, enabling chip testing to meet more stringent industry requirements, expanding the application scenarios of chip testing, and reducing the economic losses of chip manufacturers.

[0072] The chip detection method provided by the present application will be described in detail below. First, the chip detection system to which the chip detection method is applied will be introduced. As shown in Figure 2As shown, the chip detection system 200 includes an automatic detection subsystem 210, a data classification analysis device 220, a chip detection device (also referred to as a PAT calculation subsystem) 230, and a relabeling engine 240.

[0073] The automatic detection subsystem 210 includes an ATE (Automatic Test Equipment), a Prober device (probe station), and a Probe card device (probe card). The ATE is mainly used to implement test items such as function tests, performance tests, and quality verification tests on the chips to be tested. The Prober device is used to contact probes with each chip on a wafer in wafer testing, and is usually used in combination with the ATE to test the electrical performance of the chips to be tested on the wafer. The Probe card device is an interface between the chips to be tested and the testing machine in wafer testing, and is mainly used to preliminarily measure the electrical performance of the chips before the chips are packaged, and to screen out defective chips.

[0074] The automatic detection subsystem 210 is configured to test a plurality of chips to be tested based on at least one test item, and output test information of each chip to be tested under the at least one test item. The test information includes a test value, a test result, and a corresponding test limit value of the chip to be tested under each test item. The test item includes at least any one of an electrical characteristic test, a function test, an aging test, a performance test, and a reliability test.

[0075] The data classification analysis device 220 and the chip detection device 230 can be an industrial computer, a desktop computer, a server, or an electronic device, or can be a cloud computing platform, or can be a processor with a data processing function. The data classification analysis device 220 and the chip detection device 230 can be selected based on the amount of data to be processed and the processing speed, and the embodiments of the present application do not make specific limitations. The data classification analysis device 220 is connected to the automatic detection subsystem 210, the chip detection device 230 is connected to the data classification analysis device 220, and the relabeling engine 240 is connected to the chip detection device 230.

[0076] The data classification analysis device 220 is configured to group a plurality of chips that pass the test in the plurality of chips to be tested according to the test information of each chip to be tested under the at least one test item. At least one chip combination is combined, at least one chip in the same chip combination has the same test limit value, and different chip combinations correspond to different test limit values. The data classification analysis device 220 is further configured to determine at least one potential defect chip in each chip combination.

[0077] The chip detection device 230 is configured to determine the margin value of each potential defective chip, and output whether the potential defective chip passes the test based on the size relationship between the margin value and the preset threshold value.

[0078] The re-labeling engine 240 is configured to label the test result of any potential defective chip as test failure or test pass according to the result output by the chip detection device.

[0079] It should be noted that the data classification analysis device 220, the chip detection device 230, and the re-labeling engine 240 can be different modules in the same device, or can be three different devices, or the data classification analysis device 220 and the chip detection device 230 can be different modules in the same device, or can be two different devices.

[0080] The chip detection method of the present application will be described in detail below, such as Figure 3 The chip detection method of the present application will be described in detail below, such as Figure 1 The chip detection method of the present application will be described in detail below, such as

[0081] In step S301, the chip detection system obtains the test value of each first chip in a plurality of first chips that pass the test.

[0082] The plurality of first chips correspond to the same test limit value. After testing the to-be-tested chips, the automatic detection subsystem in the chip detection system outputs the test results and test values of the plurality of to-be-tested chips under different test items, and the test limit value corresponding to the plurality of to-be-tested chips. The chip detection system uses the data classification analysis device in the chip detection system to screen out the chips with test results passing the test from the test results output by the automatic detection subsystem, and takes any batch of chips with the same test limit value in the chips passing the test as the first chips, thereby obtaining the test values of the first chips.

[0083] In step S302, the chip detection system determines at least one potential defective chip from the plurality of first chips according to the test values of the plurality of first chips and the test limit value.

[0084] The chip detection system screens out at least one test value close to the test limit value from the test values of the plurality of first chips, and takes the first chip corresponding to each screened test value as a potential defective chip.

[0085] As an example, the chip detection system utilizes the data classification analysis device to count the deviation between the test value of the first chip and the test limit value, and regards the first chip corresponding to the test value with a deviation greater than or equal to a specified value as a potential defective chip. For example, in order to quickly find the potential defective chip, and considering that the test value of the chip test passes the normal distribution, and the test value farther away from the mean value in the normal distribution is closer to the test limit value. The chip detection system utilizes the data classification analysis device to draw a histogram based on the test values of the plurality of first chips, and draws a normal distribution curve based on the histogram (the horizontal coordinate of the normal distribution curve is the test value), and selects the test value outside the specified length (for example, three standard deviation values) from the mean value (the mean value is determined in the process of drawing the normal distribution curve) in the normal distribution curve, and the selected test value is the test value of the potential defective chip.

[0086] For example, the chip detection system utilizes the data classification analysis device to obtain the histogram and the normal distribution curve as shown in FIG. 4, wherein the X-axis is the test value, the Y-axis is the frequency of the test value, 410 represents the mean value, 420 represents the value with a distance of +3Sigma (i.e., +3σ, which means three standard deviation values) from the mean value, and 430 represents the value with a distance of -3Sigma (i.e., -3σ, which means three standard deviation values) from the mean value. The chip detection system utilizes the data classification analysis device to regard the values outside 420 and 430 as being within the test limit value. Figure 4 Figure 4 Figure 4

[0087] For another example, the chip detection system utilizes the data classification analysis device to calculate the difference between the test value of the first chip and the test limit value, and when the difference is less than or equal to a specified value, the first chip is determined to be a defective chip. Alternatively, when the test limit value includes an upper limit value and a lower limit value, the chip detection system utilizes the data classification analysis device to calculate the difference between the test value of the first chip and the mean value of the upper limit value and the lower limit value, and when the difference is greater than or equal to another specified value, the first chip is a defective chip.

[0088] Step S303, the chip detection system determines the margin value of each potential defective chip.

[0089] ​​​The residual value indicates the difference between any potential defective chip and each chip adjacent to the potential defective chip in the chip test graph. The chip test graph includes test values of a plurality of chips, and the plurality of chips includes at least one potential defective chip. After the chip detection system determines the potential defective chip by using the data classification analysis device, the chip detection system can also obtain the test item to which the test value of the potential defective chip belongs. After the chip detection system detects a plurality of to-be-detected chips by using the automatic detection subsystem, the automatic detection subsystem generates and outputs a chip test graph of a wafer on which each to-be-detected chip is located. The chip test graph identifies each chip on the wafer and the test value of each chip under at least one test item.

[0090] In this way, the chip detection system can obtain the chip test graph in which each potential defective chip is located from the chip test graph output by the automatic detection subsystem. For each potential defective chip, the chip detection system can find the test value under the test item to which the test value of the potential defective chip belongs from the chip test graph including the potential defective chip.

[0091] The chip detection system can find the chip adjacent to any potential defective chip in the chip test graph in which the potential defective chip is located, and determine the test value of the adjacent chip under the test item in the corresponding chip test graph based on the test item to which the test value of the potential defective chip belongs. Then, the chip detection system can calculate the mean value between the test value of the potential defective chip and the determined test value by using the chip detection device, and calculate the difference between the test value of the potential defective chip and the mean value. The chip detection system can determine the difference as the residual value.

[0092] As an example, the specific process of finding the chip adjacent to any potential defective chip in the chip test graph in which the potential defective chip is located can be that, based on the position coordinates of each chip in the chip test graph, the chip detection system can find the chips located around any potential defective chip in the chip test graph. Alternatively, based on the position coordinates of each chip in the chip test graph, the chip detection system can query the chip closest to any potential defective chip. The distance for the query can be a straight-line distance or a Euclidean distance, etc.

[0093] In step S304, the chip detection system re-determines the test result of any potential defective chip according to the size relationship between the residual value and a preset threshold.

[0094] The chip detection system compares the size relationship between the margin value of each potential defective chip and the preset threshold value by using the chip detection device. If the margin value is greater than the preset threshold value, the chip detection device determines that the potential defective chip fails the test. In this case, the chip detection system re-labels the test result of the potential defective chip as a test failure by using the re-labeling engine. If the margin value is less than or equal to the preset threshold value, the re-labeling engine keeps the test result of any potential defective chip unchanged. The preset threshold value can be set based on the required accuracy of chip detection, for example, 3% or 5% of the mean value of the test limit, and the embodiments of the present application do not make specific limitations.

[0095] In the embodiments of the present application, the potential defective chip that may have a chip failure risk is determined from a plurality of first chips that have passed the test and have the same test limit, and the margin value of each potential defective chip is determined based on the chip test map corresponding to at least one potential defective chip. The margin value indicates the difference between any potential defective chip and the test value of each chip adjacent to the chip test map. The spatial relationship between chips is considered while performing secondary analysis on the chips that have passed the test, so that the determined margin value can more reasonably and accurately reflect the difference between the potential defective chip and the test value of each adjacent chip. Then, based on the size relationship between the difference and the preset threshold value, the possibility of chip failure of the potential defective chip can be reasonably and accurately predicted, so as to re-determine the test result of the potential defective chip. The purpose of screening chips that may have chip failure problems from the chips that have passed the test, such as automotive chips, is achieved, the probability of chip failure is reduced, the reliability and accuracy of chip testing are improved, and the economic loss of chip manufacturers is also reduced.

[0096] Figure 5 is a flowchart of another chip detection method according to an embodiment of the present application. The method is executed by the chip detection system shown in Figure 1 The method includes the following steps:

[0097] Steps S501-S502. For details, refer to steps S501-S502 in the embodiment shown in Figure 3 Steps S301-S302 in the embodiment shown in

[0098] In some embodiments, the test value of each first chip in the plurality of first chips that have passed the test is obtained, including: obtaining at least one chip combination from the data classification and analysis device, the plurality of chips in the same chip combination having the same test limit, the test limit of different chip combinations being different, all chips in at least one chip combination being chips that have passed the test; and the plurality of first chips belonging to any chip combination.

[0099] The multiple chips in the same chip combination have the same test limit value, that is, the test values of the chips that pass the test in at least one test item are divided according to the same test limit value, the test values in multiple test items with the same test limit value are grouped, the number of data groups (that is, the test values of the chips in the chip combination) that need to be analyzed subsequently is reduced, the data analysis speed is accelerated, the secondary analysis speed of the chips that pass the test is improved, and the chips that may cause chip failure problems can be quickly found from the chips that pass the test.

[0100] The specific process in which the data classification and analysis device obtains the at least one chip combination can include the following steps:

[0101] The data classification and analysis device obtains, from the automatic detection subsystem, the test values of the multiple chips to be tested in at least one test item, the test results, and the corresponding test limit values of the multiple chips to be tested in the at least one test item.

[0102] The data classification and analysis device selects, from the multiple chips to be tested, the chips whose test results in each test item are all test pass, based on the test results of each chip to be tested in the at least one test item.

[0103] The data classification and analysis device groups the test values of the selected chips in the at least one test item according to the same test limit value, and obtains at least one chip combination.

[0104] In one example, the data output by the automatic detection subsystem and obtained by the data classification and analysis device can be as shown in Table 1.

[0105] In Table 1, “P / F” represents the test result, P represents test pass, and F represents test fail. The test limit value is composed of the Test Number (lower limit value) and the Upper Limit (upper limit value). The Test Name in Table 1 is the test name, and the Test Number is the test number, both of which are used to identify different test items implemented by the automatic detection subsystem on the chips to be tested. RK0, ROW_OS, LAT_OS, and DRV_OUT are specific test names of a test item, in which RK0 represents resistance test, ROW_OS represents one open short (OS) test of the chip to be tested, LAT_OS represents another open short test of the chip to be tested, and DRV_OUT represents driver output test of the chip to be tested. Units represents the unit. The values under the column of each test name, such as 4.3268 or -0.5005, are the test values.

[0106] Table 1

[0107]

[0108] Site Num (Site Number or Number of Sites) is the number of test sites or the number of sites, which represents the number of chips (Die) that can be tested simultaneously in the wafer testing process. This concept mainly appears in the scene of testing the die on the wafer using the probe card (Probe Card) and the prober (Prober). Serial Num (Serial Number) is the serial number, SBin (Software Bin) is the software Bin. HBin (Hardware Bin) is the hardware Bin.

[0109] Assuming that any test value in Table 1 represents a to-be-tested chip, the data classification and analysis device screens out 6 to-be-tested chips with test results P, and obtains 24 test values. After the chip detection system groups the 24 test values according to the same test limit value by using the data classification and analysis device, 3 chip combinations can be obtained, which are respectively 6 test values corresponding to the to-be-tested chips under RK0, 6 test values corresponding to the to-be-tested chips under DRV_OUT, and 12 test values corresponding to the to-be-tested chips under ROW_OS and LAT_OS. It can be understood that the chips in the three chip combinations are all the 6 to-be-tested chips screened out, but they correspond to different test limit values (for example, 0-3800, -0.8-0.2 and -100-100 in Table 1).

[0110] As an example, after the chip detection system detects a plurality of to-be-tested chips by using the automatic detection subsystem, the automatic detection subsystem generates and outputs a chip test diagram of the wafer on which each to-be-tested chip is located, and the chip test diagram identifies each chip on the wafer and the test value and test result of each chip under at least one test item. The data classification and analysis device can first collect the chip test diagram output by the automatic detection subsystem and the test limit value corresponding to each to-be-tested chip under different test items. Then, according to the test result recorded on the chip test diagram, the chips that pass the test are screened out from the plurality of to-be-tested chips. Then, according to the same standard of the test limit value, the test values of the screened chips under different test items are grouped to obtain the test values of a plurality of first chips. It can be understood that the chips on the wafer that need to be tested are to-be-tested chips.

[0111] In some embodiments, determining at least one potentially defective chip from the plurality of first chips according to the test values of the plurality of first chips and the test limit value includes the following steps (1) to (3):

[0112] Step (1), the chip detection system determines a first normal distribution curve according to the test limit value and the plurality of test values.

[0113] The first normal distribution curve includes at least part of the test values, and a first mean value and a standard deviation value determined based on the at least part of the test values. The chip testing system draws a histogram of the test values of the plurality of first chips by using the data classification analysis device, and draws a normal distribution curve based on the histogram, and adds a straight line representing the test limit value to the drawn normal distribution curve to obtain the first normal distribution curve.

[0114] In some embodiments, the test limit value includes an upper limit value and a lower limit value. The first normal distribution curve is determined according to the test limit value and the plurality of test values, including the following steps (11) to (15):

[0115] Step (11), the chip testing system determines an ideal mean value according to the upper limit value and the lower limit value.

[0116] The chip testing system calculates the mean value of the upper limit value and the lower limit value by using the data classification analysis device, and determines the calculated mean value as the ideal mean value.

[0117] Step (12), the chip testing system performs normal distribution analysis on the plurality of test values to obtain an actual normal distribution curve.

[0118] The actual normal distribution curve includes the plurality of test values and an actual mean value determined based on the plurality of test values. The chip testing system calculates a time mean value of the plurality of test values by using the data classification analysis device, and calculates a standard deviation of the plurality of test values to obtain an actual standard deviation value, thereby drawing a normal distribution curve of the plurality of test values based on the actual mean value and the actual standard deviation value to obtain the actual normal distribution curve.

[0119] In an example, the chip testing system draws the number of groups and the group distance of the test values of the plurality of first chips by using the data classification analysis device, and calculates the frequency of the test values in each group. The actual histogram is drawn with the test value grouping interval as the horizontal axis and the test value frequency as the vertical axis. According to the actual mean value, the actual standard deviation value, and the grouping of the test values of the plurality of first chips, the frequency that should be theoretically contained in each grouping interval is calculated by using the probability density function of the normal distribution. The frequency that should be theoretically contained in each grouping interval can be approximately calculated by using integral operation or lookup table (such as normal distribution table). Further, based on the actual histogram, the calculated theoretical frequency is taken as the vertical coordinate to draw a smooth curve to obtain the actual normal distribution curve.

[0120] Step (13), if the deviation between the actual mean value and the ideal mean value is within a preset range, the chip testing system determines the actual normal distribution curve as the first normal distribution curve.

[0121] The preset range is set based on the accuracy requirement of the chip detection, and embodiments of the present application do not make specific limitations. When the deviation between the actual mean value and the ideal mean value is within the preset range, the actual mean value at this time is the first mean value, and the actual standard deviation value is the standard deviation value in the first normal distribution curve.

[0122] Step (14), the deviation between the actual mean value and the ideal mean value exceeds the preset range, and the chip detection system performs processing operation on the plurality of test values to update the actual normal distribution curve and the actual mean value, so that the deviation between the updated actual mean value and the ideal mean value is within the preset range.

[0123] The processing operation includes deleting at least one test value in the plurality of test values. The processing operation further includes determining a test value that does not conform to the normal distribution from the plurality of test values. When the deviation between the actual mean value and the ideal mean value exceeds the preset range, the chip detection system determines a test value that does not conform to the normal distribution from the plurality of test values by using the data classification analysis device, and deletes the determined test value, and then updates the actual normal distribution curve and the actual mean value, so that the deviation between the updated actual mean value and the ideal mean value is within the preset range.

[0124] In one example, the test value that does not conform to the normal distribution can be a test value that is outside three times the actual standard deviation value from the actual mean value in the actual histogram and exceeds the boundary of the actual normal distribution curve.

[0125] In one example, the test result of the first chip corresponding to the deleted test value remains unchanged.

[0126] Step (15), the chip detection system determines the updated actual normal distribution curve as the first normal distribution curve.

[0127] In the above technical solution, in the process of determining the first normal distribution curve, when the deviation between the actual mean value determined based on the plurality of test values and the ideal mean value is large, that is, the deviation exceeds the preset range, the processing operation including deleting at least one test value is performed on the plurality of test values, and the individual that deviates obviously from the ideal mean value is removed, so as to ensure that the first mean value in the determined first normal distribution curve is close to or equal to the ideal mean value, and the first normal distribution curve more accurately reflects the main distribution characteristics of the test values, thereby improving the reliability and accuracy of screening the chips that may have chip failure problems from the test passed automotive chips.

[0128] Step (2), the chip detection system divides the abscissa of the first normal distribution curve into intervals based on the first mean value as the benchmark and the standard deviation value as the interval, to obtain a plurality of interval ranges.

[0129] The horizontal axis is used to indicate at least part of the test values. The vertical axis of the first normal distribution curve is used to indicate the frequency of the at least part of the test values. The chip testing system divides a plurality of endpoint values in the horizontal axis of the first normal distribution curve with the first mean value as a reference and the standard deviation value as an interval. The interval between two endpoint values is an interval range. The chip testing system divides the endpoint values by using the data classification analysis device. The number of the standard deviation value in each interval can be the same or different. For example, the chip testing system divides an endpoint value in the horizontal axis of the first normal distribution curve with the first mean value as a reference and every interval of one standard deviation value until the sixth standard deviation value. At this time, the chip testing system can obtain twelve interval ranges, for example, Figure 1 μ~μ+σ (i.e., 0~1) and μ+σ~μ+2σ (μ+2σ, Figure 1 (i.e., 1~2) and the like.

[0130] For example, the chip testing system divides an endpoint value in the horizontal axis of the first normal distribution curve with the first mean value as a reference and every interval of three standard deviation values to the left and right sides. Then, the chip testing system divides an endpoint value in the horizontal axis of the first normal distribution curve with the first mean value as a reference and every interval of six standard deviation values to the left and right sides. At this time, the chip testing system can obtain four interval ranges. For example, Figure 4 The first normal distribution curve shown in FIG. 4A has a first mean value of 1.6. The values of three standard deviation values to the left and right sides of the first mean value are 1.6285 (+3Sigma, shown by the straight line 420) and 1.5489 (-3Sigma, shown by the straight line 430), respectively. The values of six standard deviation values (±6Sigma) to the left and right sides of the first mean value are 1.55 and 1.65, respectively. At this time, the four interval ranges are 1.5489~1.55, 1.6285~1.65, 1.6~1.6285, and 1.55~1.6, respectively. It can be understood that the values of six standard deviation values to the left and right sides of the first mean value can be the same as or different from the test limit value. For example, Figure 4 The upper limit value in the above interval range is 1.64, which is less than the sum of the first mean value and six standard deviation values. The lower limit value is 1.56, which is greater than the difference between the first mean value and six standard deviation values.

[0131] Step (3), the chip testing system determines the first chip corresponding to the test value in the preset interval range in the test values of the plurality of first chips as a potential defective chip.

[0132] The preset interval range is one of the multiple interval ranges. The chip detection system selects, by using the data classification and analysis device, an interval range farthest from the first mean value from the multiple interval ranges as the preset interval range, and determines a first chip corresponding to a test value in the preset interval range from the multiple test values of the multiple first chips as a potential defective chip.

[0133] As an example, the preset interval range can be μ+3σ~μ+6σ and μ-6σ~μ-3σ, where μ represents the first mean value and σ represents the standard deviation value.

[0134] In the technical solutions of steps (1) to (3), the determined first normal distribution curve includes a first mean value and a standard deviation value determined based on at least part of the test values and the test limit value. The first mean value and the standard deviation value in the first normal distribution curve can reflect the average reference of the test values of the first chips that pass the test and the dispersion degree between the test values and the average reference under the specific test limit value. In this way, the first normal distribution curve can describe the difference degree between at least part of the test values of the multiple first chips and the first mean value. In this way, each interval range obtained by interval division of the horizontal coordinates of the first normal distribution curve with the first mean value as the reference and the standard deviation value as the interval is a test value set having a certain difference from the first mean value. In this way, the first chip corresponding to the test value in the preset interval range is a potential defective chip that may have a chip failure problem close to the test limit value. In this way, the potential defective chip can be quickly and accurately determined through interval division of the determined normal distribution curve.

[0135] In step S503, the chip detection system obtains a chip test graph corresponding to each potential defective chip.

[0136] The chip test graph corresponding to any potential defective chip includes the test values of one or more chips and the test value of the potential defective chip. When the chip detection system obtains the multiple first chips, the chip detection system also obtains the identification of the first chips. The chip detection system queries the identification of each potential defective chip from the multiple chip test graphs output by the automatic detection subsystem, and determines a chip test graph having the identification as the chip test graph corresponding to the potential defective chip. The identification of the chip can be a serial number of the chip, coordinate information of the chip in a wafer, an encoding of the chip, or a name of the chip, and the like, which is not specifically limited in the embodiments of the present application.

[0137] In step S504, the chip detection system determines a margin value of any potential defective chip according to the chip test graph corresponding to the potential defective chip.

[0138] The chip detection system utilizes the chip detection device to find the chips adjacent to any potential defective chip in the chip test diagram corresponding to the potential defective chip, and determines the test values of the adjacent chips under the test item to which the test value of the potential defective chip belongs in the chip test diagram corresponding to the potential defective chip. Then the chip detection device calculates the average value between the test value of the potential defective chip and the determined test values, and calculates the difference between the test value of the potential defective chip and the average value, and determines the difference as the margin value.

[0139] In some embodiments, the margin value of any potential defective chip is determined according to the chip test diagram corresponding to the potential defective chip, including the following steps (1) to (2):

[0140] Step (1), the chip detection system determines the detection area according to the chip test diagram corresponding to any potential defective chip.

[0141] The detection area includes any potential defective chip and at least one chip adjacent to the potential defective chip in the chip test diagram. The at least one chip adjacent to the potential defective chip in the chip test diagram can be at least one of the chips adjacent to the potential defective chip on the left and right, the chips adjacent to the potential defective chip above and below, and the chips adjacent to the potential defective chip diagonally. The chip detection system utilizes the chip detection device to query at least one chip adjacent to the potential defective chip in the chip test diagram corresponding to the potential defective chip, and determines the area composed of the area where the queried chip is located and the area where the potential defective chip is located as the detection area.

[0142] In some embodiments, the detection area is determined according to the chip test diagram corresponding to any potential defective chip, including that the chip detection system determines the chips adjacent to any potential defective chip based on the coordinate information of each chip in the chip test diagram corresponding to the potential defective chip, and the detection area is composed of the potential defective chip and the determined area.

[0143] The coordinate information is used to indicate the position of the chip in the wafer. The chip detection system utilizes the chip detection device to determine the area of each chip in the chip test diagram based on the coordinate information of each chip in the chip test diagram corresponding to any potential defective chip, and then finds the area adjacent to the area where the potential defective chip is located in the chip test diagram, so that the chips on the area found in this way are the chips adjacent to the potential defective chip, and the area where the potential defective chip and the adjacent chips are located constitutes the detection area.

[0144] Thus, based on the coordinate information of each chip in the chip detection image, at least one chip adjacent to any potential defective chip can be quickly determined, so as to obtain a detection area including the potential defective chip and at least one chip adjacent to the potential defective chip, and the potential defective chip that has passed the test is connected with the chips around the potential defective chip, thereby facilitating subsequent determination of a reasonable and accurate margin value.

[0145] As an example, the adjacent relationship between the area where any potential defective chip is located and the area where the chips around the potential defective chip are located can be at least one of left-right adjacent, up-down adjacent, and diagonal adjacent. For example, as shown in FIG. 6A, a chip test image corresponding to a certain potential defective chip is shown, the area of the potential defective chip in the chip test image is a rectangle 610 framed in the center of FIG. 6A (i.e., a central area 611 in the partial enlarged view of the rectangle 610 in FIG. 6A), and it is determined that there are 8 areas that are left-right adjacent, up-down adjacent, and diagonal adjacent to the area of the potential defective chip in the chip test image. Therefore, the determined detection area is a 3*3 rectangle 610 framed in FIG. 6A. Figure 6 Figure 6 Figure 6 Figure 6 It can be understood that if any potential defective chip is located at the edge of the chip test image, the areas adjacent to the area of the potential defective chip are not symmetrical with respect to the area of the potential defective chip, and the determined detection area can be an irregular geometric area. It should be noted that Figure 6

[0146] As another example, the chip detection system draws a circle with the position of any potential defective chip as the center and a preset length as the radius in the chip test image corresponding to the potential defective chip, determines the areas of the chips located in the circle as the detection area.

[0147] Step (2), the chip detection system determines a margin value of any potential defective chip according to the test values of each chip in the detection area.

[0148] The chip detection system calculates the average of the test values of each chip in the detection area by using the chip detection device, and calculates the difference between the test value of any potential defective chip and the average, and determines the difference as the margin value.

[0149] In some embodiments, the determination of the margin value of any potential defective chip according to the test values of each chip in the detection area includes: the chip detection system determines a second average of the test values of each chip in the detection area except any potential defective chip; and the chip detection system determines the difference between the test value of any potential defective chip and the second average as the margin value. For example, as shown in FIG. 6B, a chip test image corresponding to a certain potential defective chip is shown, the area of the potential defective chip in the chip test image is a rectangle 620 framed in the center of FIG. 6B (i.e., a central area 621 in the partial enlarged view of the rectangle 620 in FIG. 6B), and it is determined that there are 8 areas that are left-right adjacent, up-down adjacent, and diagonal adjacent to the area of the potential defective chip in the chip test image. Therefore, the determined detection area is a 3*3 rectangle 620 framed in FIG. 6B. Figure 6 ​​​​As shown, the test value of a potential defective chip is 1.2. There are 8 chips adjacent to the potential defective chip. The second mean of the test values ​​of each chip in the determined inspection area except for any potential defective chip is (1.2+1.1+1.2+1.3+1.4+1.2+1.4) / 8=1.2375. Figure 6 The margin value determined is 1.2-1.2375=-0.0375, that is, Figure 6 The calculation margin in .

[0150] In this way, the second mean value calculated based on the test values ​​of each chip in the inspection area, excluding any potentially defective chip, can reflect the average benchmark of the test values ​​of the other chips in the inspection area. In this way, the difference between the test value of any potentially defective chip and the second mean value can accurately reflect the degree of difference in the test values ​​between the potentially defective chip and the other chips in the inspection area. Therefore, based on the margin value, it is possible to accurately determine whether the potentially defective chip is a chip that may cause chip failure.

[0151] Step S505. See Figure 3 Step S304 in the illustrated embodiment will not be described in detail here.

[0152] For example, combined Figure 6 as well as Figure 7 , set the preset threshold to 5% of the average of the upper and lower limits, that is, Figure 6 The PAT standard is 5%. For a large number of chips that have passed the test, that is, the first chips that have passed the test, after determining at least one potential defective chip, each potential defective chip is tested. Figure 7 The PAT calculation shown in the figure is that the chip detection system uses the chip detection device to determine the margin value of any potential defective chip and compares the margin value with the preset threshold value to determine whether any potential defective chip passes the PAT calculation. If the margin value of a potential defective chip with a test value of 1.2 is -0.0375, which is less than or equal to the PAT standard, then the potential defective chip is determined to have passed the PAT calculation, that is, Figure 6 PAT in: Pass. Figure 7 As shown, the chip inspection system's re-marking engine will set the test result Bin (also known as classification, update, or marking) of the potentially defective chip to Pass, leaving the test result of the potentially defective chip unchanged. If the potentially defective chip fails the PAAT calculation, the re-marking engine will set the test result Bin of the potentially defective chip to Fail, updating the test result of the potentially defective chip to Fail.

[0153] In the embodiment of the present application, a chip test map corresponding to each potentially defective chip is obtained, and based on the chip test map, which includes test values ​​of one or more chips and the test values ​​of the potentially defective chip, a margin value for each potentially defective chip is determined. By correlating the margin value with the test values ​​of other chips in the chip test map, the degree of difference between the test values ​​of the potentially defective chip and those of adjacent chips can be accurately reflected. This allows for accurate identification and elimination of chips that are likely to fail, thereby reducing the probability of chip failure and improving the reliability and accuracy of chip testing.

[0154] Figure 8 This is a schematic diagram of the structure of an electronic device provided in one embodiment of the present application. Figure 8 As shown, the electronic device 8 of this embodiment includes: at least one processor 80 ( Figure 8 Only one is shown in the figure) a processor, a memory 81, and a computer program 82 stored in the memory 81 and executable on the at least one processor 80, wherein the processor 80 implements the steps of any of the above-mentioned chip detection method embodiments when executing the computer program 82.

[0155] The electronic device 8 can be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The electronic device can include, but is not limited to, a processor 80 and a memory 81. Those skilled in the art will understand that Figure 8 This is merely an example of the electronic device 8 and does not constitute a limitation on the electronic device 8 . The electronic device 8 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0156] The processor 80 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor may be a microprocessor or any conventional processor.

[0157] The memory 81 may, in some embodiments, be an internal storage unit of the electronic device 8, such as a hard disk or a memory of the electronic device 8. The memory 81 may, in other embodiments, also be an external storage device of the electronic device 8, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, or the like, equipped on the electronic device 8. Further, the memory 81 may also include both an internal storage unit and an external storage device of the electronic device 8. The memory 81 is used to store an operating system, application programs, a BootLoader, data, and other programs, such as program codes of the computer program, and the like. The memory 81 may also be used to temporarily store data that has been output or is to be output.

[0158] corresponding to the chip detection method described in the above embodiments, Figure 9 A structure block diagram of the apparatus provided by the embodiments of the present application is shown, and only parts related to the embodiments of the present application are shown for ease of illustration.

[0159] With reference to Figure 9 The apparatus comprises:

[0160] The acquisition module 910 is configured to acquire a test value of each first chip in a plurality of first chips that pass the test, the plurality of first chips corresponding to the same test limit value;

[0161] The first determination module 920 is configured to determine at least one potentially defective chip from the plurality of first chips according to the test values of the plurality of first chips and the test limit value;

[0162] The second determination module 930 is configured to determine a margin value of each potentially defective chip, the margin value indicating a difference degree between any potentially defective chip and a test value of each chip of at least one chip adjacent to the potentially defective chip in a chip test graph; the chip test graph comprises test values of a plurality of chips, and the plurality of chips comprise at least one potentially defective chip;

[0163] The third determination module 940 is configured to re-determine a test result of any potentially defective chip according to a size relationship between the margin value and a preset threshold.

[0164] In some embodiments, the second determination module comprises:

[0165] The acquisition unit is configured to acquire a chip test graph corresponding to each potentially defective chip, the chip test graph corresponding to any potentially defective chip comprising test values of one or more chips and a test value of the potentially defective chip;

[0166] The first determining unit is configured to determine the margin value of any potential defective chip according to the chip test map corresponding to the potential defective chip.

[0167] In some embodiments, the first determining unit is further configured to determine a to-be-inspected region in the chip test map corresponding to any potential defective chip, the to-be-inspected region including the potential defective chip and at least one chip adjacent to the potential defective chip in the chip test map.

[0168] The margin value of any potential defective chip is determined according to the test value of each chip in the to-be-inspected region.

[0169] In some embodiments, the first determining module includes:

[0170] The second determining unit is configured to determine a first normal distribution curve according to the test limit value and the plurality of test values, the first normal distribution curve including at least part of the plurality of test values, a first mean value and a standard deviation value determined based on the at least part of the test values and the test limit value.

[0171] The interval dividing unit is configured to divide the abscissa of the first normal distribution curve into a plurality of interval ranges based on the first mean value as a reference and the standard deviation value as an interval, the abscissa being used to indicate the at least part of the test values.

[0172] The third determining unit is configured to determine a first chip corresponding to a test value in the test values of the plurality of first chips and located in a preset interval range as a potential defective chip, the preset interval range being one of the plurality of interval ranges.

[0173] In some embodiments, the second determining unit is further configured to determine an ideal mean value according to the upper limit value and the lower limit value.

[0174] The plurality of test values are subjected to normal distribution analysis to obtain an actual normal distribution curve, the actual normal distribution curve including the plurality of test values and an actual mean value determined based on the plurality of test values.

[0175] If a deviation between the actual mean value and the ideal mean value is within a preset range, the actual normal distribution curve is determined as the first normal distribution curve.

[0176] If the deviation between the actual mean value and the ideal mean value exceeds the preset range, the plurality of test values are subjected to a processing operation to update the actual normal distribution curve and the actual mean value, so that a deviation between the updated actual mean value and the ideal mean value is within the preset range. The processing operation includes deleting at least one test value in the plurality of test values.

[0177] The updated actual normal distribution curve is determined as the first normal distribution curve.

[0178] In some embodiments, the first determining unit is further configured to determine a second average value of the test values of each chip in the to-be-inspected region except for any potential defective chip.

[0179] The difference between the test value of any potential defective chip and the second average value is determined as the margin value.

[0180] In some embodiments, the first determining unit is further configured to determine, based on coordinate information of each chip in a chip test image corresponding to any potential defective chip, chips adjacent to the potential defective chip, and a region where the potential defective chip and the determined chips are located as the to-be-inspected region.

[0181] In some embodiments, the obtaining module is further configured to obtain, from the data classification analysis device, at least one set of chip combinations, a plurality of chips in a same chip combination having a same test limit value, different chip combinations corresponding to different test limit values, and all chips in the at least one set of chip combinations being chips that pass the test; and the plurality of first chips belong to any chip combination.

[0182] As an example, the obtaining module, the first determining module, and the second determining module can be configured in the data classification analysis device, and the third determining module can be configured in the chip detection device.

[0183] It should be noted that the information interaction between the above-described devices / units, the execution process, and the like, are based on the same concept as the method embodiments of the present application, and specific functions and technical effects brought by the same can be referred to the method embodiments part, which will not be described herein.

[0184] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is exemplified, and in actual applications, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit. In addition, the specific names of the functional units and modules are only for the convenience of mutual distinction, and do not limit the protection scope of the present application. The specific working process of the units and modules in the system can be referred to the corresponding process in the foregoing method embodiments, which will not be described herein.

[0185] The embodiments of the present application also provide a computer readable storage medium storing a computer program, and the computer program is executed by a processor to implement the steps in each of the above method embodiments.

[0186] The embodiment of the present application provides a computer program product, when the computer program product is run on a mobile terminal, the mobile terminal is caused to execute the steps in the above-mentioned various method embodiments.

[0187] The integrated unit, if in the form of a software function unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on such understanding, the present application can implement all or part of the processes in the above-mentioned embodiment methods, which can be completed by instructing related hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by a processor. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms. The computer-readable medium at least includes any entity or device capable of carrying the computer program code to the photographing device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunications signal and a software distribution medium. For example, a U disk, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, the computer-readable medium cannot be an electrical carrier signal and a telecommunications signal.

[0188] In the above-mentioned embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0189] Those skilled in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in the present application can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0190] In the embodiments provided by the present application, it should be understood that the disclosed apparatus / network device and method can be implemented in other manners. For example, the embodiments of the apparatus / network device described above are merely illustrative. For example, the division of the modules or units is merely logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0191] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0192] The above-described embodiments are merely used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalent replacements; and these modifications or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A chip detection method characterized by, The method comprises: obtaining a test value of each of a plurality of first chips that pass a test, the plurality of first chips corresponding to a same test limit value, the test value being a value corresponding to the first chip after a test item, the test item comprising at least one of a resistance test, an open / short circuit test or a driving output test; statistically determining a deviation between the test value of the first chip and the test limit value, and regarding a first chip corresponding to a test value greater than or equal to a specified value as a potential defective chip to obtain at least one potential defective chip; obtaining a chip test map in which the potential defective chip is located, the chip test map comprising test values of a plurality of chips, the plurality of chips comprising at least one potential defective chip; for each potential defective chip, finding at least one adjacent chip located around the potential defective chip in the chip test map in which the potential defective chip is located; determining a mean value between test values of adjacent chips of the potential defective chip; regarding a difference between the test value of the potential defective chip and the determined mean value as a margin value of the potential defective chip, the margin value indicating a difference degree between the test value of the potential defective chip and each adjacent chip thereof; re-determining a test result of any potential defective chip according to a size relationship between the margin value and a preset threshold value.

2. The method of claim 1, wherein, The statistical determination of the deviation between the test value of the first chip and the test limit value, and the regarding of the first chip corresponding to the test value greater than or equal to the specified value as the potential defective chip to obtain at least one potential defective chip comprises: determining a first normal distribution curve according to the test limit value and a plurality of test values, the first normal distribution curve comprising at least part of the test values in the plurality of test values, a first mean value and a standard deviation value determined based on at least part of the test values and the test limit value; performing interval division on an abscissa of the first normal distribution curve to obtain a plurality of interval ranges, the abscissa being used to indicate at least part of the test values, with the first mean value as a reference and the standard deviation value as an interval; determining the first chip corresponding to the test value in the plurality of test values of the first chip in a preset interval range as the potential defective chip, the preset interval range being one interval range in the plurality of interval ranges.

3. The method of claim 2, wherein, The test limit value comprises an upper limit value and a lower limit value, and the determination of the first normal distribution curve according to the test limit value and the plurality of test values comprises: determining an ideal mean value according to the upper limit value and the lower limit value; performing normal distribution analysis on the plurality of test values to obtain an actual normal distribution curve, the actual normal distribution curve comprising the plurality of test values and an actual mean value determined based on the plurality of test values; if a deviation between the actual mean value and the ideal mean value is within a preset range, regarding the actual normal distribution curve as the first normal distribution curve. If the deviation between the actual mean value and the ideal mean value exceeds the preset range, a processing operation is performed on the test values to update the actual normal distribution curve and the actual mean value, so that the deviation between the updated actual mean value and the ideal mean value is within the preset range; the processing operation includes deleting at least one of the test values; The updated actual normal distribution curve is determined as the first normal distribution curve.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: At least one chip combination is obtained from the data classification analysis device, the chips in the same chip combination have the same test limit value, the test limit values of different chip combinations are different, and all the chips in the at least one chip combination are test-passing chips; the first chips belong to any of the chip combinations.

5. A chip testing apparatus characterized by comprising: The device includes: An acquisition module is configured to acquire a test value of each of the first chips that pass the test, the first chips correspond to the same test limit value, the test value is a value corresponding to the first chip after a test item, and the test item includes at least one of a resistance test, an open / short circuit test, or a driving output test; A first determination module is configured to determine a deviation between the test value of the first chip and the test limit value, regard the first chip corresponding to a test value greater than or equal to a specified value as a potential defective chip, and obtain at least one potential defective chip; A second determination module is configured to acquire a chip test graph in which each of the potential defective chips is located, the chip test graph includes test values of a plurality of chips, and the plurality of chips include at least one potential defective chip; for each of the potential defective chips, at least one adjacent chip located around the potential defective chip is found in the chip test graph in which the potential defective chip is located; a mean value between test values of the adjacent chips of the potential defective chip is determined; a difference between the test value of the potential defective chip and the determined mean value is regarded as a margin value of the potential defective chip, and the margin value indicates a difference degree between the test value of the potential defective chip and each of the adjacent chips of the potential defective chip; A third determination module is configured to re-determine a test result of any of the potential defective chips according to a size relationship between the margin value and a preset threshold.

6. A chip detection system, including: An automatic detection subsystem is configured to respectively test a plurality of to-be-tested chips based on at least one test item, and output test information of each of the to-be-tested chips under the at least one test item, the test information including a test value, a test result, and a test limit value corresponding to the to-be-tested chip under each of the test items, the test value is a value corresponding to the chip after the test item, and the test item includes at least one of a resistance test, an open / short circuit test, or a driving output test; a data classification analysis device connected with the automatic detection subsystem, configured to count the deviation between the test value of each chip and the test limit value, and take the chip corresponding to the test value with a deviation greater than or equal to a specified value as a potential defective chip, and obtain at least one potential defective chip; a chip detection device, configured to obtain a chip test map in which the potential defective chip is located, the chip test map comprising test values of a plurality of chips, and the plurality of chips comprising at least one potential defective chip; determine the mean value between the test values of the adjacent chips of the potential defective chip, and take the difference between the test value of the potential defective chip and the determined mean value as a margin value of the potential defective chip, the margin value indicating the difference between the test value of the potential defective chip and each adjacent chip thereof; a re-marking engine, configured to re-determine the test result of any potential defective chip according to the size relationship between the margin value output by the chip detection device and a preset threshold.

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