A TIA input offset voltage calibration method and calibration circuit

Abstract

The present invention discloses a TIA input offset voltage calibration method and calibration circuit, the circuit includes a TIA, the output end of the TIA includes a load output stage and a calibration output stage; the load output stage is connected to the calibration input end of the TIA by a feedback circuit; switches are provided on the calibration output stage and the load output stage, during calibration, the switch on the calibration output stage is closed and the switch on the load output stage is disconnected, so that the load output stage is an open circuit and the calibration output stage is a passage; the output end of the calibration output stage is connected to a comparator, so that the output voltage of the calibration output stage is compared with a standard voltage through the comparator; the output end of the comparator is connected to the TIA. In the present invention, the switch on the feedback circuit is cancelled, and a special calibration output stage is provided at the output end of the TIA. Since the switch on the feedback circuit is cancelled, the resistance value on the feedback circuit will not change, thereby avoiding the generation of errors.

Description

Technical Field

[0001] The present invention belongs to the technical field of transimpedance amplifiers, and in particular to a TIA input offset voltage calibration method and a calibration circuit. Background Art

[0002] A transimpedance amplifier (TIA) is an electronic device that converts an input current signal into a corresponding voltage output signal. It is widely used in fields such as photoelectric detection, sensor interface and communication systems, optoelectronic hybrid computing systems, etc. to amplify and measure weak current signals. Transimpedance amplifiers play an important role in the field of electronics and can improve the sensitivity and accuracy of signal processing.

[0003] In a measurement system, the input offset voltage of a transimpedance amplifier can cause errors in the measurement results. Therefore, the input offset voltage needs to be calibrated to reduce the measurement error.

[0004] During calibration, the feedback circuit of the TIA should be disconnected so that the TIA circuit works in an open-loop state. Therefore, a switch is added to the feedback circuit to disconnect the feedback circuit in the calibration mode so that the TIA meets the above requirements. Figure 1 shown.

[0005] However, since the switch itself has a certain resistance, during calibration, the switch is in an open state and is no longer within the calibration range. During normal operation, the switch is closed and connected to the feedback circuit, which causes the feedback circuit parameters to change, causing other measurement errors. Summary of the invention

[0006] The object of the present invention is to provide a TIA input offset voltage calibration method and calibration circuit, which partially solve or alleviate the above-mentioned deficiencies in the prior art and eliminate the influence of switches in the feedback circuit.

[0007] In order to solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions:

[0008] A first aspect of the present invention is to provide a TIA input offset voltage calibration circuit, comprising a TIA, wherein the input end of the TIA comprises a normal input end and a calibration input end; the output end of the TIA comprises a load output stage and a calibration output stage; the load output stage is connected to the calibration input end of the TIA by a feedback circuit; and the feedback circuit is connected only with a feedback resistor;

[0009] During normal operation, the load output stage is connected and the calibration output stage is disconnected; during calibration, the load output stage is disconnected and the calibration output stage is connected;

[0010] The output terminal of the calibration output stage is connected to a comparator, so that the output voltage of the calibration output stage is compared with a standard voltage through the comparator; and the output terminal of the comparator is connected to the TIA.

[0011] As an improvement, switches are provided on both the calibration output stage and the load output stage. During normal operation, the switch on the calibration output stage is opened and the switch on the load output stage is closed, so that the load output stage is connected and the calibration output stage is open. During calibration, the switch on the calibration output stage is closed and the switch on the load output stage is opened, so that the load output stage is open and the calibration output stage is connected.

[0012] As an improvement, the comparator includes a first input terminal and a second input terminal; the output terminal of the calibration output stage is connected to the first input terminal of the comparator, and the second input terminal of the comparator is externally connected to a standard voltage.

[0013] As an improvement, the TIA includes two outputs, which are respectively connected to the input ends of the first group of field effect transistors and the input ends of the second group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors form the load output stage and the calibration output stage in parallel.

[0014] As an improvement, the first group of field effect transistors includes a first field effect transistor MOS-1 and a second field effect transistor MOS-2, whose gates G are respectively connected to two outputs of the TIA, wherein the source S of the first field effect transistor MOS-1 is externally connected to a voltage through a first switch SW1, the source S of the second field effect transistor MOS-2 is grounded through a second switch SW2, and the drain D of the first field effect transistor MOS-1 is connected to the drain D of the second field effect transistor MOS-2 as a load output terminal externally connected to a load. Preferably, the common point where the drain D of the first field effect transistor MOS-1 and the drain D of the second field effect transistor MOS-2 are connected is also connected to the calibration input terminal of the TIA through the feedback resistor.

[0015] As an improvement, the second group of field effect transistors includes a third field effect transistor MOS-3 and a fourth field effect transistor MOS-4, whose gates G are respectively connected to the two outputs of the TIA, wherein the source S of the third field effect transistor MOS-3 is externally connected to a voltage through a third switch SW3, the source S of the fourth field effect transistor MOS-4 is grounded through a fourth switch SW4, and the drain D of the third field effect transistor MOS-3 is connected to the drain D of the fourth field effect transistor MOS-4 as a calibration output stage connected to the first input terminal of the comparator.

[0016] The present invention also provides a TIA input offset voltage calibration method, which is applied to the above TIA input offset voltage calibration circuit, comprising:

[0017] Disconnecting a switch on a load output stage in the TIA input offset voltage calibration circuit so that the load output stage is in an open circuit state; and at the same time, closing a switch on a calibration output stage in the TIA input offset voltage calibration circuit so that the calibration output stage is in a circuit state;

[0018] By connecting the input voltage Vcm to both the calibration input terminal and the normal input terminal of the TIA, and comparing the calibration output voltage Vout_cal of the calibration output stage with the preset standard voltage Vref;

[0019] The difference between the calibrated output voltage Vout_cal and the standard voltage Vref is input into the TIA for adjustment, so that the calibrated output voltage Vout_cal approaches the standard voltage Vref.

[0020] As an improvement, the difference between the calibrated output voltage Vout_cal and the standard voltage Vref is input into the TIA for adjustment through one of the binary method, gradient descent method, genetic algorithm, and particle swarm optimization method, so that the calibrated output voltage Vout_cal approaches the standard voltage Vref.

[0021] As an improvement, the step of inputting the difference between the calibrated output voltage Vout_cal and the standard voltage Vref into the TIA for adjustment by binary division so that the calibrated output voltage Vout_cal approaches the standard voltage Vref specifically includes:

[0022] Comparing the calibrated output voltage Vout_cal with the standard voltage Vref,

[0023] If the calibrated output voltage Vout_cal is higher than the standard voltage Vref, adjusting the TIA parameters so that the calibrated output voltage Vout_cal is reduced;

[0024] If the calibrated output voltage Vout_cal is lower than the standard voltage Vref, adjusting the TIA parameters so that the calibrated output voltage Vout_cal increases;

[0025] Repeat the above steps until the adjustment times reach the set value;

[0026] The current adjustment step size for adjusting the TIA parameters is 1 / 2 of the previous adjustment step size.

[0027] As an improvement, the set value of the adjustment times is adjusted according to the circuit design accuracy.

[0028] Beneficial effect: In the existing calibration circuit, during normal operation, the switch on the feedback circuit is closed, so the resistance value on the feedback circuit is the sum of the resistance value of the feedback resistor and the switch resistance value. During the calibration process, the switch on the feedback circuit is in an open state, making the feedback circuit open circuit. That is, the calibration process does not cover the switch on the feedback circuit, and during normal operation, the resistance value of switch SW5 will change the resistance value of the feedback circuit, thereby causing a measurement error. Especially when it is applied to a photonic computing chip or an optoelectronic hybrid computing system for high-precision and high-speed computing, such an error will greatly reduce the accuracy of the link, thereby reducing the accuracy of the photonic computing chip or the optoelectronic hybrid computing system.

[0029] In the present invention, the switch SW5 on the feedback circuit is cancelled, and a special calibration output stage is set at the output end of the TIA. The calibration output stage and the load output stage conventionally used by the TIA are both connected to the output end of the TIA, and the calibration output stage is in a disconnected state during normal operation and is only connected to the circuit during calibration. When the calibration output stage is connected to the circuit, the load output stage is disconnected from the output end of the TIA, and the feedback circuit connected to the load output stage is also disconnected, entering the calibration state. Since the switch SW5 on the feedback circuit is cancelled, the resistance value on the feedback circuit will not change, thereby avoiding the generation of other measurement errors. In particular, when it is applied to a photonic computing chip or an optoelectronic hybrid computing system for high-precision and high-speed computing, the accuracy of the link is greatly improved, thereby improving the accuracy of the photonic computing chip or the optoelectronic hybrid computing system.

[0030] In addition, in the present invention, an algorithm such as a binary search method can be used to adjust TIA parameters so that the output voltage of the TIA approaches the standard voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative labor.

[0032] Figure 1 A schematic diagram of an existing TIA input offset voltage calibration circuit;

[0033] Figure 2 Schematic diagram of a TIA input offset voltage calibration circuit in Embodiment 1 of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0035] Herein, suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings by themselves. Therefore, "module", "component" or "unit" can be used mixedly.

[0036] In this document, the terms "upper", "lower", "inner", "outer", "front", "back", "one end", "the other end" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0037] In this document, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] Herein "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] Herein, "plurality" means two or more than two, ie, it includes two, three, four, five, etc.

[0040] Embodiment 1: Prior art Chinese patent application CN202210885427.9 discloses a current calibration circuit and method for a transimpedance amplifier chip. The calibration circuit includes a detection resistor, one end of which is connected to the received signal strength indication pin of the transimpedance amplifier chip and the other end is grounded; a comparator, whose two input ends are respectively connected to the received signal strength indication pin of the transimpedance amplifier chip and the bandgap reference voltage VBG inside the transimpedance amplifier chip; a binary search logic module, which is connected to the output end of the comparator, and is configured to output an n-bit binary code according to the comparison result of the comparator, and the n-bit binary code is used to control the n-bit encoding control end of the current source array to be calibrated; a calibration control switch, one end of which is connected to the positive electrode of the current source array to be calibrated, and the other end is connected to the PD cathode bias pin of the transimpedance amplifier chip; the negative electrode of the current source array to be calibrated is grounded. The current calibration circuit described in the present invention calibrates the internal reference current of the transimpedance amplifier chip under the premise of adapting to the conventional ROSA package.

[0041] The above-mentioned prior art is actually to calibrate the internal reference current of the transimpedance amplifier chip, which cannot eliminate the influence of the switch on the feedback circuit during the input offset voltage calibration process.

[0042] In the present invention, input offset voltage is an important parameter in TIA, which refers to the voltage difference that must be applied between the two input terminals (inverting input and non-inverting input) of TIA in order to make the output voltage of TIA zero in the absence of any input signal.

[0043] In order to eliminate the influence of the feedback circuit switch in the existing TIA input offset voltage calibration circuit, such as Figure 2 As shown, the present invention provides a TIA input offset voltage calibration circuit, including a TIA, wherein the input end of the TIA includes a normal input end and a calibration input end; the output end of the TIA includes a load output stage and a calibration output stage; wherein the load output stage is connected to the calibration input end of the TIA using a feedback circuit; and only a feedback resistor is connected to the feedback circuit.

[0044] In some embodiments, switches are provided on both the calibration output stage and the load output stage. During normal operation, the switch on the calibration output stage is opened and the switch on the load output stage is closed, so that the load output stage is connected and the calibration output stage is open. During calibration, the switch on the calibration output stage is closed and the switch on the load output stage is opened, so that the load output stage is open and the calibration output stage is connected. Furthermore, the output end of the calibration output stage is connected to a comparator, so that the output voltage of the calibration output stage is compared with a standard voltage through the comparator. The output end of the comparator is connected to the TIA.

[0045] like Figure 1In the conventional calibration circuit shown, in normal operation, the switch SW5 on the feedback circuit is closed, so the resistance value on the feedback circuit is the sum of the resistance value of the feedback resistor and the switch resistance value. During the calibration process, the switch SW5 on the feedback circuit is in an open state, making the feedback circuit open circuit. That is, during Figure 1 In the prior art shown, the calibration process does not cover the switch SW5, and during normal operation, the resistance value of the switch SW5 will change the resistance value of the feedback circuit, thereby causing a measurement error. However, when this is applied to an application scenario with high precision requirements, especially in an optoelectronic hybrid system with very high computational precision requirements (e.g., an optoelectronic hybrid system with a large-scale photon computing matrix), the impact of this measurement error will seriously affect the computational precision.

[0046] In the present invention, the switch SW5 on the feedback circuit is cancelled, and a special calibration output stage is set at the output end of the TIA. The calibration output stage and the load output stage conventionally used by the TIA are both connected to the output end of the TIA, and the calibration output stage is disconnected during normal operation and is only connected to the circuit during calibration. When the calibration output stage is connected to the circuit, the load output stage is disconnected from the output end of the TIA, and the feedback circuit connected to the load output stage is also disconnected, entering the calibration state.

[0047] Since the switch SW5 on the feedback circuit is cancelled, the resistance value on the feedback circuit will not change, thereby avoiding the generation of other measurement errors.

[0048] More specifically, the comparator in this embodiment includes a first input terminal and a second input terminal; the output terminal of the calibration output stage is connected to the first input terminal of the comparator, and the second input terminal of the comparator is externally connected to a standard voltage.

[0049] The specific structure of the calibration output stage and the load output stage is as follows: TIA includes two outputs, and the two outputs are respectively connected to the input ends of the first group of field effect transistors and the input ends of the second group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors form a parallel load output stage and a calibration output stage.

[0050] In some embodiments, the specific structure of the load output stage includes: a first group of field effect transistors includes a first field effect transistor MOS-1 and a second field effect transistor MOS-2, whose gates G are respectively connected to two outputs of the TIA, wherein the source S of the first field effect transistor MOS-1 is externally connected to a voltage through a first switch SW1, the source S of the second field effect transistor MOS-2 is grounded through a second switch SW2, and the drain D of the first field effect transistor MOS-1 is connected to the drain D of the second field effect transistor MOS-2 as an external load at the load output terminal; and the common point where the drain D of the first field effect transistor MOS-1 and the drain D of the second field effect transistor MOS-2 are connected is connected to the calibration input terminal of the TIA through the above-mentioned feedback resistor.

[0051] In some embodiments, the specific structure of the calibration output stage includes: the second group of field effect transistors includes a third field effect transistor MOS-3 and a fourth field effect transistor MOS-4, whose gates G are respectively connected to the two outputs of the TIA, wherein the source S of the third field effect transistor MOS-3 is externally connected to a voltage through a third switch SW3, the source S of the fourth field effect transistor MOS-4 is grounded through a fourth switch SW4, and the drain D of the third field effect transistor MOS-3 is connected to the drain D of the fourth field effect transistor MOS-4 as a calibration output stage connected to the first input terminal of the comparator.

[0052] Embodiment 2: The present invention also provides a TIA input offset voltage calibration method, which is applied to the above-mentioned TIA input offset voltage calibration circuit, comprising:

[0053] S1 disconnects the switch on the load output stage in the TIA input offset voltage calibration circuit, so that the load output stage is in an open circuit state; at the same time, it closes the switch on the calibration output stage in the TIA input offset voltage calibration circuit, so that the calibration output stage is in a circuit state.

[0054] See also Figure 2 During calibration, the switches SW1 and SW2 on the load output stage are disconnected to disconnect the entire load output stage from the TIA output terminal, and the feedback circuit is also disconnected from the TIA. The switches SW3 and SW4 on the calibration output stage are closed to connect the calibration output stage to the TIA output terminal.

[0055] S2 connects the input voltage Vcm to both the calibration input terminal and the normal input terminal of the TIA, and compares the calibration output voltage Vout_cal of the calibration output stage with the standard voltage Vref.

[0056] After the voltage Vcm is input to the calibration input terminal and the normal input terminal, the calibration output voltage Vout_cal will be output at the TIA calibration output stage. The calibration output voltage Vout_cal is then input to the first input terminal of the comparator. The second input terminal of the comparator is externally connected to the standard voltage Vref, and the calibration output voltage Vout_cal can be compared with the standard voltage Vref through the comparator.

[0057] S3 inputs the difference between the calibrated output voltage Vout_cal and the standard voltage Vref into the TIA for adjustment, so that the calibrated output voltage Vout_cal approaches the standard voltage Vref.

[0058] The purpose of calibration is to make the output voltage of TIA equal to the standard voltage under ideal conditions. Of course, it is difficult to make the output voltage of TIA completely equal to the standard voltage in actual calibration, and it can only be gradually approached to the standard voltage. Through one of the binary method, gradient descent method, genetic algorithm, and particle swarm optimization method, the difference between the calibrated output voltage Vout_cal and the standard voltage Vref is input into TIA for adjustment, so that the calibrated output voltage Vout_cal approaches the standard voltage Vref. In this embodiment, the binary method is used for adjustment, and the specific steps include:

[0059] S31 compares the calibrated output voltage Vout_cal with the standard voltage Vref. If the calibrated output voltage Vout_cal is higher than the standard voltage Vref, the TIA parameters are adjusted to reduce the calibrated output voltage Vout_cal. If the calibrated output voltage Vout_cal is lower than the standard voltage Vref, the TIA parameters are adjusted to increase the calibrated output voltage Vout_cal.

[0060] In this embodiment, the TIA parameter that affects the calibrated output voltage Vout_cal may be the number of MOS transistors inside the TIA. The calibrated output voltage Vout_cal is adjusted by changing the number of MOS transistors in the access circuit. When the input voltage Vcm does not change, the purpose of adjusting the calibrated output voltage Vout_cal is achieved by adjusting the parameters of the TIA itself.

[0061] The specific adjustment rule is that the current adjustment step of the TIA parameter is 1 / 2 of the previous adjustment step. Through continuous adjustment, the quasi-output voltage Vout_cal gradually approaches the standard voltage Vref.

[0062] S32 repeats the above step S31 until the adjustment times reaches the set value.

[0063] For example, after the first comparison, if the calibrated output voltage Vout_cal is higher than the standard voltage Vref, the TIA parameters are adjusted to reduce the calibrated output voltage Vout_cal, and the adjustment step size is S. After the second comparison, the calibrated output voltage Vout_cal is still higher than the standard voltage Vref, so the TIA parameters need to be further adjusted to reduce the calibrated output voltage Vout_cal, and the adjustment step size is S / 2. After the third comparison, the calibrated output voltage Vout_cal is still higher than the standard voltage Vref, so the TIA parameters need to be further adjusted to reduce the calibrated output voltage Vout_cal, and the adjustment step size is S / 4. After the fourth comparison, the calibrated output voltage Vout_cal is lower than the standard voltage Vref, so the TIA parameters need to be adjusted to increase the calibrated output voltage Vout_cal, and the adjustment step size is S / 8. After the fifth comparison, the calibrated output voltage Vout_cal is higher than the standard voltage Vref again, so the TIA parameters need to be adjusted to reduce the calibrated output voltage Vout_cal, and the adjustment step size is S / 16... and so on.

[0064] Through continuous adjustment, the quasi-output voltage Vout_cal gradually approaches the standard voltage Vref.

[0065] It can be foreseen that the more times the adjustment is performed, the closer the calibrated output voltage Vout_cal will be to the standard voltage Vref. Of course, in actual engineering applications, there will not be unlimited adjustment, and a certain number of adjustment times will be set. When the number of adjustment times reaches the set value, the adjustment will stop.

[0066] In fact, the setting value of the number of adjustments is adjusted according to the circuit design accuracy. The higher the design accuracy, the larger the setting value of the number of adjustments, so that the calibrated output voltage Vout_cal will be closer to the standard voltage Vref, thereby achieving the corresponding design accuracy; and the lower the design accuracy, the smaller the setting value of the number of adjustments, thereby reducing system overhead.

[0067] In some other embodiments, in order to further reduce the overhead, before the number of adjustments reaches the number threshold, if the difference between the calibrated output voltage Vout_cal and the standard voltage Vref is less than the difference threshold, it means that the design accuracy has been met, and the adjustment can be stopped at this time.

[0068] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0069] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A TIA input offset voltage calibration circuit, characterized in that: The invention comprises a TIA, wherein the input end of the TIA comprises a normal input end and a calibration input end; the output end of the TIA comprises a load output stage and a calibration output stage; the load output stage is connected to the calibration input end of the TIA by a feedback circuit; and the feedback circuit is connected to only a feedback resistor; During normal operation, the load output stage is connected and the calibration output stage is disconnected; during calibration, the load output stage is disconnected and the calibration output stage is connected; The output end of the calibration output stage is connected to a comparator, so that the output voltage of the calibration output stage is compared with a standard voltage through the comparator; the output end of the comparator is connected to the TIA; The TIA includes two outputs, which are respectively connected to the input end of the first group of field effect transistors and the input end of the second group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors form the load output stage and the calibration output stage in parallel; The first group of field effect transistors includes a first field effect transistor MOS-1 and a second field effect transistor MOS-2, whose gates G are respectively connected to two outputs of the TIA, wherein a source S of the first field effect transistor MOS-1 is externally connected to a voltage through a first switch SW1, a source S of the second field effect transistor MOS-2 is grounded through a second switch SW2, and a drain D of the first field effect transistor MOS-1 is connected to a drain D of the second field effect transistor MOS-2 as a load output terminal externally connected to a load; The second group of field effect transistors includes a third field effect transistor MOS-3 and a fourth field effect transistor MOS-4, whose gates G are respectively connected to the two outputs of the TIA, wherein the source S of the third field effect transistor MOS-3 is externally connected to a voltage through a third switch SW3, the source S of the fourth field effect transistor MOS-4 is grounded through a fourth switch SW4, and the drain D of the third field effect transistor MOS-3 is connected to the drain D of the fourth field effect transistor MOS-4 as a calibration output stage connected to the first input terminal of the comparator.

2. The TIA input offset voltage calibration circuit according to claim 1, characterized in that: The calibration output stage and the load output stage are both provided with switches. During normal operation, the switch on the calibration output stage is opened and the switch on the load output stage is closed, so that the load output stage is connected and the calibration output stage is open. During calibration, the switch on the calibration output stage is closed and the switch on the load output stage is opened, so that the load output stage is open and the calibration output stage is connected.

3. The TIA input offset voltage calibration circuit according to claim 2, characterized in that: The comparator comprises a first input terminal and a second input terminal; the output terminal of the calibration output stage is connected to the first input terminal of the comparator, and the second input terminal of the comparator is externally connected to a standard voltage.

4. A TIA input offset voltage calibration method, applied to the TIA input offset voltage calibration circuit according to any one of claims 1 to 3, characterized in that include: Disconnecting a switch on a load output stage in the TIA input offset voltage calibration circuit so that the load output stage is in an open circuit state; At the same time, closing the switch on the calibration output stage in the TIA input offset voltage calibration circuit so that the calibration output stage is a path; By connecting the input voltage Vcm to both the calibration input terminal and the normal input terminal of the TIA, and comparing the calibration output voltage Vout_cal of the calibration output stage with the standard voltage Vref; The difference between the calibrated output voltage Vout_cal and the standard voltage Vref is input into the TIA for adjustment, so that the calibrated output voltage Vout_cal approaches the standard voltage Vref.

5. The TIA input offset voltage calibration method according to claim 4, characterized in that: The difference between the calibration output voltage Vout_cal and the standard voltage Vref is input into the TIA for adjustment through one of the binary method, gradient descent method, genetic algorithm, and particle swarm optimization method, so that the calibration output voltage Vout_cal approaches the standard voltage Vref.

6. The TIA input offset voltage calibration method according to claim 5, characterized in that: The step of inputting the difference between the calibrated output voltage Vout_cal and the standard voltage Vref into the TIA for adjustment by a dichotomy method so that the calibrated output voltage Vout_cal approaches the standard voltage Vref specifically includes: Comparing the calibrated output voltage Vout_cal with the standard voltage Vref, If the calibrated output voltage Vout_cal is higher than the standard voltage Vref, adjusting the TIA parameters so that the calibrated output voltage Vout_cal is reduced; If the calibrated output voltage Vout_cal is lower than the standard voltage Vref, adjusting the TIA parameters so that the calibrated output voltage Vout_cal increases; Repeat the above steps until the adjustment times reach the set value; The current adjustment step size for adjusting the TIA parameters is 1 / 2 of the previous adjustment step size.

7. The TIA input offset voltage calibration method according to claim 6, characterized in that: The setting value of the adjustment times is adjusted according to the circuit design accuracy.

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