A chip verification method, system, device and medium

Abstract

The present invention provides a chip verification method, system, device and medium, by setting a first interface, a second interface and a bridge chip, the bridge chip includes a sending chip and a receiving chip; the first interface, the second interface, the sending chip and the receiving chip are integrated in the SYS_ENV environment of UVM to form a plurality of independent verification channels, the verification channels are used to connect the first interface, the second interface, the sending chip and the receiving chip to form a loop, and verify the sending chip and / or the receiving chip. Not only can the sending chip or the receiving chip be independently verified, but also the sending chip and the receiving chip can be docked and verified, not only the verification efficiency is high, but also the flexibility is high, and it can be highly reused.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and in particular to a chip verification method, system, equipment and medium. Background Art

[0002] In the field of chip testing, APHY bridge chips, as a key component, play an important role in bridging and converting image data of different formats. Such chips usually appear in pairs, including a transmitting chip and a receiving chip. They work together to realize the conversion of CSI (Camera Serial Interface) format image data captured by the camera to APHY format, and from APHY format data back to CSI format data for further processing by the post-stage controller. This design ensures the seamless transmission and processing of image data between different system components. However, the paired development and application characteristics of APHY bridge chips bring unique challenges to verification. The verification process not only needs to ensure the functional correctness of a single chip (transmitting or receiving), but also needs to verify the interface compatibility and data interaction accuracy between the two chips. This requires the verification team to be able to handle two closely related verification tasks at the same time to ensure that they can work together to meet the overall performance requirements of the system. There are two main traditional verification schemes:

[0003] Independent verification followed by docking verification: First, independently verify the sending chip and the receiving chip, and then perform docking verification. The main problem with this method is that with fixed manpower, two sets of verification environments need to be developed at the same time, resulting in a long verification cycle and slow convergence.

[0004] Direct docking verification: Directly dock the sending chip and the receiving chip for docking verification. Although this method can shorten the verification cycle, there are certain risks. For example, if there is a misunderstanding between the sending and receiving of the protocol, it may cause the docking test to pass, but the actual situation is inconsistent with the protocol. In addition, the handling of some special cases may not be flexible enough, which is not conducive to subsequent reuse.

[0005] Therefore, there is an urgent need for a chip verification method, system, device and medium to improve the above problems. Summary of the invention

[0006] The object of the present invention is to provide an efficient and highly reusable chip verification method, system, device and medium.

[0007] In a first aspect, the present invention provides a chip verification system, comprising a first interface, a second interface and a bridge chip, wherein the bridge chip comprises a sending chip and a receiving chip;

[0008] The first interface, the second interface, the transmitting chip and the receiving chip are integrated in the SYS_ENV environment of UVM to form several independent verification channels, and the verification channels are used to connect the first interface, the second interface, the transmitting chip and the receiving chip to form a loop to verify the transmitting chip and / or the receiving chip.

[0009] The beneficial effects of the present invention are as follows: by setting a first interface, a second interface, a transmitting chip and a receiving chip; integrating the first interface, the second interface, the transmitting chip and the receiving chip in the environment of SYS_ENV of UVM, a plurality of independent verification channels are formed, and the verification channels are used to connect the first interface, the second interface, the transmitting chip and the receiving chip to form a loop, and verify the transmitting chip and / or the receiving chip. Not only can the transmitting chip or the receiving chip be independently verified, but also the transmitting chip and the receiving chip can be docked and verified, which has high verification efficiency, high flexibility and high reuse.

[0010] Optionally, the verification channel includes a first verification channel for verifying a sending chip;

[0011] The first verification channel includes a first path and a second path;

[0012] The first interface is connected to the transmitting chip through the first path, and the transmitting chip is connected to the second interface through the second path;

[0013] And / or the verification channel further includes a second verification channel for verifying the receiving chip;

[0014] The second verification channel includes a third path, a fourth path and a fifth path;

[0015] The first interface is connected to the second interface through the third path, the second interface is connected to the receiving chip through the fourth path, and the receiving chip is connected to the first interface through the fifth path.

[0016] Optionally, the verification channel further includes a third verification channel for verifying the interconnected sending chip and receiving chip;

[0017] The third verification channel includes a sixth path, a seventh path and an eighth path;

[0018] The first interface is connected to the transmitting chip through the sixth path, the transmitting chip is connected to the receiving chip through the seventh path, and the receiving chip is connected to the first interface through the eighth path;

[0019] And / or the verification channel further includes a fourth verification channel for verifying independent sending chips and receiving chips;

[0020] The fourth verification channel includes a ninth path, a tenth path, an eleventh path and a twelfth path;

[0021] The first interface is connected to the transmitting chip through a ninth path, the transmitting chip is connected to the second interface through a tenth path, the second interface is connected to the receiving chip through the eleventh path, and the receiving chip is connected to the first interface through the twelfth path.

[0022] Optionally, the first interface is DPHY_AGENT; and / or the second interface is APHY_AGENT.

[0023] Optionally, in the first verification channel, the first interface sends first data that complies with a set protocol to the sending chip through a first path, so that the sending chip outputs second data in a set format to the second interface through a second path, and the sending chip is verified based on the first data and the second data;

[0024] And / or in the second verification channel, the first interface sends third data to the second interface through the third path, so that the second interface packs the third data into fourth data in a set format, and sends the fourth data to the receiving chip through the fourth path, so that the receiving chip packs the data into fifth data in a set format after processing, and sends the data to the first interface through the fifth path, and verifies the receiving chip based on the third data and the fifth data.

[0025] Optionally, in the third verification channel, the first interface sends sixth data to the sending chip through a sixth path, so that the sixth data is received by the receiving chip through an output end of the sending chip and a seventh path, so that the receiving chip outputs seventh data to the sending chip through an eighth path, and verification of the interconnected sending chip and receiving chip is performed based on the sixth data and the seventh data;

[0026] And / or in the fourth verification channel, the first interface sends the eighth data to the sending chip through the ninth path, so that the eighth data is received by the receiving chip through the output end of the sending chip, the tenth path, the second interface and the eleventh path, so that the receiving chip outputs the ninth data to the first interface through the twelfth path, and independent verification of the sending chip and the receiving chip is performed based on the eighth data and the ninth data.

[0027] In a second aspect, the present invention provides a chip verification method, which is applied to any possible combination of the above chip verification systems, including:

[0028] Integrate the first interface, the second interface, the sending chip and the receiving chip of the chip verification system in the environment of SYS_ENV of UVM to form a plurality of independent verification channels, wherein the verification channels are used to connect the first interface, the second interface, the sending chip and the receiving chip to form a loop;

[0029] The sending chip and / or the receiving chip are verified respectively through the verification channel.

[0030] In a third aspect, the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a program that can be run on the processor, and when the program is executed by the processor, the electronic device implements a method for executing any possible design of any of the above aspects.

[0031] In a fourth aspect, the present invention provides a readable storage medium, wherein the readable storage medium stores a program, and when the program is executed, it implements any possible design method of any of the above aspects.

[0032] For the beneficial effects of the second to fourth aspects, reference may be made to the description of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a chip verification system provided by an embodiment of the present invention;

[0034] Figure 2 A schematic diagram of a chip verification method according to an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0037] In view of the inconvenience of current chip verification, the chip verification system provided by the present invention can improve the verification efficiency, and has high flexibility and can be highly reused. The technical scheme in the embodiment of the present invention is described below in conjunction with the drawings in the embodiment of the present invention. Among them, in the description of the embodiment of the present invention, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present invention. As used in the specification of the present invention and the attached claims, the singular expressions "a", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present invention, "at least one", "one or more" refers to one or more than two (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0038] References to "one embodiment" or "some embodiments" described in this specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", and "in some other embodiments" that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. The term "connected" includes direct and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0039] In the embodiments of the present invention, "exemplarily" or "for example" is used to indicate an example, illustration or description. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of "exemplarily" or "for example" is intended to present the relevant concepts in a specific way.

[0040] like Figure 1As shown, the present invention provides a chip verification system, including a first interface 13, a second interface 14 and a bridge chip, wherein the bridge chip includes a sending chip 15 and a receiving chip 16; the first interface 13, the second interface 14, the sending chip 15 and the receiving chip 16 are integrated in the SYS_ENV environment of UVM to form a plurality of independent verification channels, wherein the verification channels are used to connect the first interface 13, the second interface 14, the sending chip 15 and the receiving chip 16 to form a loop, and verify the sending chip 15 and / or the receiving chip 16.

[0041] In some embodiments, the first interface 13 is a DPHY_AGENT; and / or the second interface 14 is an APHY_AGENT.

[0042] In some embodiments, the verification channel includes a first verification channel for verifying the sending chip 15; the first verification channel includes a first path 1 and a second path 2; the first interface 13 is connected to the sending chip 15 through the first path 1, and the sending chip 15 is connected to the second interface 14 through the second path 2.

[0043] In some specific embodiments, in the first verification channel, the first interface 13 sends first data that complies with a set protocol (such as a CSI protocol) to the sending chip 15 through a first path 1, so that the sending chip 15 outputs second data in a set format to the second interface 14 through a second path 2, and the sending chip 15 is verified based on the first data and the second data.

[0044] In some embodiments, the verification channel also includes a second verification channel for verifying the receiving chip 16; the second verification channel includes a third path 3, a fourth path 4 and a fifth path 5; the first interface 13 is connected to the second interface 14 through the third path 3, the second interface 14 is connected to the receiving chip 16 through the fourth path 4, and the receiving chip 16 is connected to the first interface 13 through the fifth path 5.

[0045] In some specific embodiments, in the second verification channel, the first interface 13 sends third data to the second interface 14 through the third path 3, so that the second interface 14 packs the third data into fourth data of a set format, and sends the fourth data to the receiving chip 16 through the fourth path 4, so that the receiving chip 16 packs the data into fifth data of a set format after processing, and sends it to the first interface 13 through the fifth path 5, and verifies the receiving chip 16 based on the third data and the fifth data.

[0046] In some embodiments, the verification channel also includes a third verification channel for verifying the interconnected sending chip 15 and receiving chip 16; the third verification channel includes a sixth path 6, a seventh path 7 and an eighth path 8; the first interface 13 is connected to the sending chip 15 through the sixth path 6, the sending chip 15 is connected to the receiving chip 16 through the seventh path 7, and the receiving chip 16 is connected to the first interface 13 through the eighth path 8.

[0047] In some specific embodiments, in the third verification channel, the first interface 13 sends sixth data to the sending chip 15 through the sixth path 6, so that the sixth data is received by the receiving chip 16 through the output end of the sending chip 15 and the seventh path 7, so that the receiving chip 16 outputs seventh data to the sending chip 15 through the eighth path 8, and verification of the interconnected sending chip 15 and receiving chip 16 is performed based on the sixth data and the seventh data.

[0048] In some embodiments, the verification channel also includes a fourth verification channel for verifying independent transmitting chip 15 and receiving chip 16; the fourth verification channel includes a ninth path 9, a tenth path 10, an eleventh path 11 and a twelfth path 12; the first interface 13 is connected to the transmitting chip 15 through the ninth path 9, the transmitting chip 15 is connected to the second interface 14 through the tenth path 10, the second interface 14 is connected to the receiving chip 16 through the eleventh path, and the receiving chip 16 is connected to the first interface 13 through the twelfth path 12.

[0049] In some specific embodiments, in the fourth verification channel, the first interface 13 sends the eighth data to the sending chip 15 through the ninth path 9, so that the eighth data is received by the receiving chip 16 through the output end of the sending chip 15, the tenth path 10, the second interface 14 and the eleventh path 11, so that the receiving chip 16 outputs the ninth data to the first interface 13 through the twelfth path 12, and independent verification of the sending chip 15 and the receiving chip 16 is performed based on the eighth data and the ninth data.

[0050] For ease of understanding, this embodiment further describes the specific implementation process of the above system in combination with a specific application scenario system. In this embodiment, the first interface 13 is DPHY_AGENT, and the second interface 14 is APHY_AGENT, which specifically includes the following steps:

[0051] DPHY_AGENT and APHY_AGENT are VIPs developed to verify MIPI DPHY and MIPI APHY, integrating the two interfaces in a UVM-based SYS_ENV environment.

[0052] The first mode: Use the first verification channel to verify the sending chip 15. The data paths in this mode are the first path 1 and the second path 2. The driver in the DPHY AGENT generates first data that complies with the CSI protocol and sends it to the sending chip 15 through the first path 1. The data packet in the APHY format output by the sending chip 15 is collected as the second data through the second path 2 by the monitor in the APHY AGENT. The monitor collects the first data sent by the sending chip 15 and uses the first data and the second data for final data comparison to verify the sending chip 15.

[0053] The second mode: the receiving chip 16 is verified by the second verification channel. The data paths of this mode are the third path 3, the fourth path 4 and the fifth path 5. The DPHY_AGENT only uses the driver to generate packaged data as the third data, and does not need to be actually driven to the interface. The generated third data is transmitted to the APHY_AGENT through the third path 3. The APHYAGENT driver packages the original third data generated by the DPHY AGENT into an APHY data packet, and transmits the APHY data packet as the fourth data to the receiving chip 16 through the fourth path 4. The receiving chip 16 packages the fourth data into the fifth data in the CSI format after processing, and outputs it to the monitor in the DPHY AGENT through the fifth path 5DPHY. In this way, the data generated by the DPHYAGENT and the data monitored by the monitor should be the same, which is convenient for data comparison, and then the verification of the receiving chip 16 is realized by using the third data and the fifth data.

[0054] The third mode: Use the third channel to verify the interconnected (such as bridging) transmitting chip 15 and receiving chip 16. The data paths of this mode are the sixth path 6, the seventh path 7 and the eighth path 8. The sixth data generated by the DPHY_AGENT driver is given to the transmitting chip 15 through the sixth path 6. The output of the transmitting chip 15 is connected to the receiving chip 16 through the seventh path 7. The data output by the receiving chip 16 DPHY is given to the DPHY monitor as the seventh data through the eighth path 8. The sixth data generated by the DPHYAGENT and the seventh data monitored by the monitor should be the same and can be directly compared, thereby realizing the docking verification of the interconnected transmitting chip 15 and receiving chip 16.

[0055] The fourth mode: the fourth channel is used to verify the independent transmitting chip 15 and receiving chip 16. The difference from the third mode is that the transmitting chip 15 and the receiving chip 16 are not directly interconnected. The data paths of this mode are the ninth path 9, the tenth path 10, the eleventh path 11 and the twelfth path 12. The eighth data generated by the DPHY_AGENT driver is given to the transmitting chip 15, and the eighth data is received by the receiving chip 16 through the output end of the transmitting chip 15, the tenth path 10, the second interface 14 and the eleventh path 11. The receiving chip 16DPHY outputs the ninth data to the DPHY monitor through the twelfth path 12. The eighth data generated by the DPHY AGENT and the ninth data monitored by the monitor should be the same, and can be directly compared, thereby realizing the docking verification of the independent transmitting chip 15 and the receiving chip 16.

[0056] The advantage of the embodiment of the present invention is that, in the same verification environment, it fully utilizes DPHY and APHY VIP, supports four different verification modes, can easily switch between modes, and is easy to compare data in the path. It also supports the verification of the sending chip 15 and the receiving chip 16 as well as the verification of a single chip, and is an efficient and flexible verification solution.

[0057] Based on the above chip verification system, such as Figure 2 As shown, the present invention provides a chip verification method, comprising:

[0058] S201, integrating the first interface, the second interface, the transmitting chip and the receiving chip of the chip verification system in the SYS_ENV environment of UVM to form a plurality of independent verification channels, wherein the verification channels are used to connect the first interface, the second interface, the transmitting chip and the receiving chip to form a loop.

[0059] S202: Verify the sending chip and / or the receiving chip respectively through the verification channel.

[0060] It should be understood that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, which will not be repeated here. In addition, the use of suffixes such as "module", "component" or "unit" used to represent elements is only for the purpose of facilitating the description of the present invention, and has no specific meaning in itself. Therefore, "module", "component" or "unit" can be used in a mixed manner. The terminal can be implemented in various forms. For example, the terminal described in the present invention may include mobile terminals such as mobile phones, tablet computers, laptops, PDAs, portable media players (PMP), navigation devices, wearable devices, smart bracelets, pedometers, and fixed terminals such as digital TVs and desktop computers. The subsequent description will be described by taking the mobile terminal as an example, and those skilled in the art will understand that, in addition to components specifically used for mobile purposes, the construction according to the embodiment of the present invention can also be applied to fixed types of terminals.

[0061] In some other embodiments of the present invention, an electronic device 300 is disclosed. Figure 3 As shown, it may include: one or more processors 301; memory 302; display 303; one or more applications (not shown); and one or more computer programs 304. The above-mentioned components may be connected via one or more communication buses 305. The one or more computer programs 304 are stored in the above-mentioned memory 302 and configured to be executed by the one or more processors 301. The one or more computer programs 304 include instructions, which may be used to execute the following instructions: Figure 1 The various steps in the corresponding embodiments.

[0062] The processor 301 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0063] The memory 302 may be an internal storage unit of the electronic device 300, such as a hard disk or memory of the electronic device 300. The memory 302 may also be an external storage device of the electronic device 300, such as a plug-in hard disk, a smart memory card (SmartMediaCard, SMC), a secure digital (SecureDigital, SD) card, a flash card (FlashCard), etc. equipped on the electronic device 300. Further, the memory 302 may also include both an internal storage unit of the electronic device 300 and an external storage device. The memory 302 is used to store computer programs and other programs and data required by the electronic device. The memory 302 may also be used to temporarily store data that has been output or is to be output.

[0064] The computer program 304 may be divided into one or more modules / units. The one or more modules / units may be a series of computer program instruction segments capable of performing specific functions. The instruction segments are used to describe the execution process of the computer program 304 in the electronic device 300 .

[0065] In addition to the above structure, those skilled in the art can understand that Figure 3 It is only an example of the electronic device 300 and does not constitute a limitation of the electronic device 300. The electronic device 300 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the electronic device may also include input and output devices, network access devices, buses, etc.

[0066] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0067] Based on the above embodiments, the present invention further discloses a computer-readable storage medium on which at least one computer program is stored. When the computer program is executed by a processor, the chip verification system in the above embodiments is implemented.

[0068] A person of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above embodiment can be completed by instructing the processor through a program, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state hard disk, a magnetic tape, a floppy disk, an optical disk, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state disk (SSD)), etc.

[0069] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0070] To sum up, the chip verification method, system, device and medium disclosed in the present invention can not only independently verify the sending chip or the receiving chip, but also perform docking verification on the sending chip and the receiving chip. It not only has high verification efficiency, but also high flexibility and can be highly reused.

[0071] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A chip verification system, characterized in that: It includes a first interface, a second interface and a bridge chip, wherein the bridge chip includes a sending chip and a receiving chip; Integrate the first interface, the second interface, the transmitting chip and the receiving chip in the environment of SYS_ENV of UVM to form a plurality of independent verification channels, wherein the verification channels are used to connect the first interface, the second interface, the transmitting chip and the receiving chip to form a loop, and verify the transmitting chip and / or the receiving chip; The verification channel includes a first verification channel for verifying a transmitting chip, a second verification channel for verifying a receiving chip, a third verification channel for verifying an interconnected transmitting chip and a receiving chip, and a fourth verification channel for verifying an independent transmitting chip and a receiving chip; The first verification channel includes a first path and a second path; the first interface is connected to the sending chip through the first path, and the sending chip is connected to the second interface through the second path; The second verification channel includes a third path, a fourth path and a fifth path; the first interface is connected to the second interface through the third path, the second interface is connected to the receiving chip through the fourth path, and the receiving chip is connected to the first interface through the fifth path; The third verification channel includes a sixth path, a seventh path and an eighth path; the first interface is connected to the sending chip through the sixth path, the sending chip is connected to the receiving chip through the seventh path, and the receiving chip is connected to the first interface through the eighth path; The fourth verification channel includes a ninth path, a tenth path, an eleventh path and a twelfth path; the first interface is connected to the sending chip through the ninth path, the sending chip is connected to the second interface through the tenth path, the second interface is connected to the receiving chip through the eleventh path, and the receiving chip is connected to the first interface through the twelfth path.

2. The system according to claim 1, characterized in that The first interface is DPHY_AGENT; and / or the second interface is APHY_AGENT.

3. The system according to claim 1, characterized in that In the first verification channel, the first interface sends first data that complies with a set protocol to the sending chip through a first path, so that the sending chip outputs second data in a set format to the second interface through a second path, and the sending chip is verified based on the first data and the second data; And / or in the second verification channel, the first interface sends third data to the second interface through the third path, so that the second interface packs the third data into fourth data in a set format, and sends the fourth data to the receiving chip through the fourth path, so that the receiving chip packs the data into fifth data in a set format after processing, and sends the data to the first interface through the fifth path, and verifies the receiving chip based on the third data and the fifth data.

4. The system according to claim 1, characterized in that In the third verification channel, the first interface sends sixth data to the transmitting chip through a sixth path, so that the sixth data is received by the receiving chip through an output end of the transmitting chip and a seventh path, so that the receiving chip outputs seventh data to the transmitting chip through an eighth path, and verification of the interconnected transmitting chip and receiving chip is performed based on the sixth data and the seventh data; And / or in the fourth verification channel, the first interface sends the eighth data to the sending chip through the ninth path, so that the eighth data is received by the receiving chip through the output end of the sending chip, the tenth path, the second interface and the eleventh path, so that the receiving chip outputs the ninth data to the first interface through the twelfth path, and independent verification of the sending chip and the receiving chip is performed based on the eighth data and the ninth data.

5. A chip verification method, characterized in that: A chip verification system applied to any one of claims 1 to 4, comprising: Integrate the first interface, the second interface, the sending chip and the receiving chip of the chip verification system in the environment of SYS_ENV of UVM to form a plurality of independent verification channels, wherein the verification channels are used to connect the first interface, the second interface, the sending chip and the receiving chip to form a loop; The sending chip and / or the receiving chip are verified respectively through the verification channel.

6. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory stores a program that can be run on the processor, and when the program is executed by the processor, the electronic device implements the method described in claim 5.

7. A readable storage medium, wherein a program is stored in the readable storage medium, characterized in that: When the program is executed, the method described in claim 5 is implemented.

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