Semiconductor device with silicon carbide ohmic contact and method for preparing the same

Abstract

This application provides a semiconductor device with a silicon carbide ohmic contact and a method for fabricating the same. The semiconductor device includes: a silicon carbide substrate; a single-crystal silicon carbide epitaxial layer formed on the silicon carbide substrate; a first doped region formed downwards from the upper surface of the silicon carbide epitaxial layer; a polycrystalline silicon carbide layer covering the first doped region, wherein the first doped region and the silicon carbide layer have the same doping type, and the doping concentration of the silicon carbide layer is higher than that of the silicon carbide epitaxial layer; and an alloy metal layer covering the silicon carbide layer; wherein both the polycrystalline silicon carbide layer and the single-crystal silicon carbide epitaxial layer are made of silicon carbide, and a tunnel is formed between the polycrystalline silicon carbide layer and the alloy metal layer. This application solves the technical problem of the extremely high requirements for the fabrication process of traditional ohmic contacts.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor device with silicon carbide ohmic contact and a method for preparing the same. Background Art

[0002] Ohmic contact and Schottky contact are two types of metal-semiconductor contact methods. Their main difference lies in the size of the contact resistance and the current-voltage relationship. Ohmic contact is an ideal contact state between metal and semiconductor in semiconductor devices. Its resistance value is extremely low, which can ensure that the current passes smoothly on the contact interface.

[0003] For SiC devices, the performance of ohmic contact directly affects the overall performance of the device. Source-drain contact resistance is one of the important parameters for measuring the performance of SiC MOSFET devices.

[0004] Therefore, how to make SiC ohmic contacts with low resistance and high stability has always been an important issue in the field of semiconductor technology. The quality of ohmic contacts greatly affects the performance of various devices, including gain, power consumption and switching speed.

[0005] The difficulty in preparing low contact resistance lies in selecting the appropriate alloy metal and process conditions. In addition to metal selection, the ionization energy of p-type impurities in SiC materials is higher than that of n-type impurities, and the P-type has the characteristics of low effective doping concentration and low hole mobility, making it more difficult to form high-quality p-type SiC ohmic contacts.

[0006] At present, the mainstream preparation process for mass-produced commercial silicon carbide ohmic contacts is as follows:

[0007] 1. On the SiC epitaxial layer, use photolithography masking technology to perform high-dose ion implantation of N-type and P-type in different areas (dose of 10 15 atm / cm 2 ), defining the N-type and P-type regions.

[0008] 2. Use SIO2 hard mask to define the area where ohmic contact is required.

[0009] 3. Sputtering metal (Ni is used for mainstream production);

[0010] 4. Rapid thermal annealing (700~900 degrees Celsius);

[0011] 5. Wet removal of nickel.

[0012] 6. Al metal wiring completes the interconnection.

[0013] The specific contact resistance formed by the above-mentioned silicon carbide ohmic contact preparation process is not low enough. At present, the specific contact resistance of N-type is generally at least 10 -5 Ω·cm 2 The P-type has a higher specific contact resistance, generally around 10 -4 Ω·cm 2 For devices such as SiC MOSFET and SiC BJT with higher performance requirements, such specific contact resistance is far from meeting the device requirements. Among them, specific contact resistance is also called conductivity, which is a physical quantity that measures the conductive properties of a material.

[0014] The SiC ohmic contact problem is currently mainly concentrated on three technical points. In addition to alloy metal selection and annealing technology, there are also technical difficulties as follows:

[0015] The height and width of the Schottky barrier established by the metal-SiC contact determine whether the contact is a Schottky contact or an Ohmic contact. The metal work function of an ideal N-type Ohmic contact should be lower than 4eV, and the metal work function of an ideal P-type Ohmic contact should be higher than 7eV.

[0016] The metal work function of commonly used metal-semiconductor contacts is 4.2 to 6 eV. Therefore, the metal-SiC contact inevitably forms a Schottky contact. The barrier width W can only be reduced by heavy doping, so that electrons can tunnel through the relatively thin barrier, thereby forming a tunnel to achieve ohmic contact.

[0017] The epitaxial layer used in SiC devices is 4H-SiC, and the doping concentration is generally 5×10 15 ~2×10 16 Therefore, it is necessary to use a large dose of ion implantation process to form an epitaxial layer of 4H-SiC, which can significantly increase the carrier density of SiC and reduce its depletion layer width, forming tunneling.

[0018] The key problem of this method is that lattice defects or amorphous states are easily formed during the process of ion implantation to form the epitaxial layer of 4H-SiC. These defects are very stubborn and need to be restored by extremely high temperature annealing at about 1800 degrees Celsius, which complicates the manufacture of SiC devices. In addition, due to the limitation of the implantation machine capacity, the implantation concentration is at most 10 19 cm -3 level.

[0019] Therefore, traditional ohmic contacts have extremely high requirements on the preparation process, which is a technical problem that technical personnel in this field urgently need to solve.

[0020] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0021] The embodiments of the present application provide a semiconductor device with silicon carbide ohmic contact and a method for preparing the same, so as to solve the technical problem that traditional ohmic contact has extremely high requirements on the preparation process.

[0022] According to a first aspect of an embodiment of the present application, there is provided a semiconductor device having a silicon carbide ohmic contact, comprising:

[0023] Silicon carbide substrate;

[0024] A single-crystal silicon carbide epitaxial layer is formed on the silicon carbide substrate;

[0025] A first doped region, formed from the upper surface of the silicon carbide epitaxial layer downwardly;

[0026] a polycrystalline silicon carbide layer covering the first doped region, the first doped region and the silicon carbide layer having the same doping type, and a doping concentration of the silicon carbide layer being higher than a doping concentration of the silicon carbide epitaxial layer;

[0027] An alloy metal layer covering the silicon carbide layer;

[0028] The polycrystalline silicon carbide layer and the single crystal silicon carbide epitaxial layer are both made of silicon carbide materials, and a tunnel is formed between the polycrystalline silicon carbide layer and the alloy metal layer, so that the alloy metal layer and the silicon carbide epitaxial layer are in ohmic contact.

[0029] According to a second aspect of an embodiment of the present application, a method for preparing a semiconductor device having a silicon carbide ohmic contact is provided, comprising the following steps:

[0030] forming a single-crystalline silicon carbide epitaxial layer on the silicon carbide substrate;

[0031] Forming a first doped region by implantation downward from the upper surface of the silicon carbide epitaxial layer;

[0032] A polycrystalline silicon carbide layer formed by deposition, covering the first doped region, the first doped region and the silicon carbide layer having the same doping type, and a doping concentration of the silicon carbide layer being higher than a doping concentration of the silicon carbide epitaxial layer;

[0033] An alloy metal layer is formed covering the silicon carbide layer.

[0034] The embodiment of the present application adopts the above technical solution, which has the following technical effects:

[0035] The semiconductor device with silicon carbide ohmic contact in the embodiment of the present application is an improvement on the problems existing in the single-crystal silicon carbide epitaxial layer in the prior art. That is, the epitaxial layer of the semiconductor device with silicon carbide ohmic contact in the present application is a single-crystal silicon carbide epitaxial layer 2, and the single-crystal silicon carbide epitaxial layer 2 requires that at least the position in the substrate 1 connected to the silicon carbide epitaxial layer 2 is a single crystal. Specifically, the silicon carbide substrate can be a single-crystal silicon carbide substrate, or the position in the substrate 1 connected to the silicon carbide epitaxial layer 2 can be a single crystal.

[0036] The semiconductor device with silicon carbide ohmic contact in the embodiment of the present application realizes that the doping concentration requirement for the first doping region 4 is not high by arranging a highly doped polycrystalline silicon carbide layer 5 between the first doping region 4 and the alloy metal layer 6. That is, in the preparation of the first doping region 4 formed by implantation, high-dose ion implantation is no longer required, and the lattice defects or amorphous state caused by high-dose ion implantation have been avoided in the present application.

[0037] The highly doped polycrystalline silicon carbide layer 5 is provided between the first doped region 4 and the alloy metal layer 6, and the highly doped polycrystalline silicon carbide layer 5 is formed by deposition. The highly doped polycrystalline silicon carbide layer 5 formed by deposition can be easily increased in doping concentration without introducing other defects.

[0038] Since the polycrystalline silicon carbide layer 5 and the single-crystalline silicon carbide epitaxial layer 2 are both made of silicon carbide materials, that is, are homogeneous, the potential barrier between the two is relatively low.

[0039] The doping concentration of the highly doped polycrystalline silicon carbide layer 5 is an order of magnitude lower than the ion concentration of the alloy metal layer 6 , so the potential barrier between the highly doped polycrystalline silicon carbide layer 5 and the alloy metal layer 6 is low and tunneling is easily formed.

[0040] The potential barriers between the polycrystalline silicon carbide layer 5 and the single crystal silicon carbide epitaxial layer 2, and between the doped polycrystalline silicon carbide layer 5 and the alloy metal layer 6 are low and tunneling is easy to form. The two conditions are combined together, and finally an ohmic contact is formed between the alloy metal layer 6 and the silicon carbide epitaxial layer 2 through the polycrystalline silicon carbide layer 5 and the first doped region 4.

[0041] The polycrystalline silicon carbide layer 5 plays a connecting role between the alloy metal layer 6 and the single crystal silicon carbide epitaxial layer 2 . BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0043] Figure 1 A schematic diagram of a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application;

[0044] Figure 2 A schematic diagram of the method for preparing a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application after executing step S1;

[0045] Figure 3 A schematic diagram of the method for preparing a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application after executing step S2;

[0046] Figure 4 A schematic diagram showing the method for preparing a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application after executing step S3;

[0047] Figure 5 A schematic diagram of the method for preparing a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application after executing step S4;

[0048] Figure 6 A schematic diagram of the method for preparing a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application after executing step S5;

[0049] Figure 7 A schematic diagram of the method for preparing a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application after executing step S6;

[0050] Figure 8 A schematic diagram of the method for preparing a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application after executing step S7;

[0051] Fig. 9 A schematic diagram of the method for preparing a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application after executing step S8;

[0052] Fig.10 A schematic diagram of the method for preparing a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application after executing step S9;

[0053] Fig.11 A schematic diagram of the method for preparing a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application after executing step S10;

[0054] Fig.12 A schematic diagram of the method for preparing a semiconductor device with silicon carbide ohmic contact according to an embodiment of the present application after executing step S11;

[0055] Fig.13The semiconductor device with silicon carbide ohmic contact of the present application is a curve diagram showing the change of drain efficiency of the first BJT device as a function of output performance;

[0056] Fig.14 A graph showing a change in power point linear gain versus output performance of a first BJT device for a semiconductor device with silicon carbide ohmic contact according to the present application;

[0057] Fig.15 A graph showing changes in drain efficiency versus output performance of a second BJT device for the semiconductor device with silicon carbide ohmic contact of the present application;

[0058] Fig.16 The semiconductor device with silicon carbide ohmic contact of the present application is a curve diagram showing the change of power point linear gain versus output performance of the second BJT device.

[0059] Reference numerals:

[0060] Silicon carbide substrate 1, silicon carbide epitaxial layer 2, silicon dioxide dielectric layer 3, first doped region 4,

[0061] Silicon carbide layer 5, alloy metal layer 6. DETAILED DESCRIPTION

[0062] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. Embodiment 1

[0063] like Figure 1 As shown, the semiconductor device with silicon carbide ohmic contact according to the embodiment of the present application includes:

[0064] Silicon carbide substrate 1;

[0065] A single crystal silicon carbide epitaxial layer 2 is formed on the silicon carbide substrate 1, and a position in the substrate 1 that is connected to the silicon carbide epitaxial layer 2 is a single crystal;

[0066] A first doped region 4 is formed by implanting from the upper surface of the silicon carbide epitaxial layer 2 downwards;

[0067] A polycrystalline silicon carbide layer 5 formed by deposition, covering the first doped region 4, the first doped region 4 and the silicon carbide layer 5 have the same doping type, and the doping concentration of the silicon carbide layer 5 is higher than the doping concentration of the silicon carbide epitaxial layer 2;

[0068] an alloy metal layer 6, covering the silicon carbide layer 5;

[0069] Among them, the polycrystalline silicon carbide layer 5 and the single crystal silicon carbide epitaxial layer 2 are both made of silicon carbide materials, that is, they are homogeneous, so that the potential barrier between the two is low, and a tunnel is formed between the polycrystalline silicon carbide layer 5 and the alloy metal layer 6, and finally the alloy metal layer 6 and the silicon carbide epitaxial layer 2 are in ohmic contact.

[0070] The semiconductor device with silicon carbide ohmic contact in the embodiment of the present application is an improvement on the problems existing in the single-crystal silicon carbide epitaxial layer in the prior art. That is, the epitaxial layer of the semiconductor device with silicon carbide ohmic contact in the present application is a single-crystal silicon carbide epitaxial layer 2, and the single-crystal silicon carbide epitaxial layer 2 requires that at least the position in the substrate 1 connected to the silicon carbide epitaxial layer 2 is a single crystal. Specifically, the silicon carbide substrate can be a single-crystal silicon carbide substrate, or the position in the substrate 1 connected to the silicon carbide epitaxial layer 2 can be a single crystal.

[0071] The semiconductor device with silicon carbide ohmic contact in the embodiment of the present application realizes that the doping concentration requirement for the first doping region 4 is not high by arranging a highly doped polycrystalline silicon carbide layer 5 between the first doping region 4 and the alloy metal layer 6. That is, in the preparation of the first doping region 4 formed by implantation, high-dose ion implantation is no longer required, and the lattice defects or amorphous state caused by high-dose ion implantation have been avoided in the present application.

[0072] The highly doped polycrystalline silicon carbide layer 5 is provided between the first doped region 4 and the alloy metal layer 6, and the highly doped polycrystalline silicon carbide layer 5 is formed by deposition. The highly doped polycrystalline silicon carbide layer 5 formed by deposition can be easily increased in doping concentration without introducing other defects.

[0073] Since the polycrystalline silicon carbide layer 5 and the single-crystalline silicon carbide epitaxial layer 2 are both made of silicon carbide materials, that is, are homogeneous, the potential barrier between the two is relatively low.

[0074] The doping concentration of the highly doped polycrystalline silicon carbide layer 5 is an order of magnitude lower than the ion concentration of the alloy metal layer 6, that is, the ion concentrations of the highly doped polycrystalline silicon carbide layer 5 and the alloy metal layer 6 are both high and the order of magnitude difference is small. Therefore, the potential barrier between the highly doped polycrystalline silicon carbide layer 5 and the alloy metal layer 6 is low and tunneling is easily formed.

[0075] The potential barriers between the polycrystalline silicon carbide layer 5 and the single crystal silicon carbide epitaxial layer 2, and between the doped polycrystalline silicon carbide layer 5 and the alloy metal layer 6 are low and tunneling is easy to form. The two conditions are combined together, and finally an ohmic contact is formed between the alloy metal layer 6 and the silicon carbide epitaxial layer 2 through the polycrystalline silicon carbide layer 5 and the first doped region 4.

[0076] The polycrystalline silicon carbide layer 5 plays a connecting role between the alloy metal layer 6 and the single crystal silicon carbide epitaxial layer 2. On the one hand, the polycrystalline silicon carbide layer 5 has the same characteristics as the single crystal silicon carbide epitaxial layer 2, so that the potential barrier between the polycrystalline silicon carbide layer 5 and the single crystal silicon carbide epitaxial layer 2 is low; on the other hand, because the doping concentration of the polycrystalline silicon carbide layer 5 is high and the ion concentration of the alloy metal layer 6 is also high, the high ion concentration of the polycrystalline silicon carbide layer 5 and the alloy metal layer 6 is utilized to achieve a low potential barrier between the silicon carbide layer 5 and the alloy metal layer 6.

[0077] Specifically, the first doping region 4 is formed by implanting the single-crystal silicon carbide epitaxial layer 2 , and may be either a single-crystal first doping region 4 or a polycrystalline first doping region 4 .

[0078] In practice, the doping concentration of the polycrystalline silicon carbide layer 5 is 2 to 3 orders of magnitude lower than the ion concentration of the alloy metal layer 6 , so that the potential barrier between the alloy metal layer 6 and the silicon carbide layer 5 is low and tunneling is easily formed.

[0079] In practice, the doping concentration of the polycrystalline silicon carbide layer 5 is 1 to 3 orders of magnitude higher than the doping concentration of the first doping region 4 .

[0080] The higher the doping concentration of the polycrystalline silicon carbide layer 5, the better. The higher the doping concentration of the polycrystalline silicon carbide layer 5, the less ion concentration is lower than that of the alloy metal layer 6, so that the potential barrier between the alloy metal layer 6 and the silicon carbide layer 5 is low and tunneling is easily formed.

[0081] There is no need to consider the potential barrier difference between the polycrystalline silicon carbide layer 5 and the first doping region 4. The reasons are as follows:

[0082] According to the position of the Fermi level:

[0083] ; Formula 1

[0084] Among them, E F is the Fermi level; E V is the energy of the valence band top; k is the Boltzmann constant; n0 is the concentration of free electrons (carrier concentration) in the conduction band at temperature T; n iis the intrinsic carrier concentration in the conduction band at temperature T. Equation 1 describes the relationship between the Fermi level and the top of the valence band in semiconductor materials. Specifically, it shows that the position of the Fermi level relative to the top of the valence band is related to the free electron concentration n in the conduction band. i and the intrinsic carrier concentration n i The logarithmic ratio between them.

[0085] The doping concentration of the polycrystalline silicon carbide layer 5 is in the range of greater than or equal to 10 20 cm -3 The doping concentration of the first doping region 4 is in the range of greater than or equal to 10 16 cm -3 Less than or equal to 10 20 cm -3 , and they are made of the same material, silicon carbide. Therefore, the calculated Fermi level positions are not much different, and therefore, the barrier difference between the polycrystalline silicon carbide layer 5 and the first doped region 4 is small.

[0086] Since the potential barrier difference between the polycrystalline silicon carbide layer 5 and the first doped region 4 is small, that is, the potential barrier difference between the alloy metal layer 6 and the silicon carbide epitaxial layer 2 is small, the corresponding potential barrier width is small. Electrons can tunnel through the smaller potential barrier, thereby forming an ohmic contact between the alloy metal layer 6 and the silicon carbide epitaxial layer 2.

[0087] As an optional manner, the doping type of the silicon carbide layer 5 is N-type;

[0088] The doping concentration of the polycrystalline silicon carbide layer 5 is greater than or equal to 10 20 cm -3 .

[0089] As another optional manner, the doping type of the silicon carbide layer 5 is P type;

[0090] The doping concentration of the polycrystalline silicon carbide layer 5 is greater than or equal to 10 20 cm -3 .

[0091] In the implementation, the doping concentration of the first doping region 4 is in the range of greater than or equal to 10 16 cm -3 Less than or equal to 10 20 cm -3 .

[0092] In practice, the material of the polycrystalline silicon carbide layer 5 is 3C-SiC, 4H-SiC or 6H-SiC.

[0093] In practice, the silicon carbide epitaxial layer 2 is a silicon carbide epitaxial layer 2 made of a single crystal 4H-SiC material.

[0094] The method for preparing a semiconductor device with silicon carbide ohmic contact of the present application comprises the following steps:

[0095] A single-crystalline silicon carbide epitaxial layer 2 is formed on a silicon carbide substrate 1;

[0096] Forming a first doped region 4 on the upper surface of the silicon carbide epitaxial layer 2 by implantation downwards;

[0097] A polycrystalline silicon carbide layer 5 formed by deposition, covering the first doped region 4, the first doped region 4 and the silicon carbide layer 5 have the same doping type, and the doping concentration of the silicon carbide layer 5 is higher than the doping concentration of the silicon carbide epitaxial layer 2;

[0098] An alloy metal layer 6 is formed covering the silicon carbide layer 5 .

[0099] In practice, the doping concentration of the polycrystalline silicon carbide layer 5 is 2 to 3 orders of magnitude lower than the ion concentration of the alloy metal layer 6 , so that the potential barrier between the alloy metal layer 6 and the silicon carbide layer 5 is low and tunneling is easily formed.

[0100] In practice, the doping concentration of the polycrystalline silicon carbide layer 5 is 1 to 3 orders of magnitude higher than the doping concentration of the first doping region 4 .

[0101] The method for preparing a semiconductor device having a silicon carbide ohmic contact comprises the following steps in the preparation order:

[0102] like Figure 2 As shown, step S1: epitaxially growing a single crystal silicon carbide epitaxial layer 2 of 4H-SiC on a silicon carbide substrate 1;

[0103] like Figure 3 As shown, step S2: depositing a silicon dioxide dielectric layer 3 on the silicon carbide epitaxial layer 2;

[0104] like Figure 4 As shown, step S3: using a photolithography and etching process, a first doped region 4 to be formed into a P-type or N-type is etched in the silicon carbide epitaxial layer 2 .

[0105] like Figure 5 As shown, step S4: adopt ion implantation process to implant at the position where the first doped region 4 needs to be formed. If the first doped region 4 is P-type, P-type ions are implanted; if the first doped region 4 is N-type, N-type ions are implanted.

[0106] like Figure 6 As shown, step S5: depositing a highly doped polycrystalline silicon carbide film.

[0107] like Figure 7As shown, step S6: using a photolithography and etching process, the first doped region 4 is protected by a photoresist;

[0108] like Figure 8 As shown, step S7: the other regions of the silicon carbide film except the first doped region 4 are dry-etched.

[0109] like Fig. 9 As shown, step S8: etching away the photoresist and the vertical silicon carbide film to form a single-layer silicon carbide layer 5;

[0110] like Fig.10 As shown, step S9: sputtering alloy metal (such as Ni, etc.);

[0111] like Fig.11 As shown, step S10: rapid thermal annealing to form alloy metal.

[0112] like Fig.12 As shown, step S11: removing the excess part of the alloy metal by wet method to form the alloy metal layer 6.

[0113] The present invention has been verified through experiments and simulations, and the results are feasible.

[0114] The present application provides a semiconductor device with silicon carbide ohmic contact, and the parameters and performance of the device are shown in Table 1 below.

[0115] Table 1:

[0116]

[0117] According to the above table, the doping type of the silicon carbide layer 5 is N-type, the silicon carbide layer 5 is highly doped polycrystalline silicon carbide, the alloy metal layer 6 is NI, and the semiconductor device with silicon carbide ohmic contact annealed during the preparation process of the silicon carbide layer 5 has the smallest specific contact resistance. Among them, the specific contact resistance is the specific contact resistance between the alloy metal layer 6 and the silicon carbide epitaxial layer 2.

[0118] The following is an explanation by taking the simulation of a BJT device as an example in which the semiconductor device with silicon carbide ohmic contact is used.

[0119] The first BJT device:

[0120] The specific contact resistance between the alloy metal layer 6 and the silicon carbide epitaxial layer 2 of the first BJT device is (specific contact resistance when the silicon carbide epitaxial layer is P-type) ρ CP =10 -5 ohm cm 2 , or (specific contact resistance when the silicon carbide epitaxial layer is N-type) ρ CN =10- 6 ohm cm 2, BJT device with power point linear gain Gp=15.7dB,

[0121] The output performance (Pout@MaxP), power gain (Gp@MaxP), linearity index AMPM (AMPM@MaxP), and drain efficiency (DE@MaxE) under 3dB compression are shown in Table 2.

[0122] Table 2:

[0123]

[0124] Fig.13 The semiconductor device with silicon carbide ohmic contact of the present application is a curve chart showing the change of drain efficiency of the first BJT device as the output performance changes; the horizontal axis is Pout@MaxP output performance, in db; the vertical axis is DE@MaxE drain efficiency, in percentage.

[0125] Fig.14 The semiconductor device with silicon carbide ohmic contact of the present application is a curve chart showing the change of power point linear gain of the first BJT device with output performance; the horizontal axis is Pout@MaxP output performance, in db; the vertical axis is Gp@MaxP power point linear gain, in db.

[0126] The second BJT device:

[0127] The specific contact resistance between the alloy metal layer 6 and the silicon carbide epitaxial layer 2 of the second BJT device is (specific contact resistance when the silicon carbide epitaxial layer is P-type) ρ CP =10 -6 ohm cm 2 , or (specific contact resistance when the silicon carbide epitaxial layer is N-type) ρ CN =10- 7 ohm cm 2 , BJT device with power point linear gain Gp=20.959dB,

[0128] The output performance (Pout@MaxP), power gain (Gp@MaxP), linearity index AMPM (AMPM@MaxP), and drain efficiency (DE@MaxE) under 3dB compression are shown in Table III.

[0129] Table 3:

[0130]

[0131] Fig.15The semiconductor device with silicon carbide ohmic contact of the present application is a curve chart showing the change of drain efficiency of the second BJT device as a function of output performance; the horizontal axis is Pout@MaxP output performance, in db; the vertical axis is DE@MaxE drain efficiency, in percentage.

[0132] Fig.16 The semiconductor device with silicon carbide ohmic contact of the present application is a curve chart showing the change of power point linear gain of the second BJT device with output performance; the horizontal axis is Pout@MaxP output performance, in db; the vertical axis is Gp@MaxP power point linear gain, in db.

[0133] Simulation results show that reducing the ohmic contact resistance can improve the power point linear gain.

[0134] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0135] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0136] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0137] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0138] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0139] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A semiconductor device having a silicon carbide ohmic contact, characterized in that: include: Silicon carbide substrate (1); A single-crystal silicon carbide epitaxial layer (2) formed on the silicon carbide substrate (1); A first doped region (4), formed downward from the upper surface of the silicon carbide epitaxial layer (2); a polycrystalline silicon carbide layer (5) covering the first doped region (4), the first doped region (4) and the silicon carbide layer (5) having the same doping type, and a doping concentration of the silicon carbide layer (5) being higher than a doping concentration of the silicon carbide epitaxial layer (2); An alloy metal layer (6) covering the silicon carbide layer (5); The polycrystalline silicon carbide layer (5) and the single-crystalline silicon carbide epitaxial layer (2) are both made of silicon carbide materials, and a tunnel is formed between the polycrystalline silicon carbide layer (5) and the alloy metal layer (6); The doping concentration of the polycrystalline silicon carbide layer (5) is 1 to 3 orders of magnitude higher than the doping concentration of the first doping region (4).

2. The semiconductor device with silicon carbide ohmic contact according to claim 1, characterized in that: The doping concentration of the polycrystalline silicon carbide layer (5) is 2 to 3 orders of magnitude lower than the ion concentration of the alloy metal layer (6).

3. The semiconductor device with silicon carbide ohmic contact according to any one of claims 1 to 2, characterized in that: The doping type of the silicon carbide layer (5) is N-type; The doping concentration of the polycrystalline silicon carbide layer (5) is greater than or equal to 10 20 cm -3 ; Alternatively, the doping type of the silicon carbide layer (5) is P type; The doping concentration of the polycrystalline silicon carbide layer (5) is greater than or equal to 10 20 cm -3 .

4. The semiconductor device with silicon carbide ohmic contact according to any one of claims 1 to 2, characterized in that: The doping concentration of the first doping region (4) is in the range of greater than or equal to 10 16 cm -3 Less than or equal to 10 20 cm -3 .

5. The semiconductor device with silicon carbide ohmic contact according to any one of claims 1 to 2, characterized in that: The material of the polycrystalline silicon carbide layer (5) is 3C-SiC, 4H-SiC or 6H-SiC.

6. The semiconductor device with silicon carbide ohmic contact according to any one of claims 1 to 2, characterized in that: The silicon carbide epitaxial layer (2) is a silicon carbide epitaxial layer (2) made of a single-crystal 4H-SiC material.

7. A method for preparing a semiconductor device having a silicon carbide ohmic contact, characterized in that: The steps include: Forming a single-crystalline silicon carbide epitaxial layer (2) on a silicon carbide substrate (1); Forming a first doped region (4) by implantation downwardly on the upper surface of the silicon carbide epitaxial layer (2); A polycrystalline silicon carbide layer (5) formed by deposition, covering the first doped region (4), the first doped region (4) and the silicon carbide layer (5) having the same doping type, and a doping concentration of the silicon carbide layer (5) being higher than a doping concentration of the silicon carbide epitaxial layer (2); forming an alloy metal layer (6) covering the silicon carbide layer (5); The doping concentration of the polycrystalline silicon carbide layer (5) is 1 to 3 orders of magnitude higher than the doping concentration of the first doping region (4).

8. The preparation method according to claim 7, characterized in that: The doping concentration of the polycrystalline silicon carbide layer (5) is 2 to 3 orders of magnitude lower than the ion concentration of the alloy metal layer (6), so that the potential barrier between the alloy metal layer (6) and the silicon carbide layer (5) is low and tunneling is easily formed.

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