A high-speed, low-power logic switch

Abstract

A high-speed, low-power logic switch, the function of the clock frequency module is to divide the frequency according to the input working clock external clock input pin P1, and generate two clock signals CLK1 and clock signal CLK2. The function of the logic module is to collect the input analog signal. When the integrated voltage signal reaches the high or low voltage trigger condition, the switch module controls the output of the corresponding clock frequency. The present invention integrates the voltage modulation voltage, logic control circuit and switch circuit in the traditional I / F conversion circuit scheme, simplifies the design difficulty and design scheme of the I / F conversion circuit scheme, and uses the integration circuit to convert the voltage signal of the current change signal into the low-power high-speed logic switch, and outputs the corresponding frequency signal, which greatly reduces the complexity and cost of the current I / F conversion circuit board card, and improves the stability of the I / F conversion circuit board card system.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a high-speed and low-power consumption logic switch. Background Art

[0002] The high-speed, low-power logic switch technology solution is not currently disclosed through other means.

[0003] The high-speed, low-power logic switch responds to analog voltage signals. Based on the time when the voltage rises or falls and the level, when the level reaches the high or low trigger threshold, the switch is turned on to output digital code.

[0004] In the current logic switch circuit, it can only be triggered by high or low levels and output corresponding high or low levels. It is a pure logic circuit, generally composed of one or more groups of gate circuits, which are composed of the combinational logic that needs to be implemented to reflect the state or combination state of one or more input signals.

[0005] Currently, all logic switch circuits are pure logic circuits, which do not add time variable constraints to the input signal, that is, the speed of change of the input signal level cannot be reflected through the output result. Summary of the invention

[0006] In order to solve the above problems in the prior art, the present invention provides a high-speed and low-power logic switch.

[0007] The technical solution adopted by the present invention to solve the technical problem is:

[0008] A high-speed and low-power logic switch comprises a clock frequency module, a logic module and a switch module.

[0009] The clock frequency module uses a D-type flip-flop method to sort out the external clock signal input from the external clock input pin P1, and output it from the output pin O15 of the flip-flop circuit after eliminating the interference signal. The output signal of the output pin O15 of the flip-flop circuit is short-connected to the circuit clock input terminal P2 from the outside of the product. The circuit clock input terminal P2 signal passes through the D flip-flop, buffer and gate circuit to sort the circuit clock input terminal P2 signal into a signal with the same frequency but different duty cycle. The function of the clock frequency module is to divide the frequency according to the input working clock external clock input pin P1 to generate two clock signals CLK1 and CLK2.

[0010] The logic module outputs different levels at the flip threshold node P5 and the flip threshold node P3 for the input analog signal level through the sampling circuit. The function of the logic module is to collect the input analog signal. The working principle of the logic module is: when the analog signal level reaches the high level trigger condition 2.5V, the high level logic channel is triggered, and the output terminal O9 outputs a signal with a duty cycle of 50%, the output terminal O11 outputs the high level of 7 trigger clock signals CLK, the output terminal O12 outputs the opposite phase to the output terminal O11, and the frequency of the output signal is consistent with the output terminal O9. Similarly, when the analog signal level drops to 0.3V, the low level channel is triggered, and the output terminal O10 outputs a signal with a duty cycle of 50%, the output terminal O13 outputs the high level of 7 trigger clock signals CLK, the output terminal O14 outputs the opposite phase to the output terminal O13, and the frequency of the output signal is consistent with the output terminal O10.

[0011] The switch module triggers the different levels of the flip threshold node P5 and the flip threshold node P3, turns on the switch module switch, and allows the trigger clock signal CLK to pass. The trigger clock signal CLK passes through the AND gate and the inverter circuit and is output to different output pins. The working principle of the switch module is: when the integrated voltage signal reaches the high or low voltage trigger condition, the switch module controls the output of the corresponding clock frequency.

[0012] The present invention also has the following additional technical features:

[0013] As a further specific optimization of the technical solution of the present invention: in the clock frequency module, the clock signal provided by the external system is modulated by frequency division to generate two groups of clock signals CLK1 and clock signal CLK2 with the same frequency but different duty cycles; the high level of the clock signal CLK1 is 7 times the external clock cycle; the high level of the clock signal CLK2 is 4 times the external clock cycle.

[0014] As a further specific optimization of the technical solution of the present invention: in the logic module and the switch module, the external integration level is input by the flip threshold node P4, and through the voltage division level modulation, a high level signal of the flip threshold node P3 or a low level signal of the flip threshold node P5 is obtained; when the high level signal of the flip threshold node P3 is greater than the threshold level of 2.5V, the switch circuit opens the high level channel and outputs the frequency signal of the clock signal CLK2 from the output terminal O9, and at the same time, the switch circuit controls the clock signal CLK1 frequency signal to be output from the output terminal O12.

[0015] As a further specific optimization of the technical solution of the present invention: when the low-level signal of the flip threshold node P5 is lower than the 0.3V threshold level, the switch circuit opens the low-level channel and outputs the frequency signal of the clock signal CLK2 from the output terminal O10. At the same time, the switch circuit controls the clock signal CLK1 frequency signal to be output from the output terminal O14, and the output terminal O13 outputs the inverted signal of the output terminal O14. The frequencies of this group of signals are the same.

[0016] Compared with the prior art, the present invention has the following advantages:

[0017] The high-speed low-power logic switch of the present invention has a working clock of up to 1.024MHz, and outputs digital codes through the working clock and input signal level changes. According to the working clock, the output digital codes are decoded to obtain the input signal level change state and change time.

[0018] The high-speed, low-power logic switch of the present invention is mainly used in the I / F (current to frequency) field. Currently, traditional solutions for implementing I / F conversion include an integration circuit, a voltage modulation circuit, a logic control circuit, a switching circuit, a constant current source circuit, and a temperature-sensitive adjustable current circuit.

[0019] The present invention integrates the voltage modulation voltage, logic control circuit and switch circuit in the traditional I / F conversion circuit scheme, simplifies the design difficulty and design scheme of the I / F conversion circuit scheme, and uses an integral circuit to convert the voltage signal of the current change signal into the low-power high-speed logic switch to output the corresponding frequency signal, which greatly reduces the complexity and cost of the current I / F conversion circuit board card and improves the stability of the I / F conversion circuit board card system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a clock frequency module of the present invention;

[0021] Figure 2 It is a schematic diagram of a logic module of the present invention;

[0022] Figure 3 is a schematic diagram of a switch module of the present invention;

[0023] Figure 4 It is a schematic diagram of a clock frequency module of the present invention;

[0024] Figure 5 It is a schematic diagram of the logic control module and the switch module of the present invention.

[0025] Markings in the accompanying drawings:

[0026] P1 refers to the external clock input pin, which is used as Figure 1 The input signal of the trigger clock signal CLK.

[0027] O15 refers to the output pin of the trigger circuit, which realizes the output of the clock signal input from the external clock input pin P1 after dividing it by 2.

[0028] D refers to the trigger input, which is connected to the trigger output Qn and serves as the output pin of the circuit.

[0029] Q refers to the trigger output and is not brought out in the circuit.

[0030] CLK refers to the trigger clock signal input of the integrated circuit.

[0031] Qn refers to the output terminal of the trigger and is connected to the trigger input pin D. Its output is the non-output of Q.

[0032] P3 refers to the flip threshold node set by the circuit.

[0033] P4 refers to the flip threshold node of the circuit setting.

[0034] P5 refers to the flip threshold node set by the circuit.

[0035] VDD refers to the power supply of this circuit, which is 4.5V to 5.5V.

[0036] O7 refers to the output terminal of the Q NOT of the D flip-flop which takes the inversion threshold node P3 as the input signal, and the clock of the flip-flop is the clock signal CLK1.

[0037] O8 refers to the output terminal of the Q NOT of the D flip-flop which takes the inversion threshold node P5 as the input signal, and the clock of the flip-flop is the clock signal CLK1.

[0038] O9 is an output terminal, which refers to the output terminal after O7 is negated and the clock signal CLK2 is subjected to a negated and inverted operation.

[0039] O10 is an output terminal, which refers to the output terminal after O8 is negated and the clock signal CLK2 is ANDed and then reversed.

[0040] O11 is an output terminal, which refers to the output terminal where the clock signal CLK1 and O7 are inverted after being ORed.

[0041] O12 is an output terminal, which refers to the output terminal after the clock signal CLK1 and O7 are ORed.

[0042] The output terminal O14 is the output terminal after the clock signals CLK1 and O8 are negated.

[0043] P2 is the circuit clock input terminal, which refers to the clock that generates the subsequent clock signal CLK1 and the clock signal CLK2.

[0044] CLK1 is the clock signal. After the circuit clock input terminal P2 is negated, the two-stage D flip-flop frequency division processing signal is first negated through NAND processing, and then NAND-negated with the signal after the circuit clock input terminal P2 is negated to obtain the clock signal.

[0045] CLK2 is the clock signal. The circuit clock input terminal P2 is processed by two-stage D flip-flop frequency division. The clock frequency output by the clock signal CLK1 is 4 times the frequency of the clock circuit clock input terminal P2. DETAILED DESCRIPTION

[0046] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0047] A high-speed and low-power logic switch comprises a clock frequency module, a logic module and a switch module.

[0048] The clock frequency module uses a D-type flip-flop method to sort out the external clock signal input from the external clock input pin P1, and output it from the output pin O15 of the flip-flop circuit after eliminating the interference signal. The output signal of the output pin O15 of the flip-flop circuit is short-connected to the circuit clock input terminal P2 from the outside of the product. The circuit clock input terminal P2 signal passes through the D flip-flop, buffer and gate circuit to sort the circuit clock input terminal P2 signal into a signal with the same frequency but different duty cycle. The function of the clock frequency module is to divide the frequency according to the input working clock external clock input pin P1 to generate two clock signals CLK1 and CLK2.

[0049] The logic module outputs different levels at the flip threshold node P5 and the flip threshold node P3 for the input analog signal level through the sampling circuit. The function of the logic module is to collect the input analog signal. The working principle of the logic module is: when the analog signal level reaches the high level trigger condition 2.5V, the high level logic channel is triggered, and the output terminal O9 outputs a signal with a duty cycle of 50%, the output terminal O11 outputs the high level of 7 trigger clock signals CLK, the output terminal O12 outputs the opposite phase to the output terminal O11, and the frequency of the output signal is consistent with the output terminal O9. Similarly, when the analog signal level drops to 0.3V, the low level channel is triggered, and the output terminal O10 outputs a signal with a duty cycle of 50%, the output terminal O13 outputs the high level of 7 trigger clock signals CLK, the output terminal O14 outputs the opposite phase to the output terminal O13, and the frequency of the output signal is consistent with the output terminal O10.

[0050] The switch module triggers the different levels of the flip threshold node P5 and the flip threshold node P3, turns on the switch module switch, and allows the trigger clock signal CLK to pass. The trigger clock signal CLK passes through the AND gate and the inverter circuit and is output to different output pins. The working principle of the switch module is: when the integrated voltage signal reaches the high or low voltage trigger condition, the switch module controls the output of the corresponding clock frequency.

[0051] In the clock frequency module, the clock signal provided by the external system is modulated by frequency division to generate two sets of clock signals CLK1 and clock signal CLK2 with the same frequency but different duty cycles; the high level of the clock signal CLK1 is 7 times the external clock cycle; the high level of the clock signal CLK2 is 4 times the external clock cycle.

[0052] In the logic module and the switch module, the external integration level is input from the flip threshold node P4, and through the voltage division level modulation, a high level signal of the flip threshold node P3 or a low level signal of the flip threshold node P5 is obtained. When the high level signal of the flip threshold node P3 is greater than the threshold level of 2.5V, the switch circuit opens the high level channel and outputs the frequency signal of the clock signal CLK2 from the output terminal O9. At the same time, the switch circuit controls the clock signal CLK1 frequency signal to be output from the output terminal O12.

[0053] When the low-level signal of the flip threshold node P5 is lower than the 0.3V threshold level, the switch circuit opens the low-level channel and outputs the frequency signal of the clock signal CLK2 from the output terminal O10. At the same time, the switch circuit controls the clock signal CLK1 frequency signal to be output from the output terminal O14, and the output terminal O13 outputs the inverted signal of the output terminal O14. The frequencies of this group of signals are the same.

[0054] The high-speed low-power logic switch of the present invention has a working clock of up to 1.024MHz, and outputs digital codes through the working clock and input signal level changes. According to the working clock, the output digital codes are decoded to obtain the input signal level change state and change time.

[0055] The high-speed, low-power logic switch of the present invention is mainly used in the field of I / F (current conversion to frequency). At present, the traditional scheme for realizing I / F conversion includes an integration circuit, a voltage modulation circuit, a logic control circuit, a switch circuit, a constant current source circuit, and a temperature-sensitive adjustable current circuit. In the traditional I / F conversion circuit, the sampling frequency of the signal is usually completed below 100KHz, while the present circuit can complete the sampling and digital output of the signal within the frequency range of 1KHz to 1.024MHz according to the design requirements, and the sampling speed is far higher than the transmission sampling mode. Secondly, compared with the traditional I / F conversion circuit, the present circuit can replace the voltage comparison, clock generation, logic control, analog switch, and buffer output module in the traditional I / F conversion circuit, and realize low power consumption on the basis of reducing costs, and the working power is within 10mW. In the traditional circuit, the power consumption of a module (such as a voltage comparison or an analog switch) will reach or exceed 10mW.

[0056] The present invention integrates the voltage modulation voltage, logic control circuit and switch circuit in the traditional I / F conversion circuit scheme, simplifies the design difficulty and design scheme of the I / F conversion circuit scheme, and uses an integral circuit to convert the voltage signal of the current change signal into the low-power high-speed logic switch to output the corresponding frequency signal, which greatly reduces the complexity and cost of the current I / F conversion circuit board card and improves the stability of the I / F conversion circuit board card system.

[0057] The above detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention but merely represents selected embodiments of the present invention.

Claims

1. A high-speed, low-power logic switch, characterized in that: It includes a clock frequency module, a logic module and a switch module; wherein: The clock frequency module uses a D-type flip-flop method to sort out the external clock signal input from the external clock input pin P1, and output it from the output pin O15 of the flip-flop circuit after eliminating the interference signal; the output signal of the flip-flop circuit output pin O15 is short-connected to the circuit clock input terminal P2 from the outside of the product, and the circuit clock input terminal P2 signal passes through the D flip-flop, buffer and gate circuit to sort out the circuit clock input terminal P2 signal into a signal with the same frequency but different duty cycle; the function of the clock frequency module is to divide the frequency according to the input working clock external clock input pin P1 to generate two clock signals CLK1 and clock signal CLK2; The logic module outputs different levels at the flip threshold node P5 and the flip threshold node P3 for the input analog signal level through the sampling circuit; the function of the logic module is to collect the input analog signal; the working principle of the logic module is: when the analog signal level reaches the high level trigger condition 2.5V, the high level logic channel is triggered, and a signal with a duty cycle of 50% is output at the output terminal O9, and the output terminal O11 outputs the high level of 7 trigger clock signals CLK, and the output terminal O12 outputs the opposite phase to the output terminal O11; similarly, when the analog signal level drops to 0.3V, the low level channel is triggered, and a signal with a duty cycle of 50% is output at the output terminal O10, and the output terminal O13 outputs the high level of 7 trigger clock signals CLK, and the output terminal O14 outputs the opposite phase to the output terminal O13; The switch module triggers the different levels of the flip threshold node P5 and the flip threshold node P3, turns on the switch module switch, and allows the trigger clock signal CLK to pass. The trigger clock signal CLK passes through the AND gate and the inverter circuit and is output to different output pins. The working principle of the switch module is: when the integrated voltage signal reaches the high or low voltage trigger condition, the switch module controls the output of the corresponding clock frequency; In the logic module and the switch module, the external integration level is input from the flip threshold node P4, and through the voltage division level modulation, a high level signal of the flip threshold node P3 or a low level signal of the flip threshold node P5 is obtained; when the high level signal of the flip threshold node P3 is greater than the threshold level of 2.5V, the switch circuit opens the high level channel and outputs the frequency signal of the clock signal CLK2 from the output terminal O9. At the same time, the switch circuit controls the clock signal CLK1 frequency signal to be output from the output terminal O12, and the output terminal O11 outputs the inverted signal of the output terminal O12; When the low level signal of the flip threshold node P5 is lower than the 0.3V threshold level, the switch circuit opens the low level channel and outputs the frequency signal of the clock signal CLK2 from the output terminal O10. At the same time, the switch circuit controls the clock signal CLK1 frequency signal to be output from the output terminal O14, and the output terminal O13 outputs the inverted signal of the output terminal O14.

2. A high-speed, low-power logic switch according to claim 1, characterized in that: In the clock frequency module, the clock signal provided by the external system is modulated by frequency division to generate two sets of clock signals CLK1 and clock signal CLK2 with the same frequency but different duty cycles; the high level of the clock signal CLK1 is 7 times the external clock cycle; the high level of the clock signal CLK2 is 4 times the external clock cycle.

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