A method for mapping input and output functions and pins within a chip

Abstract

The invention relates to the technical field of chip pin mapping, and discloses a method for mapping input and output functions within a chip to pins. In the mapping method of the invention, the input functions and output functions of the chip are processed by categories, thereby simplifying the circuit, thereby reducing the relative area of ​​the circuit; secondly, the input mapping control module and the output mapping control module used in the method are modularly designed, the overall number can change with the chip scale, can be quickly generated, and have strong portability; in addition, the priorities of adjacent pins corresponding to the output functions in the invention are opposite, and different solution requirements can be applied; finally, the mapping of the input function and the output function to the pins can be configured through registers, and can be mapped to any pin, which can make the chip highly compatible and easier to use.

Description

Technical Field

[0001] The present invention relates to the technical field of chip pin mapping, and in particular to a method for mapping input and output functions and pins in a chip. Background Art

[0002] With the continuous development of integrated circuits, the functional design inside the chip is becoming more and more complex. Correspondingly, the input and output functions of the chip are also increasing. For example, the microcontrollers used for control have gradually developed from 8-bit microcontrollers to 16-bit microcontrollers, 32-bit microcontrollers and 64-bit microcontrollers.

[0003] For chips with more and more functions, if a pin is configured for each function, the chip package and area will become larger, which will eventually increase the cost of the chip. In addition, for chip users, chip users will design corresponding peripheral circuits according to the chip specifications to form the final circuit product. If the chip package changes, the chip will be incompatible with the previous circuit product.

[0004] In order to avoid the above problems, the chip pins are reused so that the chip functions are increased without increasing the chip pins. However, in actual use, when multiple functions of chip pins are reused, two functions on the same pin need to be used at the same time, which will cause conflicts in the input and output of the pins.

[0005] In order to solve the problem of pin multiplexing and make the chip adaptable to different application scenarios, the functions of the chip pins are currently configurable through function mapping.

[0006] For example, a microcontroller and its input / output pin mapping circuit disclosed in publication number CN107329417A can generate different pin mapping relationships according to different control signals, so that the position of the special function input / output pins of the microcontroller can change with the change of the control signal, solving the problem that the volume of the printed circuit board is difficult to reduce due to the fixed position of the special function input / output pins of the MCU.

[0007] Or a chip system with a remapping function and a chip remapping configuration system disclosed in publication number CN113114220 respectively set an input dynamic interconnection network and an output dynamic interconnection network for the input signal and output signal between the chip core and the chip pin driving circuit; wherein the input port of the output dynamic interconnection network is connected to the first output port of the chip core, and the output port of the output dynamic interconnection network is connected to the first output pin of the chip pin driving circuit; the input port of the input dynamic interconnection network is connected to the first input pin of the chip pin driving circuit, and the output port of the input dynamic interconnection network is connected to the first input port of the chip core. The non-blocking network structure is expanded and constructed in a recursive manner, thereby delaying the speed at which the number of cross points increases with the number of input and output lines compared to the prior art solution of using a multiplexer to achieve chip pin remapping, thereby reducing the cost of achieving chip pin remapping.

[0008] For the above two patents, the input and output of the first patent both adopt the method of multiplexer. The input and output functions have a priority, the adaptability is poor, and the multiplexer has a large area, resulting in higher cost. The non-blocking network structure of the second patent is also a two-choice selector. After recursive expansion construction, it becomes multiple two-choice selectors, which also has the problems of large area and high cost. Summary of the invention

[0009] In view of the shortcomings of the background technology, the present invention provides a method for mapping input and output functions and pins within a chip. The technical problem to be solved is that the existing method for mapping input and output functions and pins of a chip has the problems of large area and high cost.

[0010] To solve the above technical problems, the present invention provides the following technical solutions: a method for mapping input and output functions and pins in a chip, wherein the chip includes i input functions, j output functions and m pins, i, j and m are all positive integers greater than 1 and m is an even number, and is implemented by i input mapping control modules and m output mapping control modules;

[0011] The input mapping control module includes m AND gates; among the m AND gates, the output ends of every two AND gates are electrically connected to the two input ends of a first OR gate; m / 2 1 In the first OR gates, the output terminals of each two first OR gates are electrically connected to the two input terminals of a second OR gate; 2 In the second OR gates, the output terminals of every two second OR gates are electrically connected to the two input terminals of a third OR gate, and so on, until they are connected to the last final OR gate;

[0012] The output mapping control module includes j selectors that select one of two, and the j selectors are connected in series in sequence, and the series connection is that the output end of the front-end selector is electrically connected to the second input end of the back-end selector;

[0013] The method is as follows:

[0014] For each input mapping control module, the m pins are electrically connected to the first input terminals of the m AND gates respectively, and the second input terminals of the m AND gates are respectively used to access the input control signals; the output terminals of the final OR gates of the i input mapping control modules are electrically connected to the input terminals of the i input functions;

[0015] For each output mapping control module, the first input terminals of j selectors are electrically connected to the output terminals of j output functions respectively, and the selection terminals of j selectors are used to input selection control signals; the output terminals of the final stage selectors of m output mapping control modules are electrically connected to m pins respectively.

[0016] In a certain embodiment, the m pins are respectively recorded as pin 1, pin 2...pin m, the output ends of the two AND gates connected to pin 1 and pin 2 are connected to a first OR gate, the output ends of the two AND gates connected to pin 3 and pin 4 are connected to a first OR gate, and so on, the output ends of the two AND gates connected to pin m-1 and pin m are connected to a first OR gate.

[0017] In a certain embodiment, the j output functions are sequentially recorded as output function one, output function two, ... output function j;

[0018] For the output mapping control modules electrically connected to the pins at odd positions, along the series direction of the selectors, the output end of output function one is electrically connected to the first input end of the first selector, the output end of output function two is electrically connected to the first input end of the second selector, and so on, the output end of output function j is electrically connected to the first input end of the jth selector;

[0019] For the output mapping control module electrically connected to the pins in even positions, along the series direction of the selectors, the output end of the output function j is electrically connected to the first input end of the first selector, the output end of the output function j-1 is electrically connected to the first input end of the second selector, and so on, the output end of the output function one is electrically connected to the first input end of the jth selector.

[0020] In some implementations, for each input mapping control module, the input control signal is generated as follows:

[0021] An input mapping register and an input mapping decoder are configured for each input mapping control module. The input mapping decoder is electrically connected to the input mapping register to decode output information of the input mapping register. The decoded information output by the input mapping decoder is input into m AND gates.

[0022] In some embodiments, the bit width of the input mapping register is k, where k>=log , and k<=log +1, and is a positive integer greater than 1, the input mapping decoder is a km decoder, the first bit of decoding information output by the input mapping decoder is input to the second input end of the AND gate electrically connected to pin one, the second bit of decoding information output by the input mapping decoder is input to the second input end of the AND gate electrically connected to pin two, and so on, the mth bit of decoding information output by the input mapping decoder is input to the second input end of the AND gate electrically connected to pin m.

[0023] In some implementations, for all output mapping control modules, the selection control signal is generated as follows:

[0024] An output mapping register and an output mapping decoder are configured for each output mapping control module. The output mapping decoder is electrically connected to the output mapping register to decode the output information of the output mapping register. The decoded information output by the output mapping decoder is input to the selection end of the selector.

[0025] In some embodiments, the bit width of the output mapping register is k, where k>=log , and k<=log +1, and is a positive integer greater than 1, the output mapping decoder is the km decoder; the j output mapping decoders are recorded as output mapping decoder one, output mapping decoder two...output mapping decoder j; the first bit of information output by the j output mapping decoders is input to the selection end of the selector in the output mapping control module electrically connected to pin one, the second bit of information output by the j output mapping decoders is input to the selection end of the selector in the output mapping control module electrically connected to pin two, and so on, the mth bit of information output by the j output mapping decoders is input to the selection end of the selector in the output mapping control module electrically connected to pin m.

[0026] In a certain embodiment, for the output mapping control module electrically connected to the pin 1, the first bit of information output by the output mapping decoder 1 is input to the selection end of the first selector, the first bit of information output by the output mapping decoder 2 is input to the selection end of the second selector, and so on, the first bit of information output by the output mapping decoder j is input to the selection end of the last selector;

[0027] For the output mapping control module electrically connected to pin 2, the second bit of information output by output mapping decoder j is input to the selection end of the first selector, the second bit of information output by output mapping decoder j-1 is input to the selection end of the second selector, and so on, the second bit of information output by output mapping decoder 1 is input to the selection end of the last selector;

[0028] And so on:

[0029] For the output mapping control module electrically connected to the pin j-1, the m-1th bit information output by the output mapping decoder 1 is input to the selection end of the first selector, the m-1th bit information output by the output mapping decoder 2 is input to the selection end of the second selector, and so on, the m-1th bit information output by the output mapping decoder j is input to the selection end of the last selector;

[0030] For the output mapping control module electrically connected to pin j, the m-th bit information output by the output mapping decoder j is input to the selection end of the first selector, the m-th bit information output by the output mapping decoder j-1 is input to the selection end of the second selector, and so on, the m-th bit information output by the output mapping decoder one is input to the selection end of the last selector.

[0031] In some implementations, the m pins do not include a power pin.

[0032] In some implementations, the m pins do not include a ground pin.

[0033] Compared with the prior art, the present invention has the following beneficial effects: firstly, in the mapping method of the present invention, the input function and output function of the chip are processed by categories, thereby simplifying the circuit and reducing the relative area of ​​the circuit; secondly, the input mapping control module and the output mapping control module used in the method are modularly designed, the overall number can change with the chip scale, can be quickly generated, and have strong portability; in addition, the priorities of adjacent pins corresponding to the output function in the present invention are opposite, which can be applied to different solution requirements; finally, the mapping of the input function and the output function to the pin can be configured through registers, and can be mapped to any pin, which can make the chip highly compatible and easier to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic diagram of the structure of an input mapping control module in an embodiment;

[0035] Figure 2 is a schematic diagram of the structure of an output mapping control module in the embodiment;

[0036] Figure 3is a schematic diagram of the structure of all output mapping control modules in the embodiment;

[0037] Figure 4 A schematic diagram of a structure for providing an input control signal for an input mapping control module in an embodiment;

[0038] Figure 5 This is a schematic diagram of a structure for providing a selection control signal for all output mapping control modules in an embodiment. DETAILED DESCRIPTION

[0039] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0040] In order to solve the problems of large area and high cost in the mapping method of input and output functions and pins of the existing chip, this embodiment provides a mapping method of input and output functions and pins in a chip, wherein the chip includes i input functions, j output functions and m pins, i, j and m are all positive integers greater than 1 and m is an even number, and is implemented by i input mapping control modules and m output mapping control modules; it should be noted that the values ​​of i, j and m are not restrictive and can be set according to the specifications of the chip, but need to meet the above setting relationship; in addition, the m pins do not include power pins and ground pins;

[0041] The structure of a single input mapping control module is as follows Figure 1 As shown, it includes m AND gates, wherein the m AND gates are AND gate AND1, AND gate AND2, AND gate AND3, ..., AND gate ANDm-1 and AND gate ANDm; among the m AND gates, the output ends of every two AND gates are electrically connected to the two input ends of a first OR gate OR1; m / 2 1 In the first OR gates OR1, the output terminals of every two first OR gates OR1 are electrically connected to the two input terminals of a second OR gate OR2; 2 In the second OR gates OR2, the output terminals of every two second OR gates OR2 are electrically connected to the two input terminals of a third OR gate, and so on, until they are connected to the last final OR gate ORn;

[0042] The result of a single output mapping control module is as follows Figure 2 As shown, it includes j selectors that select one of two, and the j selectors are connected in series in sequence, and the series connection is such that the output end OUT of the front-end selector is electrically connected to the second input end B of the back-end selector;

[0043] Here’s how:

[0044] For each input mapping control module, the m pins are electrically connected to the first input terminals of the m AND gates respectively, and the second input terminals of the m AND gates are respectively used to access the input control signals; the output terminals of the final stage OR gates ORn of the i input mapping control modules are electrically connected to the input terminals of the i input functions;

[0045] For each output mapping control module, the first input terminals of j selectors are electrically connected to the output terminals of j output functions respectively, and the selection terminals of the j selectors are used to input selection control signals, and the selection control signals are used to control the output signals of the selectors, that is, to control whether the selector outputs the signal of its first input terminal or the signal of its second input terminal; the output terminals of the final-stage selectors of the m output mapping control modules are electrically connected to the m pins respectively.

[0046] In actual use, the mapping method of the present invention simplifies the circuit by classifying the input functions and output functions of the chip for processing, thereby reducing the relative area of ​​the circuit; secondly, the input mapping control module and the output mapping control module used in the method are modularly designed, the overall number can change with the chip scale, can be generated quickly, and have strong portability.

[0047] Specifically, in this embodiment, the m pins are respectively recorded as pin 1, pin 2...pin m, the output ends of the two AND gates connected to pin 1 and pin 2 are connected to a first OR gate OR1, the output ends of the two AND gates connected to pin 3 and pin 4 are connected to a first OR gate OR1, and so on, the output ends of the two AND gates connected to pin m-1 and pin m are connected to a first OR gate OR1.

[0048] by Figure 1 For example, the input of pin one is recorded as pi[1], the input of pin two is recorded as pi[2], the input of pin three is recorded as pi[3], and so on. The input of pin m is recorded as pi[m].

[0049] In this embodiment, for each input mapping control module, the access method of the m pins is the same.

[0050] Specifically, in this embodiment, the j output functions are sequentially recorded as output function one, output function two, ..., output function j;

[0051] like Figure 3 As shown, for the output mapping control module electrically connected to the pins at odd positions, along the series direction of the selectors, the output end of output function one is electrically connected to the first input end A of the first selector, the output end of output function two is electrically connected to the first input end A of the second selector, and so on, the output end of output function j is electrically connected to the first input end A of the jth selector;

[0052] For the output mapping control module electrically connected to the pins in even positions, along the series direction of the selectors, the output end of the output function j is electrically connected to the first input end A of the first selector, the output end of the output function j-1 is electrically connected to the first input end A of the second selector, and so on, the output end of the output function one is electrically connected to the first input end A of the jth selector.

[0053] In addition, in this embodiment, for each input mapping control module, the input control signal is generated in the following manner:

[0054] like Figure 4 As shown, an input mapping register and an input mapping decoder are configured for each input mapping control module. The input mapping decoder is electrically connected to the input mapping register to decode the output information of the input mapping register. The decoded information output by the input mapping decoder is input into m AND gates.

[0055] Among them, the bit width of the input mapping register is k, where k>=log , and k<=log +1, and is a positive integer greater than 1, the input mapping decoder is the km decoder, the first bit of decoding information output by the input mapping decoder is input to the second input end of the AND gate AND1 electrically connected to pin 1, the second bit of decoding information output by the input mapping decoder is input to the second input end of the AND gate AND2 electrically connected to pin 2, and so on, the mth bit of decoding information output by the input mapping decoder is input to the second input end of the AND gate ANDm electrically connected to pin m.

[0056] by Figure 1 For example, the first bit of decoding information output by the input mapping decoder is recorded as mc_i1[1], the second bit of decoding information output by the input mapping decoder is recorded as mc_i1[2], the third bit of decoding information output by the input mapping decoder is recorded as mc_i1[3], the m-1th bit of decoding information output by the input mapping decoder is recorded as mc_i1[m-1], and the mth bit of decoding information output by the input mapping decoder is recorded as mc_i1[m].

[0057] Specifically, in this embodiment, for all output mapping control modules, the generation method of the control signal is selected as follows:

[0058] like Figure 5 As shown, each output mapping control module is configured with an output mapping register and an output mapping decoder, the output mapping decoder is electrically connected to the output mapping register, and decodes the output information of the output mapping register; the decoded information output by the output mapping decoder is input to the selection end of the selector.

[0059] Among them, the bit width of the output mapping register is k, where k>=log , and k<=log +1, and is a positive integer greater than 1, the output mapping decoder is km decoder; the j output mapping decoders are recorded as output mapping decoder 1, output mapping decoder 2, ..., output mapping decoder j;

[0060] The first bit of information output by the j output mapping decoders is input to the selection end of the selector in the output mapping control module electrically connected to pin one, the second bit of information output by the j output mapping decoders is input to the selection end of the selector in the output mapping control module electrically connected to pin two, and so on, the mth bit of information output by the j output mapping decoders is input to the selection end of the selector in the output mapping control module electrically connected to pin m.

[0061] More specifically, if Figure 3 As shown, for the output mapping control module electrically connected to pin 1, the first bit information mc_o1[1] output by output mapping decoder 1 is input to the selection end S of the first selector, the first bit information mc_o2[1] output by output mapping decoder 2 is input to the selection end S of the second selector, and so on, the first bit information mc_oj[1] output by output mapping decoder j is input to the selection end S of the last selector;

[0062] For the output mapping control module electrically connected to pin 2, the second bit information mc_oj[2] output by the output mapping decoder j is input to the selection end S of the first selector, the second bit information mc_oj-1[2] output by the output mapping decoder j-1 is input to the selection end of the second selector, and so on, the second bit information mc_o1[2] output by the output mapping decoder 1 is input to the selection end S of the last selector;

[0063] And so on:

[0064] For the output mapping control module electrically connected to the pin j-1, the m-1th bit information mc_o1[m-1] output by the output mapping decoder 1 is input to the selection terminal S of the first selector, the m-1th bit information mc_o2[m-1] output by the output mapping decoder 2 is input to the selection terminal of the second selector, and so on, the m-1th bit information mc_oj[m-1] output by the output mapping decoder j is input to the selection terminal S of the last selector;

[0065] For the output mapping control module electrically connected to pin j, the m-th bit information mc_oj[m] output by the output mapping decoder j is input to the selection terminal S of the first selector, the m-th bit information mc_oj-1[m] output by the output mapping decoder j-1 is input to the selection terminal S of the second selector, and so on, the m-th bit information mc_o1[m] output by the output mapping decoder one is input to the selection terminal S of the last selector.

[0066] For this embodiment Figure 3 and Figure 5 The structure shown sets the priority of the chip's output function to two opposite priorities, so as to adapt to various application requirements. In addition, by setting the output function number size and the pin number, when the pin number is an odd number, the larger the output function number, the higher its priority; when the pin number is an even number, the larger the output function number, the lower its priority.

[0067] In summary, the mapping method of the present invention first simplifies the circuit by classifying the input function and output function of the chip for processing, thereby reducing the relative area of ​​the circuit; secondly, the input mapping control module and the output mapping control module used in the method are modularly designed, and the overall number can change with the chip scale, can be generated quickly, and have strong portability; in addition, the priorities of adjacent pins corresponding to the output function in the present invention are opposite, which can be applied to different solution requirements; finally, the mapping of input function and output function to pins can be configured through registers, and can be mapped to any pin, which can make the chip highly compatible and easier to use.

[0068] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A method for mapping input and output functions and pins in a chip, wherein the chip includes i input functions, j output functions and m pins, i, j and m are all positive integers greater than 1 and m is an even number, characterized in that: It is realized by i input mapping control modules and m output mapping control modules; The input mapping control module comprises m AND gates; among the m AND gates, the output ends of every two AND gates are electrically connected to the two input ends of a first OR gate; among the m / 21 first OR gates, the output ends of every two first OR gates are electrically connected to the two input ends of a second OR gate; among the m / 22 second OR gates, the output ends of every two second OR gates are electrically connected to the two input ends of a third OR gate, and so on, until the last final-stage OR gate is connected; The output mapping control module includes j selectors that select one of two, and the j selectors are connected in series in sequence, and the series connection is that the output end of the front-end selector is electrically connected to the second input end of the back-end selector; The method is as follows: For each input mapping control module, the m pins are electrically connected to the first input terminals of the m AND gates respectively, and the second input terminals of the m AND gates are respectively used to access the input control signals; the output terminals of the final OR gates of the i input mapping control modules are electrically connected to the input terminals of the i input functions; For each output mapping control module, the first input terminals of j selectors are electrically connected to the output terminals of j output functions respectively, and the selection terminals of the j selectors are used to input selection control signals, and the selection control signals are used to control the output signals of the selectors; the output terminals of the final stage selectors of m output mapping control modules are electrically connected to m pins respectively; The m pins are recorded as pin 1, pin 2, ... pin m, the output ends of the two AND gates connected to pin 1 and pin 2 are connected to a first OR gate, the output ends of the two AND gates connected to pin 3 and pin 4 are connected to a first OR gate, and so on, the output ends of the two AND gates connected to pin m-1 and pin m are connected to a first OR gate; The j output functions are respectively recorded as output function 1, output function 2, ... output function j; For the output mapping control modules electrically connected to the pins at odd positions, along the series direction of the selectors, the output end of output function one is electrically connected to the first input end of the first selector, the output end of output function two is electrically connected to the first input end of the second selector, and so on, the output end of output function j is electrically connected to the first input end of the jth selector; For the output mapping control modules electrically connected to the pins at even positions, along the series direction of the selectors, the output end of output function j is electrically connected to the first input end of the first selector, the output end of output function j-1 is electrically connected to the first input end of the second selector, and so on, the output end of output function one is electrically connected to the first input end of the jth selector; For all output mapping control modules, the selection control signal is generated as follows: An output mapping register and an output mapping decoder are configured for each output mapping control module. The output mapping decoder is electrically connected to the output mapping register to decode the output information of the output mapping register. The decoded information output by the output mapping decoder is input to the selection end of the selector.

2. A method for mapping input and output functions and pins in a chip according to claim 1, characterized in that: For each input mapping control module, the input control signal is generated as follows: An input mapping register and an input mapping decoder are configured for each input mapping control module. The input mapping decoder is electrically connected to the input mapping register to decode output information of the input mapping register. The decoded information output by the input mapping decoder is input into m AND gates.

3. A method for mapping input and output functions and pins within a chip according to claim 2, characterized in that: The bit width of the input mapping register is k, where k>=log , and k<=log +1, and is a positive integer greater than 1, the input mapping decoder is a km decoder, the first bit of decoding information output by the input mapping decoder is input to the second input end of the AND gate electrically connected to pin one, the second bit of decoding information output by the input mapping decoder is input to the second input end of the AND gate electrically connected to pin two, and so on, the mth bit of decoding information output by the input mapping decoder is input to the second input end of the AND gate electrically connected to pin m.

4. The method for mapping input and output functions and pins in a chip according to claim 1, characterized in that: The bit width of the output mapping register is k, where k>=log , and k<=log +1, and is a positive integer greater than 1, the output mapping decoder is the km decoder; the j output mapping decoders are recorded as output mapping decoder one, output mapping decoder two...output mapping decoder j; the first bit of information output by the j output mapping decoders is input to the selection end of the selector in the output mapping control module electrically connected to pin one, the second bit of information output by the j output mapping decoders is input to the selection end of the selector in the output mapping control module electrically connected to pin two, and so on, the mth bit of information output by the j output mapping decoders is input to the selection end of the selector in the output mapping control module electrically connected to pin m.

5. A method for mapping input and output functions and pins in a chip according to claim 4, characterized in that: For the output mapping control module electrically connected to pin 1, the first bit of information output by output mapping decoder 1 is input to the selection end of the first selector, the first bit of information output by output mapping decoder 2 is input to the selection end of the second selector, and so on, the first bit of information output by output mapping decoder j is input to the selection end of the last selector; For the output mapping control module electrically connected to pin 2, the second bit of information output by output mapping decoder j is input to the selection end of the first selector, the second bit of information output by output mapping decoder j-1 is input to the selection end of the second selector, and so on, the second bit of information output by output mapping decoder 1 is input to the selection end of the last selector; And so on: For the output mapping control module electrically connected to the pin j-1, the m-1th bit information output by the output mapping decoder 1 is input to the selection end of the first selector, the m-1th bit information output by the output mapping decoder 2 is input to the selection end of the second selector, and so on, the m-1th bit information output by the output mapping decoder j is input to the selection end of the last selector; For the output mapping control module electrically connected to pin j, the m-th bit information output by the output mapping decoder j is input to the selection end of the first selector, the m-th bit information output by the output mapping decoder j-1 is input to the selection end of the second selector, and so on, the m-th bit information output by the output mapping decoder one is input to the selection end of the last selector.

6. The method for mapping input and output functions and pins in a chip according to claim 1, characterized in that: The m pins do not include a power pin.

7. A method for mapping input and output functions and pins in a chip according to claim 1 or 6, characterized in that: The m pins do not include a ground pin.

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