Chip power consumption control method, device, equipment, medium, product and communication system

Abstract

The present application relates to a chip power consumption control method, device, equipment, medium, product and communication system. The method includes: obtaining chip configuration information of each chip on the daisy chain; the chip configuration information includes interface configuration information of the general input and output interface in each chip, the number of sampling channels or at least one of the communication positions on the above daisy chain; based on the chip configuration information, determining at least one chip to be adjusted with power consumption difference and the type of power consumption difference of the chip to be adjusted from each chip; the chip to be adjusted includes a chip configured with a pull-down resistor, or, a chip to be adjusted determined based on a reference chip in each chip; according to the power consumption adjustment scheme corresponding to the power consumption difference type, the power consumption of the chip to be adjusted is controlled. This method can effectively balance the power consumption difference of each chip on the daisy chain, thereby reducing the impact on the power consumption of the battery cell and enhancing the balancing ability of the battery cell.

Description

Technical Field

[0001] The present application relates to the field of communication system control technology, and in particular to a chip power consumption control method, device, electronic device, storage medium, computer program product and communication system. Background Art

[0002] In electric vehicles and other power-driven equipment, the power-consuming device can be considered as the core component of the equipment. The battery system of the power-consuming device is usually composed of hundreds of battery cells combined in the form of modules. Among them, the status data of the battery cell, such as the battery cell voltage and current, is important data for the battery management system when managing the battery.

[0003] At present, the mainstream communication method of the battery system is to use the Analog Front End (AFE) chip to collect the status data of the battery cell, and transmit the status data to the Battery Management System (BMS) in a daisy chain communication mode, so that the battery management system can manage the battery according to the collected status data.

[0004] When the chip is working, it draws power directly from the corresponding battery cell, which will consume a certain amount of the battery cell capacity. If there are differences in power consumption between the chips, these power consumption differences will easily lead to an unbalanced state of charge (SOC) of the battery cells in the battery system after long-term accumulation, and the voltage difference between the battery cells will increase, affecting the battery cell performance. Summary of the invention

[0005] Based on this, it is necessary to provide a chip power consumption control method, device, electronic device, computer-readable storage medium, computer program product and communication system that can balance the power consumption differences between chips in order to address the above technical problems.

[0006] In a first aspect, the present application provides a chip power consumption control method, the method comprising:

[0007] Obtain chip configuration information of each chip on the daisy chain; the chip configuration information includes at least one of interface configuration information of a general input / output interface in each of the chips, the number of sampling channels, or a communication position on the daisy chain;

[0008] Based on the chip configuration information, at least one chip to be adjusted having power consumption difference and the power consumption difference type of the chip to be adjusted are determined from the chips; the chip to be adjusted includes a chip configured with a pull-down resistor, or a chip to be adjusted determined based on a reference chip among the chips;

[0009] The power consumption of the chip to be adjusted is controlled according to the power consumption adjustment scheme corresponding to the power consumption difference type.

[0010] In the above embodiment, by acquiring the chip configuration information of each chip on the daisy chain, at least one chip to be adjusted with power consumption difference and the type of power consumption difference of the chip to be adjusted can be determined from each chip based on the chip configuration status of each chip reflected by the chip configuration information. According to the type of power consumption difference of the chip to be adjusted, a power consumption adjustment scheme matching the chip configuration status is determined for the chip to be adjusted. Subsequently, power consumption of the chip to be adjusted is controlled according to the power consumption adjustment scheme. This enables reasonable power consumption regulation of the chip to be adjusted, effectively balancing the power consumption differences of each chip on the daisy chain, thereby reducing the impact on the power consumption of the battery cell and enhancing the balancing capability of the battery cell.

[0011] In some of the embodiments, the chip configuration information includes interface configuration information of a general purpose input and output interface in each of the chips;

[0012] The step of determining, based on the chip configuration information, at least one chip to be adjusted having power consumption differences from among the chips, and the power consumption difference types of the chips to be adjusted includes:

[0013] Based on the interface configuration information of the universal input / output interface in each of the chips, the pull-down resistor configuration of each of the universal input / output interfaces is determined; the pull-down resistor is configured according to the difference in the number of interfaces of the universal input / output interface in each of the chips;

[0014] Determine the chip to which the universal input / output interface provided with the pull-down resistor belongs as the chip to be adjusted;

[0015] Determining that the power consumption difference type of the chip to be adjusted includes interface resource difference.

[0016] In the above embodiment, the main control module can quickly determine the chip to be adjusted that has interface resource differences with other chips from various chips through the interface configuration information of the general input and output interface in the chip, thereby effectively improving the efficiency and accuracy of determining the chip to be adjusted and the power consumption difference type of the chip to be adjusted.

[0017] In some of these embodiments, the power consumption adjustment scheme corresponding to the interface resource difference includes high-level regulation;

[0018] The controlling the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the power consumption difference type includes:

[0019] Determining the number of universal input and output interfaces of each of the chips to be adjusted according to the interface configuration information of each of the chips;

[0020] Based on the number of the general input and output interfaces and the preset corresponding relationship between the number of interfaces and the high-level on-time, determining the high-level on-time of each chip to be adjusted;

[0021] According to the high level start-up time of each chip to be adjusted, the universal input and output interface of each chip to be adjusted is controlled to output a high level signal.

[0022] In the above embodiment, after the main control module determines that the power consumption difference type of the chip to be adjusted includes interface resource differences, it can quickly determine the high-level turn-on time of the chip to be adjusted according to the preset correspondence between the number of interfaces and the high-level turn-on time, and the number of general input and output interfaces of the chip to be adjusted, and then control the general input and output interface of the chip to be adjusted to output a high-level signal according to the determined high-level turn-on time, thereby effectively improving the chip adjustment accuracy and adjustment efficiency of the chip to be adjusted with interface resource differences, thereby improving the control efficiency of chip power consumption control.

[0023] In some of the embodiments, the chip configuration information includes the number of sampling channels of each of the chips;

[0024] The step of determining, based on the chip configuration information, at least one chip to be adjusted having power consumption differences from among the chips, and the power consumption difference types of the chips to be adjusted includes:

[0025] Based on the number of sampling channels of each of the chips, determining a first reference chip having the largest number of sampling channels from among the chips;

[0026] Determine a channel quantity comparison value that matches the reference sampling channel quantity according to the reference sampling channel quantity of the first reference chip and a preset correspondence between the sampling channel quantity and the quantity comparison value;

[0027] A chip whose number of sampling channels is smaller than the channel number comparison value is determined as a chip to be adjusted, and it is determined that the power consumption difference type of the chip to be adjusted includes a channel number difference.

[0028] In the above embodiment, the main control module can quickly determine the chip to be adjusted with a difference in the number of channels from the chips by comparing the number of sampling channels of each chip, thereby effectively improving the efficiency and accuracy of determining the chip to be adjusted and the type of power consumption difference of the chip to be adjusted.

[0029] In some of these embodiments, the power consumption adjustment scheme corresponding to the difference in the number of channels includes starting a current source;

[0030] The controlling the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the power consumption difference type includes:

[0031] Determine a channel quantity difference between the sampling channel quantity of the chip to be adjusted and the channel quantity comparison value;

[0032] Determine a target startup duration of the current source that matches the difference in the number of channels according to a preset corresponding relationship between the difference in the number of channels and the startup duration of the current source;

[0033] The current source in the chip to be adjusted is controlled to start running based on the current source target startup time.

[0034] In the above embodiment, the main control module determines a matching current source target startup duration for the current source in the chip to be adjusted by using the channel number difference between the sampling channel number of the chip to be adjusted and the channel number comparison value, and controls the startup operation of the current source in the chip to be adjusted based on the current source target startup duration. The power consumption difference caused by the small number of chip sampling channels can be offset by increasing the operating power consumption of the chip to be adjusted, while improving the accuracy of chip power consumption control.

[0035] In some embodiments, the chip configuration information includes a communication position of each of the chips on the daisy chain;

[0036] The step of determining, based on the chip configuration information, at least one chip to be adjusted having power consumption differences from among the chips, and the power consumption difference types of the chips to be adjusted includes:

[0037] Based on the communication position of each chip in the daisy chain, determining a normal sending time required for each chip to send valid communication data;

[0038] Determine the chip with the longest normal transmission time as the second reference chip, and determine the other chips except the second reference chip as the chips to be adjusted;

[0039] Determining the power consumption difference type of each chip to be adjusted includes communication position difference.

[0040] In the above embodiment, the main control module determines the normal sending time required for each chip to send valid communication data through the communication position of each chip in the daisy chain, and can quickly determine the chip to be adjusted with a difference in communication position from each chip based on the normal sending time, thereby effectively improving the efficiency and accuracy of determining the chip to be adjusted and the type of power consumption difference of the chip to be adjusted.

[0041] In some of these embodiments, the power consumption adjustment scheme corresponding to the communication location difference includes increasing the communication duration;

[0042] The controlling the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the power consumption difference type includes:

[0043] For each chip to be adjusted, calculating the duration difference between the reference normal transmission duration of the second reference chip and the normal transmission duration of the chip to be adjusted;

[0044] Determine the duration difference as the communication compensation duration of the chip to be adjusted;

[0045] When the normal communication of each chip to be adjusted is completed, each chip to be adjusted is controlled to send invalid communication data based on the communication compensation time length of each chip to be adjusted.

[0046] In the above embodiment, the main control module calculates the communication compensation time of each chip to be adjusted, and controls each chip to be adjusted to send invalid communication data based on the communication compensation time, so that the communication time of each chip in the communication process can be consistent, thereby effectively balancing the power consumption differences of each chip on the daisy chain, thereby reducing the impact on the power consumption of the battery cell and enhancing the balancing ability of the battery cell.

[0047] In a second aspect, the present application provides a chip power consumption control device, the device comprising:

[0048] A configuration information acquisition module, used to acquire chip configuration information of each chip on the daisy chain; the chip configuration information includes at least one of interface configuration information of a general input / output interface in each of the chips, the number of sampling channels, or a communication position on the daisy chain;

[0049] A chip to be adjusted determining module, used to determine at least one chip to be adjusted having a power consumption difference from the chips, and a power consumption difference type of the chip to be adjusted, based on the chip configuration information; the chip to be adjusted includes a chip configured with a pull-down resistor, or a chip to be adjusted determined based on a reference chip among the chips;

[0050] The power consumption control module is used to control the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the power consumption difference type.

[0051] In a third aspect, the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0052] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above method when executed by a processor.

[0053] In a fifth aspect, the present application provides a computer program product, including a computer program, which implements the steps of the above method when executed by a processor.

[0054] In a sixth aspect, the present application provides a communication system, the communication system comprising a daisy chain, wherein the daisy chain is configured with various chips and a main control module;

[0055] For each of the chips, the number of sampling channels of the chip is consistent with the number of general input and output interfaces;

[0056] The main control module is used to implement the steps of the above method.

[0057] In some embodiments, the chip includes a pull-down resistor configuration chip; the pull-down resistor configuration chip is determined according to the difference in the number of interfaces of the universal input and output interfaces of each of the chips;

[0058] The universal input and output interfaces of the pull-down resistor configuration chip are all configured with pull-down resistors;

[0059] The above-mentioned chip power consumption control method, device, electronic device, storage medium, computer program product and communication system can obtain the chip configuration information of each chip on the daisy chain, and based on the chip configuration of each chip reflected by the chip configuration information, determine at least one chip to be adjusted with power consumption difference from each chip, and the type of power consumption difference of the chip to be adjusted; according to the type of power consumption difference of the chip to be adjusted, determine a power consumption adjustment scheme that matches the chip configuration for the chip to be adjusted, and then control the power consumption of the chip to be adjusted according to the power consumption adjustment scheme, so as to reasonably regulate the power consumption of the chip to be adjusted, effectively balance the power consumption difference of each chip on the daisy chain, thereby reducing the impact on the power consumption of the battery cell and enhancing the balancing ability of the battery cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 It is a structural schematic diagram of a communication system to which the chip power consumption control method is applied in some embodiments;

[0061] Figure 2 is a schematic diagram of the configuration of the pull-down resistor in some embodiments;

[0062] Figure 3 A schematic diagram of a process flow of a chip power consumption control method in some embodiments;

[0063] Figure 4 A schematic diagram of a flow chart of determining at least one chip to be adjusted having power consumption difference and the power consumption difference type of the chips to be adjusted from various chips based on chip configuration information in some embodiments;

[0064] Figure 5 A schematic diagram of a flow chart of controlling power consumption of a chip to be adjusted according to a power consumption adjustment scheme corresponding to a power consumption difference type in some embodiments;

[0065] Figure 6A schematic diagram of a flow chart of determining at least one chip to be adjusted having power consumption difference and the power consumption difference type of the chips to be adjusted from various chips based on chip configuration information in some embodiments;

[0066] Figure 7 A schematic diagram of a flow chart of controlling power consumption of a chip to be adjusted according to a power consumption adjustment scheme corresponding to a power consumption difference type in some embodiments;

[0067] Figure 8 A schematic diagram of a flow chart of determining at least one chip to be adjusted having power consumption difference and the power consumption difference type of the chips to be adjusted from various chips based on chip configuration information in some embodiments;

[0068] Fig. 9 A schematic diagram of the communication positions of a daisy chain including two chips in some embodiments;

[0069] Fig.10 A schematic diagram of a flow chart of controlling power consumption of a chip to be adjusted according to a power consumption adjustment scheme corresponding to a power consumption difference type in some embodiments;

[0070] Fig.11 Schematic diagram of the flow of chip power consumption control method in other embodiments;

[0071] Fig.12 It is a structural block diagram of a chip power consumption control device in some embodiments;

[0072] Fig.13 1 is a diagram of the internal structure of a computer device in some embodiments. DETAILED DESCRIPTION

[0073] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0075] Reference to "embodiments" herein means that the specific features, structures, or characteristics described in conjunction with the embodiments may be included in at least some embodiments of the present application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0076] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0077] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0078] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0079] The battery system can be considered as the heart of electric vehicles and other electric drive equipment, which is usually composed of hundreds of cells in the form of modules. In order to manage the battery system more accurately and efficiently, the battery management system needs to obtain the status data of each cell in the battery system.

[0080] At present, the mainstream communication method of the battery system is to use the analog front end (AFE) chip to collect the status data of the battery cell, and transmit the status data to the battery management system (BMS) in a daisy chain communication mode, so that the battery management system can manage the battery according to the collected status data. However, when the chip is working, it directly draws power from the corresponding battery cell, which will consume a certain amount of battery cell capacity. If there are power consumption differences between the chips, these power consumption differences will be superimposed on the power drive device side, such as the electric vehicle side for a long time, which will easily lead to an unbalanced state of charge (SOC) of the battery cells in the battery system, increase the voltage difference between the battery cells, and affect the performance of the battery cells.

[0081] In order to balance the power consumption differences between chips, the chip configuration information of each chip on the daisy chain can be obtained. Based on the chip configuration of each chip reflected by the chip configuration information, at least one chip to be adjusted with power consumption differences and the type of power consumption difference of the chip to be adjusted are determined from each chip. According to the type of power consumption difference of the chip to be adjusted, a power consumption adjustment scheme matching the chip configuration is determined for the chip to be adjusted. Subsequently, the power consumption of the chip to be adjusted is controlled according to the power consumption adjustment scheme. This enables reasonable power consumption regulation of the chip to be adjusted, effectively balancing the power consumption differences of the chips on the daisy chain, thereby reducing the impact on the power consumption of the battery cells and enhancing the balancing ability of the battery cells.

[0082] The chip power consumption control method provided in the embodiment of the present application can be applied to Figure 1 In the communication system shown in FIG. , the communication system includes a daisy chain 100 , on which chips 101 and a main control module 102 are configured.

[0083] The daisy chain 100 is a communication link of a linear topology structure, in which the chips 101 are connected one by one in a serial connection manner to form a chain, and each chip 101 can only communicate with the chip 101 directly adjacent to it.

[0084] Chip 101 is an analog front end (AFE) chip used for collecting status data of a battery cell, and is also a chip used by a control module on chip (CMC) module.

[0085] The cell sampling channel of the chip 101 is a signal acquisition channel for collecting analog signals of the cell status data and converting them into digital signals for subsequent processing. It can be understood that each chip 101 can include multiple cell sampling channels to facilitate simultaneous collection of the status data of multiple cells.

[0086] The general purpose input / output (GPIO) interface of chip 101 is a digital interface for connecting and controlling external devices. It consists of a group of pins, and can communicate and interact with external devices by controlling the level status of these pins. The GPIO interface has two major functions: input and output, such as receiving signal data from external devices and sending the internal status of chip 101 as output signals to external devices.

[0087] In order to reduce the power consumption differences within each chip, for each chip 101, the number of battery cell sampling channels of chip 101 is consistent with the number of universal input and output interfaces. By keeping the number of battery cell sampling channels of each chip 101 consistent with the number of universal input and output interfaces, the power consumption differences caused by chip resource imbalance problems can be reduced.

[0088] Among them, the main control module 102 can be considered as the core module in the communication system and the core node on the daisy chain 100. The main control module 102 can communicate with each chip 101 on the daisy chain 100 and coordinate and control each chip to improve the accuracy and synchronization of information transmission.

[0089] In order to enable the main control module 102 to control the power consumption of each chip, the designer can pre-build a power consumption control program in the main control module 102. When the main control module 102 is mounted on the daisy chain 100 and runs, the main control module 102 can obtain the chip configuration information of each chip 101 on the daisy chain 100, and based on the chip configuration information, determine at least one chip to be adjusted with power consumption difference and the power consumption difference type of the chip to be adjusted from each chip 101, and control the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the power consumption difference type.

[0090] In terms of hardware, the communication system mentioned above can reduce the power consumption difference caused by the chip resource imbalance problem by keeping the number of battery cell sampling channels of each chip consistent with the number of general-purpose input and output interfaces. In terms of software, by pre-configuring the power consumption control program in the main control module, the main control module can obtain the chip configuration information of each chip on the daisy chain, and based on the chip configuration of each chip reflected in the chip configuration information, determine at least one chip to be adjusted with power consumption difference from each chip, and the type of power consumption difference of the chip to be adjusted. According to the type of power consumption difference of the chip to be adjusted, determine the power consumption adjustment scheme that matches the chip configuration for the chip to be adjusted, and then control the power consumption of the chip to be adjusted according to the power consumption adjustment scheme. It can reasonably regulate the power consumption of the chip to be adjusted, effectively balance the power consumption difference of each chip on the daisy chain, and thus reduce the impact on the power consumption of the battery cell and enhance the balancing ability of the battery cell.

[0091] In some embodiments, each chip on the daisy chain includes a pull-down resistor configuration chip, which can be determined according to the difference in the number of interfaces of the universal input and output interfaces of each chip. The universal input and output interfaces of the pull-down resistor configuration chip are all configured with pull-down resistors.

[0092] The pull-down resistor configuration chip is a chip in each chip on the daisy chain that needs to be configured with a pull-down resistor for the general input and output interface. Designers can determine the difference in the number of interfaces of each chip according to the number of interfaces of the general input and output interfaces of each chip, and determine the pull-down resistor configuration chip from each chip based on the difference in the number of interfaces.

[0093] In some of the embodiments, the designer may determine the pull-down resistor configuration chip in each chip that meets the interface resource shortage condition according to the number of interfaces of the general input and output interfaces of each chip.

[0094] In some of the embodiments, the designer may determine the reference chip with the highest number of interfaces among the chips according to the number of interfaces of the universal input / output interfaces of each chip, and then determine the interface number comparison value that matches the interface number of the reference chip according to the number of interfaces of the reference chip and the preset correspondence between the number of interfaces and the interface number comparison value. The number of interfaces of each chip is compared with the interface number comparison value, and the chip with the number of interfaces less than the interface number comparison value is determined as a pull-down resistor configuration chip, and the designer can configure a pull-down resistor for the universal input / output interface of the pull-down resistor configuration chip.

[0095] Among them, a pull-down resistor is a resistor used in circuit design to pull the voltage of a specific node down to a low level, usually a low potential or 0V, such as Figure 2 As shown, the pull-down resistor can be configured between the pin of the general input / output interface to be controlled and the ground. By configuring the pull-down resistor for the general input / output interface of the pull-down resistor configuration chip, the output level of the input / output interface can be improved.

[0096] In the above embodiment, by determining the pull-down resistor configuration chip from each chip and configuring a pull-down resistor for the universal input / output interface in the pull-down resistor configuration chip, a hardware basis can be provided for subsequent regulation of the universal input / output interface in the pull-down resistor configuration chip to output a high level, thereby increasing the power consumption of the pull-down resistor configuration chip, thereby reducing the possibility of differences in chip power consumption due to uneven allocation of universal input / output interface resources.

[0097] In some embodiments, Figure 3 As shown, a chip power consumption control method is provided, and the method is applied to Figure 1 Taking the main control module 102 in the example as an example, the following steps are included:

[0098] S302, obtaining chip configuration information of each chip in the daisy chain.

[0099] The chip configuration information is information data used to characterize the configuration status of each chip on the daisy chain. The chip configuration information can be generated by designers according to actual configuration status when building a daisy chain communication system.

[0100] In some optional embodiments, the main control module may obtain chip configuration information of each chip on the daisy chain.

[0101] In some of the embodiments, after generating chip configuration information, the designer may write the chip configuration information into a power consumption control program of the main control module, and the main control module may obtain chip configuration information of each chip on the daisy chain based on the power consumption control program.

[0102] S304 : Based on the chip configuration information, determine at least one chip to be adjusted having power consumption difference from among the chips, and the power consumption difference type of the chip to be adjusted.

[0103] The chip to be adjusted is a chip that has power consumption differences and needs to be controlled by the main control module to adjust the power consumption. The power consumption difference type is a type parameter used to classify the difference causes that cause the difference in chip power consumption. It can be understood that each chip to be adjusted can correspond to at least one power consumption difference type, and each power consumption difference type corresponds to an adapted power consumption adjustment solution.

[0104] In some optional embodiments, the main control module may determine at least one chip to be adjusted having power consumption difference and the power consumption difference type of the chip to be adjusted from among the chips based on the acquired chip configuration information.

[0105] In some of the embodiments, the chip configuration information may include the chip identification of each chip, and the main control module can determine at least one chip to be adjusted with power consumption difference and the power consumption difference type of the chip to be adjusted from each chip based on the chip identification and the preset correspondence between the chip identification and the power consumption difference type.

[0106] S306: Control the power consumption of the chip to be adjusted according to the power consumption adjustment solution corresponding to the power consumption difference type.

[0107] Among them, the power consumption adjustment scheme is the adjustment scheme that the main control module needs to use when controlling the power consumption of the chip to be adjusted. The power consumption of the chip to be adjusted is controlled according to the power consumption adjustment scheme corresponding to the power consumption difference type. It can offset the power consumption difference of the chip to be adjusted to the greatest extent, and effectively balance the power consumption difference of each chip in the daisy chain, thereby reducing the impact on the power consumption of the battery cell and enhancing the balancing ability of the battery cell.

[0108] In some optional embodiments, the main control module can determine a power consumption adjustment scheme that matches the power consumption difference type of the chip to be adjusted, and a preset correspondence between the power consumption difference type and the power consumption adjustment scheme, and control the power consumption of the chip to be adjusted according to the power consumption adjustment scheme, so that the power consumption differences of the chips on the daisy chain are balanced to the greatest extent.

[0109] In the above embodiment, by acquiring the chip configuration information of each chip on the daisy chain, at least one chip to be adjusted with power consumption difference and the type of power consumption difference of the chip to be adjusted can be determined from each chip based on the chip configuration status of each chip reflected by the chip configuration information. According to the type of power consumption difference of the chip to be adjusted, a power consumption adjustment scheme matching the chip configuration status is determined for the chip to be adjusted. Subsequently, power consumption of the chip to be adjusted is controlled according to the power consumption adjustment scheme. This enables reasonable power consumption regulation of the chip to be adjusted, effectively balancing the power consumption differences of each chip on the daisy chain, thereby reducing the impact on the power consumption of the battery cell and enhancing the balancing capability of the battery cell.

[0110] How to determine the power consumption difference type between the chip to be adjusted and the chip to be adjusted is a key step in performing power consumption balancing control on each chip on the daisy chain. In addition to being set by the designer, in order to improve the universality of the power consumption control of the main control module, the process of determining the chip to be adjusted and the power consumption difference type of the chip to be adjusted can be executed by the main control module. The following will illustrate the process of the main control module determining the chip to be adjusted and the power consumption difference type of the chip to be adjusted through several embodiments.

[0111] In some embodiments, the chip configuration information includes interface configuration information of the general input and output interfaces in each chip, such as Figure 4 As shown, S304, based on the chip configuration information, determining at least one chip to be adjusted having power consumption difference from each chip, and the power consumption difference type of the chip to be adjusted, includes:

[0112] S402 , based on the interface configuration information of the general input / output interface in each chip, determine the pull-down resistor configuration of each general input / output interface.

[0113] The interface configuration information is information data used to reflect the configuration of the general input and output interfaces in each chip. For example, the interface configuration information may include the configuration of the pull-down resistor, the number of general input and output interfaces of each chip, and the like.

[0114] The pull-down resistor configuration refers to whether the chip's general input / output interface is configured with a pull-down resistor. The pull-down resistor can be configured by the designer according to the difference in the number of general input / output interfaces in each chip. For example, the designer can configure a pull-down resistor for the chip's general input / output interface when the chip meets the interface resource shortage condition based on the number of general input / output interfaces of the chip.

[0115] In some optional embodiments, the main control module may determine the pull-down resistor configuration of the universal input / output interface of each chip based on the interface configuration information of the universal input / output interface in each chip, and determine each universal input / output interface provided with a pull-down resistor.

[0116] S404: Determine the chip to which the universal input / output interface provided with the pull-down resistor belongs as the chip to be adjusted.

[0117] In some optional embodiments, the main control module may determine the chips to which the general input / output interfaces provided with pull-down resistors belong, and determine the chips to which the general input / output interfaces provided with pull-down resistors belong as the chips to be adjusted.

[0118] S406: Determine whether the power consumption difference type of the chip to be adjusted includes interface resource difference.

[0119] In some optional embodiments, since the universal input and output interface of the chip to be adjusted is provided with a pull-down resistor, it means that during the hardware construction process, the designers have taken into account the differences in interface resources between the chip and other chips, and have provided a pull-down resistor that can be used to offset the difference. Therefore, the main control module can determine that the power consumption difference type of the above-mentioned chip to be adjusted includes interface resource differences.

[0120] In the above embodiment, the main control module can quickly determine the chip to be adjusted that has interface resource differences with other chips from various chips through the interface configuration information of the general input and output interface in the chip, thereby effectively improving the efficiency and accuracy of determining the chip to be adjusted and the power consumption difference type of the chip to be adjusted.

[0121] After determining the chip to be adjusted with interface resource differences, the main control module can control the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the interface resource differences. In some embodiments, the power consumption adjustment scheme corresponding to the interface resource differences includes high-level regulation. Figure 5 As shown, S306, according to the power consumption adjustment scheme corresponding to the power consumption difference type, the power consumption of the chip to be adjusted is controlled, including:

[0122] S502 : Determine the number of general input and output interfaces of each chip to be adjusted according to the interface configuration information of each chip.

[0123] In some optional embodiments, the interface configuration information includes the number of general input and output interfaces of each chip. The main control module can determine the number of general input and output interfaces of each chip to be adjusted from the interface configuration information of each chip according to the chip identification of each chip to be adjusted.

[0124] S504 , based on the number of general input and output interfaces and the preset corresponding relationship between the number of interfaces and the high-level on-time, determine the high-level on-time of each chip to be adjusted.

[0125] Among them, the preset correspondence between the number of interfaces and the high-level turn-on duration can be generated in advance by the designer based on experimental data or empirical data. The designer can determine the corresponding high-level turn-on durations of chips with different numbers of interfaces under the condition of power consumption balance based on the experimental data or empirical data, and bind the number of interfaces with the corresponding high-level turn-on durations to obtain the preset correspondence between the number of interfaces and the high-level turn-on duration. It can be understood that the designer can write the preset correspondence between the number of interfaces and the high-level turn-on duration into the power consumption control program of the main control module in advance, so that the main control module can directly call the preset correspondence between the number of interfaces and the high-level turn-on duration based on the power consumption control program.

[0126] In some optional embodiments, after determining the number of universal input / output interfaces of each chip to be adjusted, the main control module can, for each chip to be adjusted, search for a high-level turn-on time that matches the number of universal input / output interfaces of the chip to be adjusted in a preset correspondence between the number of interfaces and the high-level turn-on time, and determine the high-level turn-on time as the high-level turn-on time of the chip to be adjusted.

[0127] S506 , controlling the universal input / output interface of each chip to be adjusted to output a high-level signal according to the high-level start-up time of each chip to be adjusted.

[0128] In some embodiments, the main control module can control the general input and output interface of each chip to be adjusted to output a high-level signal according to the high-level start-up time of each chip to be adjusted, and offset the power consumption difference caused by the interface resource difference of the chip to be adjusted by outputting the high-level signal.

[0129] In the above embodiment, after the main control module determines that the power consumption difference type of the chip to be adjusted includes interface resource differences, it can quickly determine the high-level turn-on time of the chip to be adjusted according to the preset correspondence between the number of interfaces and the high-level turn-on time, and the number of general input and output interfaces of the chip to be adjusted, and then control the general input and output interface of the chip to be adjusted to output a high-level signal according to the determined high-level turn-on time, thereby effectively improving the chip adjustment accuracy and adjustment efficiency of the chip to be adjusted with interface resource differences, thereby improving the control efficiency of chip power consumption control.

[0130] In addition to the interface resource differences, in other embodiments, such as Figure 6 As shown, the chip configuration information includes the number of sampling channels of each chip. S304, based on the chip configuration information, determining at least one chip to be adjusted with power consumption difference from each chip and the power consumption difference type of the chip to be adjusted, including:

[0131] S602 : Based on the number of sampling channels of each chip, determine a first reference chip having the largest number of sampling channels from among the chips.

[0132] In some optional embodiments, the main control module can sort the number of sampling channels of each chip according to the quantity, for example, in ascending order or descending order, and determine the chip with the largest number of sampling channels from each chip according to the sorting result, and determine the chip with the largest number of sampling channels as the first reference chip.

[0133] S604 , determining a channel quantity comparison value that matches the reference sampling channel quantity according to the reference sampling channel quantity of the first reference chip and a preset correspondence between the sampling channel quantity and the quantity comparison value.

[0134] The reference sampling channel number refers to the sampling channel number of the first reference chip. The channel number comparison value is a judgment parameter used to determine whether the chip has a power consumption difference caused by using a small number of channels. The channel number comparison value can be determined in real time by the number of sampling channels of each chip in the daisy chain.

[0135] The preset correspondence between the number of sampling channels and the quantity comparison value can be generated in advance by the designer based on experimental data or empirical data. The designer can determine the quantity comparison values ​​corresponding to different numbers of reference sampling channels when the power consumption of each chip is balanced based on the experimental data or empirical data, and bind each reference sampling channel number with its corresponding quantity comparison value to obtain the preset correspondence between the number of sampling channels and the quantity comparison value. It can be understood that the designer can write the preset correspondence between the number of sampling channels and the quantity comparison value into the power consumption control program of the main control module in advance, so that the main control module can directly call the preset correspondence between the number of sampling channels and the quantity comparison value based on the power consumption control program.

[0136] In some optional embodiments, after determining the first reference chip, the main control module may search for a quantity comparison value matching the reference sampling channel quantity in a preset correspondence between the sampling channel quantity and the quantity comparison value according to the reference sampling channel quantity of the first reference chip.

[0137] S606: Determine a chip whose number of sampled channels is smaller than the channel number comparison value as a chip to be adjusted, and determine that the power consumption difference type of the chip to be adjusted includes a channel number difference.

[0138] In some optional embodiments, after obtaining a quantity comparison value that matches the benchmark sampling channel quantity, the main control module can compare the number of sampling channels of each chip with the channel quantity comparison value respectively. For each chip, when the number of sampling channels is less than the channel quantity comparison value, it can be considered that the chip has a smaller number of sampling channels among all chips. Compared with the chip with a number of sampling channels greater than or equal to the channel quantity comparison value, that is, the chip with a larger number of sampling channels, there may be a power consumption difference problem caused by the smaller number of channels. Therefore, the main control module can determine the chip with a number of sampling channels less than the channel quantity comparison value as the chip to be adjusted, and determine that the power consumption difference type of the chip to be adjusted includes the channel quantity difference.

[0139] In the above embodiment, the main control module can quickly determine the chip to be adjusted with a difference in the number of channels from the chips by comparing the number of sampling channels of each chip, thereby effectively improving the efficiency and accuracy of determining the chip to be adjusted and the type of power consumption difference of the chip to be adjusted.

[0140] After determining the chip to be adjusted that has a difference in the number of channels, the main control module can control the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the difference in the number of channels. In some embodiments, the power consumption adjustment scheme corresponding to the difference in the number of channels includes starting the current source. Figure 7 As shown, S306, according to the power consumption adjustment scheme corresponding to the power consumption difference type, the power consumption of the chip to be adjusted is controlled, including:

[0141] S702, determining a channel quantity difference between the sampling channel quantity of the chip to be adjusted and a channel quantity comparison value.

[0142] In some optional embodiments, when the main control module determines that the power consumption difference type of the chip to be adjusted includes a channel number difference, for each chip to be adjusted, the main control module can obtain the channel number difference between the sampled channel number of the chip to be adjusted and the channel number comparison value when the channel number comparison was performed previously.

[0143] S704, determining a current source target startup duration that matches the channel quantity difference according to a preset correspondence between the channel quantity difference and the current source startup duration.

[0144] Among them, the current source is a chip component pre-configured in the chip and used to consume the chip current. For example, the current source can be a resistor in the pre-configured chip or any other component that can consume the chip current. The main control chip is started by controlling the current source in the chip, which can increase the operating power consumption of the chip.

[0145] The preset correspondence between the difference in the number of channels and the startup time of the current source can also be generated in advance by the designer based on experimental data or empirical data. The designer can determine the corresponding current source startup time of the chips corresponding to different differences in the number of channels under the condition of power consumption balance based on the experimental data or empirical data, and bind the difference in the number of channels with the corresponding current source startup time to obtain the preset correspondence between the difference in the number of channels and the startup time of the current source. It can be understood that the designer can write the preset correspondence between the difference in the number of channels and the startup time of the current source into the power consumption control program of the main control module in advance, so that the main control module can directly call the preset correspondence between the difference in the number of channels and the startup time of the current source based on the power consumption control program.

[0146] In some optional embodiments, after obtaining the channel number difference between the sampling channel number of the chip to be adjusted and the channel number comparison value, the main control module can search for the current source startup duration that matches the channel number difference corresponding to the chip to be adjusted in the preset correspondence between the channel number difference and the current source startup duration, and determine the current source startup duration as the current source target startup duration of the chip to be adjusted.

[0147] S706 , controlling the current source in the chip to be adjusted to start running based on the target startup duration of the current source.

[0148] In some optional embodiments, the main control module can control the startup operation of the current source in the chip to be adjusted based on the target startup duration of the current source, and offset the power consumption difference caused by the small number of chip sampling channels by increasing the operating power consumption of the chip to be adjusted.

[0149] In the above embodiment, the main control module determines a matching current source target startup duration for the current source in the chip to be adjusted by using the channel number difference between the sampling channel number of the chip to be adjusted and the channel number comparison value, and controls the startup operation of the current source in the chip to be adjusted based on the current source target startup duration. The power consumption difference caused by the small number of chip sampling channels can be offset by increasing the operating power consumption of the chip to be adjusted, while improving the accuracy of chip power consumption control.

[0150] In addition to the above-mentioned interface resource differences and channel quantity differences, power consumption difference types can also include communication location differences.

[0151] In some embodiments, the chip configuration information includes the communication position of each chip in the daisy chain, such as Figure 8 As shown, S304, based on the chip configuration information, determining at least one chip to be adjusted having power consumption difference from each chip, and the power consumption difference type of the chip to be adjusted, includes:

[0152] S802, based on the communication position of each chip in the daisy chain, determine the normal sending time required for each chip to send valid communication data.

[0153] Among them, the communication position is the position information used to reflect the setting position of each chip in the daisy chain. The communication position can be the node serial number of the node where each chip is located in the daisy chain, such as the first chip, the second chip, or the node distance between each chip and the battery management system. For example, if the first chip is 1 node away from the battery management system, the communication position of the first chip is 1, and if the second chip is 2 node distances away from the battery management system, the communication position of the second chip is 2, and so on.

[0154] It is understandable that the communication position of each chip in the daisy chain is related to the power consumption required by each chip when communicating in the daisy chain. Take the example of a chip sending collected cell data to a battery management system. If there are two chips on the daisy chain, the communication positions of the two chips in the daisy chain are as follows: Fig. 9 As shown, it can be seen that from the first chip to the second chip, the communication distance between the chip and the battery management system gradually increases. However, since the communication principle of the daisy chain is that communication can only be transmitted with adjacent nodes, when sending the collected cell data to the battery management system, the second chip only needs to send the second cell data collected by itself to the first chip, and the first chip, in addition to sending the first cell data collected by itself to the battery management system, also needs to send the second cell data to the battery management system. Therefore, the data sending time of the first chip is longer, and the corresponding power consumption used during communication is also greater.

[0155] The normal transmission duration of the chip is the communication duration required for the chip to send valid communication data to other nodes. The normal transmission duration can be determined based on the reference duration for the chip to send communication data and the communication position of the chip in the daisy chain. The reference duration for sending communication data refers to the information transmission duration for the chip to send the valid data it needs to send. For example, Fig. 9 In the embodiment, the reference duration for the first chip to send communication data refers to the information sending duration required for the first chip to send the first battery cell data collected by itself, rather than the total information sending duration required for the first chip to send the first battery cell data and the second battery cell data.

[0156] Effective communication data refers to the data that needs to be transmitted when the power system is working normally, such as the battery cell status data collected by each chip, or the command signals sent by the battery management system to each chip.

[0157] In some optional embodiments, the main control module may determine the normal transmission time required for each chip to send valid communication data based on the communication position of each chip in the daisy chain.

[0158] In some of the embodiments, a preset correspondence between normal sending duration and communication position is configured in the main control module. For each chip, the main control module can determine the normal sending duration that matches the communication position from the preset correspondence between normal sending duration and communication position according to the communication position of the chip in the daisy chain, and determine the normal sending duration as the normal sending duration of the chip.

[0159] In some of the embodiments, the main control module is configured with a benchmark duration for the chip to send valid data. After obtaining the communication position of the chip in the daisy chain, the main control module can determine the normal sending duration of the chip based on the communication position of the chip, the benchmark duration and the calculation method of the normal sending duration.

[0160] S804: Determine the chip with the longest normal transmission time as the second reference chip, and determine the other chips except the second reference chip as chips to be adjusted.

[0161] In some optional embodiments, after determining the normal transmission time of each chip, the main control module can determine the chip with the longest normal transmission time from each chip based on the normal transmission time, and determine the chip with the longest normal transmission time as the second reference chip, and determine other chips except the second reference chip as chips to be adjusted.

[0162] In some optional embodiments, the main control module may sort the normal transmission time of each chip in ascending or descending order, and determine the chip with the longest normal transmission time from among the chips based on the sorting result.

[0163] S806: Determine whether the power consumption difference type of each chip to be adjusted includes a communication position difference.

[0164] In some optional embodiments, in order to avoid power consumption differences between chips due to different communication durations, the main control module can determine that the power consumption difference types of each chip to be adjusted include communication position differences, and then control the power consumption of each chip to be adjusted based on the power consumption adjustment scheme corresponding to the communication position difference.

[0165] In the above embodiment, the main control module determines the normal sending time required for each chip to send valid communication data through the communication position of each chip in the daisy chain, and can quickly determine the chip to be adjusted with a difference in communication position from each chip based on the normal sending time, thereby effectively improving the efficiency and accuracy of determining the chip to be adjusted and the type of power consumption difference of the chip to be adjusted.

[0166] After determining the chips to be adjusted that have communication position differences, the main control module can control the power consumption of the chips to be adjusted according to the power consumption adjustment scheme corresponding to the communication position differences. In some embodiments, the power consumption adjustment scheme corresponding to the communication position differences includes increasing the communication duration. Fig.10 As shown, S306, according to the power consumption adjustment scheme corresponding to the power consumption difference type, the power consumption of the chip to be adjusted is controlled, including:

[0167] S1002: For each chip to be adjusted, calculate a duration difference between a reference normal transmission duration of the second reference chip and a normal transmission duration of the chip to be adjusted.

[0168] In some optional embodiments, since the main control module has determined the normal transmission duration of each chip when performing duration comparison, for each chip to be adjusted, the main control module can calculate the duration difference between the benchmark normal transmission duration of the second benchmark chip and the normal transmission duration of the chip to be adjusted.

[0169] S1004: Determine the duration difference as the communication compensation duration of the chip to be adjusted.

[0170] The communication compensation duration is a duration compensation parameter used to reduce the difference in communication duration between each chip to be adjusted and the second reference chip during communication, and can also characterize the duration difference between the normal transmission duration of the chip to be adjusted and the second reference chip. By compensating the communication duration of each chip to be adjusted based on the communication compensation duration, the operating power consumption of each chip to be adjusted can be increased, offsetting the impact of uneven power consumption of each chip caused by differences in communication positions.

[0171] In some optional embodiments, the main control module may determine the duration difference between the reference normal transmission duration of the second reference chip and the normal transmission duration of the chip to be adjusted as the communication compensation duration of the chip to be adjusted.

[0172] S1006 , when the normal communication of each chip to be adjusted is completed, based on the communication compensation time length of each chip to be adjusted, control each chip to be adjusted to send invalid communication data.

[0173] Invalid communication data refers to invalid signals that do not contain any substantial content. The chip sends invalid communication data only to increase the communication power consumption of the chip, and will not cause disorder in the normal data transmission of the chip.

[0174] In some optional embodiments, when the normal communication of each chip to be adjusted is completed, the main control module can control each chip to be adjusted to send invalid communication data based on the communication compensation duration of each chip to be adjusted, so as to improve the operating power consumption of each chip to be adjusted and offset the impact of uneven power consumption of each chip caused by the difference in communication position.

[0175] In the above embodiment, the main control module calculates the communication compensation time of each chip to be adjusted, and controls each chip to be adjusted to send invalid communication data based on the communication compensation time, so that the communication time of each chip in the communication process can be consistent, thereby effectively balancing the power consumption differences of each chip on the daisy chain, thereby reducing the impact on the power consumption of the battery cell and enhancing the balancing ability of the battery cell.

[0176] It can be understood that the power consumption difference type of the chip to be adjusted may include at least one of the three power consumption difference types mentioned above, namely, interface resource difference, channel number difference, and communication position difference. The main control module can use the corresponding power consumption adjustment scheme to control the power consumption of the chip to be adjusted according to the power consumption difference type included in the chip to be adjusted. For example, the chip to be adjusted may include interface resource difference, channel number difference and communication position difference at the same time. The main control module can control the power consumption of the chip to be adjusted based on the respective power consumption adjustment schemes of interface resource difference, channel number difference and communication position difference.

[0177] In some embodiments, a chip power consumption control method is provided, which is applied to Figure 1 In the communication system shown, the communication system is used to configure the battery management system (BMS) to realize system communication. When building the communication system, the designer will configure the pull-down resistor configuration chip for each chip (AFE) that meets the interface resource shortage condition, and will configure the pull-down resistor for the general input and output (GPIO) interface of the chip to increase the power consumption of the AFE chip through high-level collaborative control during power consumption control.

[0178] At the same time, designers will also reasonably plan the number of sampling channels and GPIO channels used by each AFE chip to make the number of sampling channels and GPIO channels used by each AFE chip equal to each other, so as to reduce the power consumption difference caused by the imbalance of internal resources in the AFE chip.

[0179] like Fig.11 As shown, the chip power consumption control method includes the following steps:

[0180] S1101, obtaining chip configuration information of each chip in the daisy chain.

[0181] Among them, the chip configuration information of each chip may include interface configuration information of the GPIO interface in each chip, the number of cell voltage sampling channels of each chip, and the communication position of each chip on the daisy chain.

[0182] After obtaining the chip configuration information of each chip, the main control module can call different power consumption control queues to respectively execute the technical solutions of determining at least one chip to be adjusted from each chip and controlling the power consumption of the chip to be adjusted. The execution steps of each power consumption control queue are described below:

[0183] Among them, the power consumption control queue 1 can execute S1102-S1106.

[0184] S1102, based on the interface configuration information of the GPIO interface of each chip, determine the pull-down resistor configuration of each GPIO interface.

[0185] S1103: Determine the chip to which the GPIO interface provided with the pull-down resistor belongs as the chip to be adjusted.

[0186] The main control module may determine the chip to which the universal input / output interface provided with the pull-down resistor belongs as the chip to be adjusted, and determine that the power consumption difference type of the chip to be adjusted includes interface resource difference.

[0187] S1104, determining the number of GPIO interfaces of each chip to be adjusted.

[0188] S1105 , based on the number of GPIO interfaces and the preset corresponding relationship between the number of interfaces and the high-level on-time, determine the high-level on-time of each chip to be adjusted.

[0189] S1106 , controlling the GPIO interface of each chip to be adjusted to output a high level signal according to the high level start-up time of each chip to be adjusted.

[0190] Among them, the power consumption control queue 2 can execute S1107-S1112.

[0191] S1107 , based on the number of sampling channels of each chip, determine a first reference chip having the largest number of sampling channels from among the chips.

[0192] S1108, determining a channel quantity comparison value that matches the reference sampling channel quantity.

[0193] The main control module may determine a channel quantity comparison value that matches the reference sampling channel quantity according to the reference sampling channel quantity of the first reference chip and a preset correspondence between the sampling channel quantity and the quantity comparison value.

[0194] S1109, determining a chip whose number of sampling channels is less than the channel number comparison value as a chip to be adjusted.

[0195] The main control module may determine a chip whose number of sampling channels is less than the channel number comparison value as a chip to be adjusted, and determine that the power consumption difference type of the chip to be adjusted includes a channel number difference.

[0196] S1110, determining a channel quantity difference between the sampling channel quantity of the chip to be adjusted and a channel quantity comparison value.

[0197] S1111, determine a current source target startup duration that matches the difference in the number of channels.

[0198] The main control module can determine the target startup duration of the current source that matches the difference in the number of channels according to the preset corresponding relationship between the difference in the number of channels and the startup duration of the current source.

[0199] S1112, controlling the current source in the chip to be adjusted to start running based on the target startup duration of the current source.

[0200] Among them, the power consumption control queue 3 can execute S1113-S1117.

[0201] S1113, based on the communication position of each chip in the daisy chain, determine the normal sending time required for each chip to send valid communication data.

[0202] S1114, determining the chip with the longest normal transmission time as the second reference chip, and determining the other chips as chips to be adjusted.

[0203] The main control module may determine the chip with the longest normal transmission time as the second reference chip, determine other chips except the second reference chip as chips to be adjusted, and determine that the power consumption difference type of each chip to be adjusted includes communication position difference.

[0204] S1115, calculating a duration difference between a reference normal transmission duration of the second reference chip and a normal transmission duration of the chip to be adjusted.

[0205] The main control module may calculate, for each chip to be adjusted, a duration difference between a reference normal transmission duration of the second reference chip and a normal transmission duration of the chip to be adjusted.

[0206] S1116, determining the duration difference as the communication compensation duration of the chip to be adjusted.

[0207] S1117, based on the communication compensation duration of each chip to be adjusted, control each chip to be adjusted to send invalid communication data.

[0208] When normal communication of each chip to be adjusted is completed, the main control module can control each chip to be adjusted to send invalid communication data based on the communication compensation time length of each chip to be adjusted.

[0209] The above chip power consumption control method can minimize the power consumption difference between AFE chips, and further reduce the impact of chip communication on the power consumption of the battery cell. The current mainstream balancing method is to turn on the odd / even cells separately to achieve battery cell power consumption balance. This balancing method cannot turn on all cells sampled by the same chip at the same time. The above chip power consumption control method can be used for all cell balance, that is, there is no need to turn on the odd / even cells separately, but all cells sampled by the same chip can be turned on for a long time at the same time to cover all cells.

[0210] In some embodiments, by performing high-level regulation on each chip to be adjusted, the power consumption imbalance caused by differences in interface resources, sampling channel numbers, and communication positions can be offset. For example, the main control module can directly determine each chip to be adjusted that has differences in interface resources, sampling channel numbers, and communication positions, and determine the power consumption compensation value required for each chip to be adjusted under the condition of balanced power consumption. Then, based on each power consumption compensation value and the preset corresponding relationship between the power consumption compensation value and the high-level turn-on time, determine the high-level turn-on time that matches each power consumption compensation value, and determine the high-level turn-on time that matches each power consumption compensation value as the high-level turn-on time of the corresponding chip to be adjusted. Based on the high-level turn-on time of each chip to be adjusted, control the GPIO interface of each chip to be adjusted to output a high-level signal.

[0211] In the above embodiment, the designer can pre-configure a pull-down resistor for the GPIO interface of each chip, and then according to the above steps, it is only necessary to control the GPIO interface to output a high-level signal of a corresponding duration to achieve balanced power consumption of each battery cell.

[0212] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0213] Based on the same inventive concept, the embodiment of the present application also provides a chip power consumption control device for implementing the chip power consumption control method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more chip power consumption control device embodiments provided below can refer to the limitations of the chip power consumption control method above, and will not be repeated here.

[0214] In some embodiments, Fig.12 As shown, a chip power consumption control device 1200 is provided, comprising: a configuration information acquisition module 1201, a chip determination module 1202 to be adjusted and a power consumption control module 1203, wherein:

[0215] The configuration information acquisition module 1201 is used to acquire chip configuration information of each chip in the daisy chain.

[0216] The chip to be adjusted determining module 1202 is used to determine at least one chip to be adjusted having power consumption difference from various chips and the power consumption difference type of the chip to be adjusted based on the chip configuration information.

[0217] The power consumption control module 1203 is used to control the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the power consumption difference type.

[0218] In some embodiments, the chip configuration information includes interface configuration information of the general input / output interface in each chip. The module 1202 for determining the chip to be adjusted is used to: determine the pull-down resistor configuration of each general input / output interface based on the interface configuration information of the general input / output interface in each chip; configure the pull-down resistor according to the difference in the number of interfaces of the general input / output interface in each chip; determine the chip to which the general input / output interface provided with the pull-down resistor belongs as the chip to be adjusted; determine that the power consumption difference type of the chip to be adjusted includes interface resource difference.

[0219] In some embodiments, the power consumption adjustment scheme corresponding to the interface resource difference includes high-level regulation. The power consumption control module 1203 is used to: determine the number of general input and output interfaces of each chip to be adjusted according to the interface configuration information of each chip; determine the high-level turn-on time of each chip to be adjusted based on the number of general input and output interfaces and the preset corresponding relationship between the number of interfaces and the high-level turn-on time; and control the general input and output interface of each chip to be adjusted to output a high-level signal according to the high-level turn-on time of each chip to be adjusted.

[0220] In some embodiments, the chip configuration information includes the number of sampling channels of each chip. The chip to be adjusted determination module 1202 is used to: determine the first reference chip with the largest number of sampling channels from each chip based on the number of sampling channels of each chip; determine the channel number comparison value that matches the reference sampling channel number according to the reference sampling channel number of the first reference chip and the preset correspondence between the sampling channel number and the number comparison value; determine the chip with a sampling channel number less than the channel number comparison value as the chip to be adjusted, and determine that the power consumption difference type of the chip to be adjusted includes a channel number difference.

[0221] In some embodiments, the power consumption adjustment scheme corresponding to the channel quantity difference includes starting the current source. The power consumption control module 1203 is used to: determine the channel quantity difference between the sampling channel quantity of the chip to be adjusted and the channel quantity comparison value; determine the current source target startup duration that matches the channel quantity difference according to the preset corresponding relationship between the channel quantity difference and the current source startup duration; and control the startup operation of the current source in the chip to be adjusted based on the current source target startup duration.

[0222] In some embodiments, the chip configuration information includes the communication position of each chip on the daisy chain. The chip determination module 1202 to be adjusted is used to: determine the normal transmission time required for each chip to send valid communication data based on the communication position of each chip in the daisy chain; determine the chip with the longest normal transmission time as the second reference chip, and determine other chips except the second reference chip as the chips to be adjusted; determine that the power consumption difference type of each chip to be adjusted includes the communication position difference.

[0223] In some embodiments, the power consumption adjustment scheme corresponding to the communication position difference includes increasing the communication duration. The power consumption control module 1203 is used to: for each chip to be adjusted, calculate the duration difference between the reference normal transmission duration of the second reference chip and the normal transmission duration of the chip to be adjusted; determine the duration difference as the communication compensation duration of the chip to be adjusted; when the normal communication of each chip to be adjusted ends, control each chip to be adjusted to send invalid communication data based on the communication compensation duration of each chip to be adjusted.

[0224] Each module in the above chip power consumption control device can be implemented in whole or in part by software, hardware and their combination. Each module can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0225] In some embodiments, an electronic device is provided. The computer device may be a main control module, and its internal structure diagram may be as shown in FIG. Fig.13 As shown. The electronic device includes a processor, a memory and a network interface connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the electronic device is used to store chip configuration information, the type of power consumption difference of the chip to be adjusted, the power consumption adjustment scheme and other data. The network interface of the electronic device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a chip power consumption control method is implemented.

[0226] Those skilled in the art will understand that Fig.13 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0227] In some embodiments, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, specific implementation steps of the above-mentioned chip power consumption control method embodiment are implemented.

[0228] In some embodiments, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the specific implementation steps of the above-mentioned chip power consumption control method embodiment are implemented.

[0229] In some embodiments, a computer program product is provided, including a computer program, which, when executed by a processor, implements the specific implementation steps of the above-mentioned chip power consumption control method embodiment.

[0230] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. In addition, the acquisition, storage, processing, and transmission of data are in compliance with relevant laws and regulations.

[0231] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0232] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0233] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A chip power consumption control method, characterized in that: The method comprises: Obtain chip configuration information of each chip on the daisy chain; the chip configuration information includes at least one of interface configuration information of a universal input / output interface in each of the chips, the number of sampling channels, or a communication position on the daisy chain; for each of the chips, the number of cell sampling channels of the chip is consistent with the number of universal input / output interfaces; Based on the chip configuration information, at least one chip to be adjusted having a power consumption difference and a power consumption difference type of the chip to be adjusted are determined from the chips; when the chip configuration information includes the interface configuration information, the chip to be adjusted includes a chip configured with a pull-down resistor, and when the chip configuration information includes the number of sampling channels or the communication position, the chip to be adjusted includes a chip to be adjusted determined based on a reference chip in each of the chips; the power consumption difference type is a type parameter for classifying the difference reasons that lead to the difference in chip power consumption, including at least one of interface resource difference, channel number difference or communication position difference; According to the power consumption adjustment scheme corresponding to the power consumption difference type, the power consumption of the chip to be adjusted is controlled; the power consumption adjustment scheme corresponding to the interface resource difference includes regulating the high-level signal output duration of the chip to be adjusted to offset the power consumption difference caused by the interface resource difference; the power consumption adjustment scheme corresponding to the channel number difference includes adjusting the current source startup duration of the chip to be adjusted to offset the power consumption difference caused by the number of sampling channels; the power consumption adjustment scheme corresponding to the communication position difference includes adjusting the communication compensation duration of the chip to be adjusted to offset the power consumption difference caused by the communication position difference.

2. The method according to claim 1, characterized in that: The step of determining, based on the chip configuration information, at least one chip to be adjusted having power consumption differences from among the chips, and the power consumption difference types of the chips to be adjusted includes: Based on the interface configuration information of the universal input / output interface in each of the chips, the pull-down resistor configuration of each of the universal input / output interfaces is determined; the pull-down resistor is configured according to the difference in the number of interfaces of the universal input / output interface in each of the chips; Determine the chip to which the universal input / output interface provided with the pull-down resistor belongs as the chip to be adjusted; Determining that the power consumption difference type of the chip to be adjusted includes interface resource difference.

3. The method according to claim 2, characterized in that The controlling the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the power consumption difference type includes: Determining the number of universal input and output interfaces of each of the chips to be adjusted according to the interface configuration information of each of the chips; Based on the number of the general input and output interfaces and the preset corresponding relationship between the number of interfaces and the high-level on-time, determining the high-level on-time of each chip to be adjusted; According to the high level start-up time of each chip to be adjusted, the universal input and output interface of each chip to be adjusted is controlled to output a high level signal.

4. The method according to any one of claims 1 to 3, characterized in that: The step of determining, based on the chip configuration information, at least one chip to be adjusted having power consumption differences from among the chips, and the power consumption difference types of the chips to be adjusted includes: Based on the number of sampling channels of each of the chips, determining a first reference chip having the largest number of sampling channels from among the chips; Determine a channel quantity comparison value that matches the reference sampling channel quantity according to the reference sampling channel quantity of the first reference chip and a preset correspondence between the sampling channel quantity and the quantity comparison value; A chip whose number of sampling channels is smaller than the channel number comparison value is determined as a chip to be adjusted, and it is determined that the power consumption difference type of the chip to be adjusted includes a channel number difference.

5. The method according to claim 4, characterized in that The controlling the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the power consumption difference type includes: Determine a channel quantity difference between the sampling channel quantity of the chip to be adjusted and the channel quantity comparison value; Determine a target startup duration of the current source that matches the difference in the number of channels according to a preset corresponding relationship between the difference in the number of channels and the startup duration of the current source; The current source in the chip to be adjusted is controlled to start running based on the current source target startup time.

6. The method according to any one of claims 1 to 3, characterized in that: The step of determining, based on the chip configuration information, at least one chip to be adjusted having power consumption differences from among the chips, and the power consumption difference types of the chips to be adjusted includes: Based on the communication position of each chip in the daisy chain, determining a normal sending time required for each chip to send valid communication data; Determine the chip with the longest normal transmission time as the second reference chip, and determine the other chips except the second reference chip as the chips to be adjusted; Determining the power consumption difference type of each chip to be adjusted includes communication position difference.

7. The method according to claim 6, characterized in that The controlling the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the power consumption difference type includes: For each chip to be adjusted, calculating the duration difference between the reference normal transmission duration of the second reference chip and the normal transmission duration of the chip to be adjusted; Determine the duration difference as the communication compensation duration of the chip to be adjusted; When the normal communication of each chip to be adjusted is completed, each chip to be adjusted is controlled to send invalid communication data based on the communication compensation time length of each chip to be adjusted.

8. A chip power consumption control device, characterized in that: The device comprises: A configuration information acquisition module, used to acquire chip configuration information of each chip on the daisy chain; the chip configuration information includes at least one of interface configuration information of a universal input / output interface in each chip, the number of sampling channels, or a communication position on the daisy chain; for each chip, the number of cell sampling channels of the chip is consistent with the number of universal input / output interfaces; A chip to be adjusted determining module, used to determine at least one chip to be adjusted having a power consumption difference from each of the chips, and a power consumption difference type of the chip to be adjusted based on the chip configuration information; when the chip configuration information includes the interface configuration information, the chip to be adjusted includes a chip configured with a pull-down resistor, and when the chip configuration information includes the number of sampling channels or the communication position, the chip to be adjusted includes a chip to be adjusted determined based on a reference chip in each of the chips; the power consumption difference type is a type parameter for classifying the difference causes that lead to the difference in chip power consumption, including at least one of interface resource difference, channel number difference or communication position difference; A power consumption control module, used to control the power consumption of the chip to be adjusted according to the power consumption adjustment scheme corresponding to the power consumption difference type; the power consumption adjustment scheme corresponding to the interface resource difference includes regulating the high-level signal output duration of the chip to be adjusted to offset the power consumption difference caused by the interface resource difference; the power consumption adjustment scheme corresponding to the channel number difference includes adjusting the current source startup duration of the chip to be adjusted to offset the power consumption difference caused by the number of sampling channels; the power consumption adjustment scheme corresponding to the communication position difference includes adjusting the communication compensation duration of the chip to be adjusted to offset the power consumption difference caused by the communication position difference.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

12. A communication system, characterized in that: The communication system includes a daisy chain, and each chip and a main control module are configured on the daisy chain; For each of the chips, the number of sampling channels of the chip is consistent with the number of general input and output interfaces; The main control module is used to implement the steps of any one of the methods of claims 1 to 7.

13. The communication system according to claim 12, characterized in that: The chip includes a pull-down resistor configuration chip; the pull-down resistor configuration chip is determined according to the difference in the number of interfaces of the universal input and output interfaces of each of the chips; The universal input and output interfaces of the pull-down resistor configuration chip are all configured with pull-down resistors.

Images