Antifuse structure, antifuse array, operation method thereof, and memory

Abstract

Embodiments of the present disclosure provide an anti-fuse structure, an anti-fuse array, an operating method thereof, and a memory, wherein the anti-fuse structure includes: an active area, and a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure located on the surface of the active area; wherein the shape of the second gate structure is an arc with an opening toward the first gate structure, and the shape of the third gate structure is an arc with an opening toward the fourth gate structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and is related to but not limited to an antifuse structure, an antifuse array, an operation method thereof, and a memory. Background Art

[0002] Dynamic random access memory (DRAM) chips typically have redundant memory cells that can replace defective cells in the DRAM chip to repair it. Repairing a DRAM chip requires the use of one-time programming devices, such as antifuses.

[0003] An antifuse cell typically consists of an antifuse device, a select transistor, and a bit line. During programming, a high voltage is applied to the programming gate of the antifuse device, a low voltage is applied to the bit line, and the select transistor is turned on. The high voltage difference between the programming gate and the bit line causes the gate oxide layer of the programming gate to break down, completing the programming operation. With the rapid development of integrated circuit technology and the continuous reduction in chip size, the area of ​​the antifuse cell must also be reduced to save valuable space in the memory array. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an antifuse structure, an antifuse array, an operating method thereof, and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides an antifuse structure, comprising:

[0006] A substrate comprising an active region extending along a first direction and a first doping region, a second doping region, and a third doping region formed in the active region and arranged in sequence;

[0007] a first gate structure located on a surface of the active region on a side of the first doping region away from the second doping region;

[0008] a second gate structure located on a surface of the active region between the first doping region and the second doping region;

[0009] a third gate structure located on a surface of the active region between the second doping region and the third doping region;

[0010] a fourth gate structure, located on a surface of the active region on a side of the third doping region away from the second doping region;

[0011] The second gate structure is in the shape of an arc with an opening toward the first gate structure, and the third gate structure is in the shape of an arc with an opening toward the fourth gate structure.

[0012] The first direction is any direction within the plane where the substrate is located.

[0013] In some embodiments, the antifuse structure is an axisymmetric structure, a first symmetry axis of the antifuse structure extends along the first direction, and a second symmetry axis of the antifuse structure extends along the second direction;

[0014] The first direction and the second direction are located in the same plane and are perpendicular to each other.

[0015] In some embodiments, the first gate structure includes a first gate dielectric layer located on the active region and a first gate conductive layer located on the first gate dielectric layer;

[0016] The second gate structure includes a second gate dielectric layer located on the active area and a second gate conductive layer located on the second gate dielectric layer; the second gate dielectric layer and the second gate conductive layer are both arc-shaped with an opening facing the first gate structure;

[0017] The third gate structure includes a third gate dielectric layer located on the active area and a third gate conductive layer located on the third gate dielectric layer; the third gate dielectric layer and the third gate conductive layer are both arc-shaped with an opening facing the fourth gate structure;

[0018] The fourth gate structure includes a fourth gate dielectric layer located on the active region and a fourth gate conductive layer located on the fourth gate dielectric layer.

[0019] In some embodiments, the antifuse structure further comprises:

[0020] a plurality of first connection structures and first conductive lines; the first connection structures are connected between the second doped regions and the first conductive lines;

[0021] a second conductive line electrically connected to the second gate structure;

[0022] a third conductive line electrically connected to the first gate structure;

[0023] a fourth conductive line electrically connected to the third gate structure;

[0024] A fifth conductive line is electrically connected to the fourth gate structure.

[0025] In a second aspect, an embodiment of the present disclosure provides an antifuse array, comprising a plurality of antifuse structures as described in the first aspect; wherein,

[0026] A plurality of the antifuse structures are arranged in an array along the first direction and the second direction;

[0027] Every two adjacent anti-fuse structures arranged along the first direction share the first gate structure or the fourth gate structure;

[0028] The second gate structures of the anti-fuse structures in a row arranged along the second direction are electrically connected, and the third gate structures of the anti-fuse structures in a row arranged along the second direction are electrically connected.

[0029] In some embodiments, the third conductive line extends along the second direction, and a row of the antifuse structures arranged along the second direction is connected to the same third conductive line;

[0030] The fifth conductive line extends along the second direction, and a row of the antifuse structures arranged along the second direction is connected to the same fifth conductive line.

[0031] In some embodiments, the antifuse array further includes: a sixth conductive line located above the first conductive line and connected to the first conductive line;

[0032] The sixth conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same sixth conductive line.

[0033] In a third aspect, an embodiment of the present disclosure provides an operating method for an antifuse structure, which is applied to the antifuse structure according to the first aspect, wherein the first gate structure and the first doped region constitute a first programming device, the fourth gate structure and the third doped region constitute a second programming device; the second gate structure, the first doped region, and the second doped region constitute a first switching device, and the third gate structure, the second doped region, and the third doped region constitute a second switching device; the method includes:

[0034] During a programming operation, a first voltage is applied to the first conductive line, a second voltage is applied to the second conductive line, and a third voltage is applied to the third conductive line to break down the first programming device; or the first voltage is applied to the first conductive line, a fourth voltage is applied to the fourth conductive line, and a fifth voltage is applied to the fifth conductive line to break down the second programming device;

[0035] During a read operation, a sixth voltage is applied to the third conductive line, the second voltage is applied to the second conductive line, and the current flows into the first conductive line to read data from the first programming device; or a seventh voltage is applied to the fifth conductive line, the fourth voltage is applied to the fourth conductive line, and the current flows into the first conductive line to read data from the second programming device;

[0036] Among them, the third voltage is greater than or equal to the breakdown voltage of the first programming device and less than the breakdown voltage of the first switching device, the fifth voltage is greater than or equal to the breakdown voltage of the second programming device and less than the breakdown voltage of the second switching device; the second voltage is greater than or equal to the turn-on voltage of the first switching device, and the fourth voltage is greater than or equal to the turn-on voltage of the second switching device; the sixth voltage and the seventh voltage are both greater than the first voltage, and the first voltage is zero voltage or ground voltage.

[0037] In a fourth aspect, embodiments of the present disclosure provide an antifuse array operating method, which is applied to the antifuse array described in the second aspect, wherein the antifuse array includes a plurality of antifuse structures, each antifuse structure including a first programming device and a second programming device; the first gate structure and the first doped region constitute the first programming device, and the fourth gate structure and the third doped region constitute the second programming device; the method includes:

[0038] During a programming operation, an eighth voltage is applied to the third conductive line or the fifth conductive line corresponding to a programming device to be programmed, a ninth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be programmed, and a first voltage is applied to the sixth conductive line corresponding to the programming device to be programmed, so as to breakdown the programming device to be programmed; at the same time, a tenth voltage is applied to the other sixth conductive lines in the antifuse array so as to prevent other programming devices except the programming device to be programmed from being broken down; the programming device to be programmed is any one of the plurality of first programming devices or the plurality of second programming devices;

[0039] During a read operation, the eleventh voltage is applied to the third conductive line or the fifth conductive line corresponding to the programming device to be read, the ninth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be read, and the first voltage is applied to the sixth conductive line corresponding to the programming device to be read, so that the current flowing into the sixth conductive line reads the data in the programming device to be read; at the same time, the first voltage is applied to the other sixth conductive line in the antifuse array, and the other second conductive line, the third conductive line, the fourth conductive line, and the fifth conductive line in the antifuse array are left floating or applied with the first voltage;

[0040] Among them, the eighth voltage is greater than or equal to the breakdown voltage of the programming device to be programmed, and is less than the breakdown voltage of the switching device corresponding to the programming device to be programmed; the ninth voltage is greater than or equal to the turn-on voltage of the switching device corresponding to the programming device to be programmed; the tenth voltage and the eleventh voltage are greater than the first voltage and less than the eighth voltage; the difference between the eighth voltage and the tenth voltage is less than the breakdown voltage of the programming device to be programmed; the first voltage is zero voltage or ground voltage.

[0041] In a fifth aspect, an embodiment of the present disclosure provides a memory comprising an antifuse array as described in any one of the second aspects.

[0042] Embodiments of the present disclosure provide an antifuse structure, an antifuse array, an operating method thereof, and a memory device. In the antifuse structure, a second gate structure, a first doped region, and a second doped region form a first switching device, and a third gate structure, a second doped region, and a third doped region form a second switching device. The second gate structure is shaped like an arc with an opening toward the first gate structure, and the third gate structure is shaped like an arc with an opening toward the fourth gate structure. Because the length of the arc is necessarily greater than the length of a straight line segment passing through two points of the arc, the widths of the active regions corresponding to the first and second switching devices can be reduced, thereby reducing the area of ​​the active region and the area of ​​the antifuse structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0044] Figure 1 Schematic diagram of the structure of an antifuse array;

[0045] Figure 2 A schematic diagram of the layout structure of an antifuse structure;

[0046] Figure 3 A schematic diagram of the local structure of an antifuse array;

[0047] Figure 4 A schematic diagram of the layout structure of an antifuse structure provided in an embodiment of the present disclosure;

[0048] Figure 5 A schematic diagram of the layout structure of another antifuse structure provided in an embodiment of the present disclosure;

[0049] Figure 6 A schematic structural diagram of an antifuse array provided in an embodiment of the present disclosure;

[0050] Figure 7 A schematic structural diagram of another antifuse array provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0052] In the following description, numerous details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0053] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0054] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the present disclosure necessarily has the first element, component, region, layer, or part.

[0055] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] Figure 1 FIG. 1 is a structural diagram of an antifuse array, such as Figure 1 As shown, the antifuse array 100 includes a plurality of antifuse structures 100 a arranged at intervals. The plurality of antifuse structures 100 a are arranged at intervals along a second direction (ie, the X-axis direction shown in the figure).

[0057] Figure 2 is a schematic diagram of a layout structure of an antifuse structure 100a, such as Figure 2 As shown, the antifuse structure 100a includes a first antifuse unit 11 and a second antifuse unit 12. The first antifuse unit 11 includes a first gate 101, a first source / drain region 102, a second gate 103, and a second source / drain region 104. The first gate 101 and the active region 13 located below the first gate 101 constitute a first antifuse device, and the first source / drain region 102, the second gate 103, and the second source / drain region 104 constitute a first select transistor. The second antifuse unit 12 includes a third gate 105, a second source / drain region 104, a third source / drain region 106, and a fourth gate 107. The fourth gate 107 and the active region 13 located below the fourth gate 107 constitute a second antifuse device, and the second source / drain region 104, the third gate 105, and the third source / drain region 106 constitute a second select transistor. The first and second select transistors share the second source / drain region 104, and a bit line connection structure 108 electrically connects the second source / drain region 104 to a bit line (BL) 109. For the anti-fuse structure 100a, when writing, a high voltage (for example, about 5 to 5.5 volts) is applied to the first gate 101 of the first anti-fuse device, 0V is set at the corresponding BL terminal, and the first selection transistor is turned on, so that the thin gate oxide of the first anti-fuse device is broken down under the high voltage and the resistance is significantly reduced, thereby achieving the purpose of writing; or, when writing, a high voltage (for example, about 5 to 5.5 volts) is applied to the fourth gate 107 of the second anti-fuse device, 0V is set at the corresponding BL terminal, and the second selection transistor is turned on, so that the thin gate oxide of the second anti-fuse device is broken down under the high voltage and the resistance is significantly reduced, thereby achieving the purpose of writing.

[0058] Please continue to refer to Figure 1and Figure 2 The first gate 101, the second gate 103, the third gate 105 and the fourth gate 107 in the anti-fuse structure 100a are arranged in sequence along the first direction (i.e., the Y-axis direction shown in the figure), so that the length of the anti-fuse structure 100a is longer, thereby making the area of ​​the anti-fuse array 100 including multiple anti-fuse structures 100a larger.

[0059] Also, please continue to refer to Figure 2 When the width of the first selection transistor or the second selection transistor (i.e., the dimension along the X-axis direction) is small, the voltage division of the channel of the first selection transistor or the second selection transistor increases, so that the voltage difference across the corresponding first anti-fuse device or the second anti-fuse device becomes smaller, weakening the energy used to break down the gate oxide in the first anti-fuse device or the second anti-fuse device, resulting in the first anti-fuse device or the second anti-fuse device being difficult to write. Therefore, the first selection transistor or the second selection transistor needs to have a larger width, which limits the reduction of the area of ​​the anti-fuse structure 100a.

[0060] Figure 3 is a partial structural diagram of the antifuse array 100, refer to Figure 3 Typically, an anti-fuse doping region 301 is provided in the substrate below the first and second anti-fuse devices. Due to the extremely high doping concentration of the anti-fuse doping region 301, the doping ions in the anti-fuse doping region 301 may diffuse to the vicinity of the channel doping region 302 of the first and second selection transistors during the high-temperature process, thereby reducing the turn-on voltage of the first and second selection transistors and increasing the risk of leakage. Therefore, the distance A between the first gate 101 and the second gate 103 and the distance C between the third gate 105 and the fourth gate 107 must be maintained at a large distance, for example, significantly larger than the distance B between the second gate 103 and the third gate 105. This makes it difficult to further reduce the length of the anti-fuse structure 100a.

[0061] Based on this, embodiments of the present disclosure provide an antifuse structure, an antifuse array, an operating method thereof, and a memory. In the antifuse structure, a second gate structure, a first doped region, and a second doped region form a first switching device, and a third gate structure, a second doped region, and a third doped region form a second switching device. The second gate structure is shaped like an arc with an opening toward the first gate structure, and the third gate structure is shaped like an arc with an opening toward the fourth gate structure. Because the length of the arc is necessarily greater than the length of a straight line segment passing through two points of the arc, the widths of the active regions corresponding to the first and second switching devices can be reduced, thereby reducing the area of ​​the active region and the area of ​​the antifuse structure.

[0062] The antifuse structure and the antifuse array in the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0063] Before introducing the embodiments of the present disclosure, let's first define two directions that may be used in describing the antifuse structure in the following embodiments. In the plane direction of the active region, two intersecting (e.g., perpendicular) directions are defined as a first direction and a second direction. For example, the direction in which the active region extends can be defined as the first direction. Here, the first direction can be, for example, the Y-axis direction, and the second direction can be, for example, the X-axis direction.

[0064] An embodiment of the present disclosure provides an antifuse structure, Figure 4 and Figure 5 A schematic diagram of the layout structure of the antifuse structure provided in the embodiment of the present disclosure is shown in FIG. Figure 4 and Figure 5 As shown, the antifuse structure 200 includes:

[0065] The substrate includes an active region 20 extending along the Y-axis direction and a first doping region 201, a second doping region 202 and a third doping region 203 formed in the active region 20 and arranged in sequence;

[0066] A first gate structure 204 is located on the surface of the active region 20 on a side of the first doping region 201 away from the second doping region 202 ;

[0067] The second gate structure 205 is located on the surface of the active region 20 between the first doping region 201 and the second doping region 202 ;

[0068] A third gate structure 206 is located on the surface of the active region 20 between the second doping region 202 and the third doping region 203 ;

[0069] a fourth gate structure 207 located on a surface of the active region 20 on a side of the third doping region 203 away from the second doping region 202 ;

[0070] The second gate structure 205 is in an arc shape with its opening facing the first gate structure 204 , and the third gate structure 206 is in an arc shape with its opening facing the fourth gate structure 207 .

[0071] In the embodiment of the present disclosure, the first gate structure 204 and the active area 20 located below the first gate structure 204 constitute a first programming device, the second gate structure 205 and the first doped area 201 and the second doped area 202 constitute a first switching device; the third gate structure 206 and the second doped area 202 and the third doped area 203 constitute a second switching device; the fourth gate structure 207 and the active area 20 located below the fourth gate structure 207 constitute a second programming device.

[0072] Among them, the second doped region 202 can serve as one of the source region or drain region of the first switching device and the second switching device, the first doped region 201 can serve as the other of the source region or drain region of the first switching device, and the third doped region 203 can serve as the other of the source region or drain region of the second switching device.

[0073] It should be noted that the reference Figure 4 and Figure 5 In the embodiment of the present disclosure, the first gate structure 204 and the fourth gate structure 207 are circular in shape. In some other embodiments, the first gate structure 204 and the fourth gate structure 207 may also be any other feasible shape, such as a square or a rectangle. The shapes of the first gate structure 204 and the fourth gate structure 207 may be the same or different, and the present disclosure does not limit this.

[0074] It is also necessary to note that please continue to refer to Figure 4 and Figure 5 In the embodiment of the present disclosure, the distance from the center point of the first gate structure 204 to any point of the second gate structure 205 is equal; the distance from the center point of the fourth gate structure 207 to any point of the third gate structure 206 is equal.

[0075] It should also be noted that the curvatures of the second gate structure 205 and the third gate structure 206 are equal. In other embodiments, the curvatures of the second gate structure 205 and the third gate structure 206 may also be unequal, which is not limited in this disclosure.

[0076] In the embodiment of the present disclosure, the shape of the second gate structure 205 is set to be an arc with an opening toward the first gate structure 204, and the shape of the third gate structure 206 is set to be an arc with an opening toward the fourth gate structure 207, because the length of the arc must be greater than the length of the straight line segment passing through the two points of the arc, so that the widths of the first switching device and the second switching device are respectively greater than Figure 2 In the case where the widths of the first switching device and the second switching device in the anti-fuse structure 100a are the same, the width of the active region in the anti-fuse structure provided by the embodiment of the present disclosure can be reduced, thereby reducing the area of ​​the active region, thereby effectively reducing the area of ​​the anti-fuse structure. Figure 3 In comparison, there is no need to set the anti-fuse doping region 301, thereby reducing the number of masks and lowering the chip manufacturing cost.

[0077] In some embodiments, reference Figure 4 and Figure 5 The antifuse structure 200 is an axisymmetric structure. A first axis of symmetry of the antifuse structure 200 extends along the Y-axis direction, and a second axis of symmetry of the antifuse structure 200 extends along the X-axis direction.

[0078] The antifuse structure 200 has two symmetry axes extending along the X-axis and the Y-axis. On the one hand, this makes the pattern of the layout of the antifuse structure 200 more uniform, which is conducive to further reducing the difficulty of actual process production; on the other hand, it makes the performance of the two antifuse units in the antifuse structure 200 closer, and thus when programming and reading the two antifuse units, consistent voltages can be applied to the corresponding wires, simplifying the operation method.

[0079] In some embodiments, reference Figure 4 and Figure 5 The first gate structure 204 includes a first gate dielectric layer (not shown in the figure) located on the active region 20 and a first gate conductive layer (not shown in the figure) located on the first gate dielectric layer;

[0080] The second gate structure 205 includes a second gate dielectric layer (not shown in the figure) located on the active region 20 and a second gate conductive layer (not shown in the figure) located on the second gate dielectric layer; both the second gate dielectric layer and the second gate conductive layer are arc-shaped with an opening facing the first gate structure 204;

[0081] The third gate structure 206 includes a third gate dielectric layer (not shown in the figure) located on the active region 20 and a third gate conductive layer (not shown in the figure) located on the third gate dielectric layer; the third gate dielectric layer and the third gate conductive layer are both arc-shaped with an opening facing the fourth gate structure 207;

[0082] The fourth gate structure 207 includes a fourth gate dielectric layer (not shown in the figures) located on the active region 20 and a fourth gate conductive layer (not shown in the figures) located on the fourth gate dielectric layer.

[0083] In some embodiments, the second gate dielectric layer and the third gate dielectric layer can have equal thicknesses in the thickness direction of the active region 20, thereby allowing them to be formed in a single process, simplifying the process and making the performance of the first switching device and the second switching device more similar. The first gate dielectric layer and the fourth gate dielectric layer can also have equal thicknesses in the thickness direction of the active region 20, thereby allowing them to be formed in a single process, simplifying the process and making the performance of the first programming device and the second programming device more similar.

[0084] In some embodiments, the materials of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer can be silicon oxide or other suitable materials; the materials of the first gate conductive layer, the second gate conductive layer, the third gate conductive layer and the fourth gate conductive layer can be any material with good conductivity, such as any one or more combinations of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), copper (Cu), and polycrystalline silicon.

[0085] In some embodiments, reference Figure 4 and Figure 5 , the antifuse structure 200 may further include:

[0086] A plurality of first connection structures 221 and first conductive lines 231 ; the first connection structures 221 are connected between the second doped regions 202 and the first conductive lines 231 .

[0087] Here, the first conductive line 231 is electrically connected to the second doped region 202 via a plurality of first connection structures 221. The first connection structures 221 may be contact plugs formed within the interlayer dielectric layer. It should be noted that, in the disclosed embodiment, providing a plurality of first connection structures 221 can reduce the contact resistance between the second doped region 202 and the first conductive line 231, thereby improving the electrical performance of the antifuse structure.

[0088] In some embodiments, reference Figure 5 , the antifuse structure 200 may further include:

[0089] A second conductive line 232 electrically connected to the second gate structure 205;

[0090] A third conductive line 233 electrically connected to the first gate structure 204;

[0091] a fourth conductive line 234 electrically connected to the third gate structure 206 ;

[0092] The fifth conductive line 235 is electrically connected to the fourth gate structure 207 .

[0093] It should be noted that the second conductive line 232 and the fourth conductive line 234 may be word lines XG, and the third conductive line 233 and the fifth conductive line 235 may be programming conductive lines FG.

[0094] Here, the second and fourth conductive lines 232 and 234 lead out the second and third gate conductive layers, respectively, so that a voltage can be applied to the second and fourth conductive lines 232 and 234 to turn on the corresponding first and second switching devices. The third conductive line 233 leads out the first gate conductive layer so that a programming voltage or a reading voltage can be applied to the third conductive line 233 when programming or reading the first programming device. The fifth conductive line 235 leads out the fourth gate conductive layer so that a programming voltage or a reading voltage can be applied to the fifth conductive line 235 when programming or reading the second programming device.

[0095] It should be noted that the second conductive line 232 and the fourth conductive line 234 and the corresponding gate conductive layer, and the third conductive line 233 and the fifth conductive line 235 and the corresponding gate conductive layer can be electrically connected through contact plugs.

[0096] It should also be noted that the first conductive line 231, the second conductive line 232, the third conductive line 233, the fourth conductive line 234 and the fifth conductive line 235 are located in the same layer, so that in the actual process, they can be formed by patterning the same conductive material layer, which simplifies the process and reduces the number of layers of the interconnection structure.

[0097] In some embodiments, the material of the first conductive line 231, the second conductive line 232, the third conductive line 233, the fourth conductive line 234 and the fifth conductive line 235 can be any material with good conductivity, for example, any one or more combinations of titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium, and copper.

[0098] In another embodiment of the present disclosure, an antifuse array is provided. Figure 6 and Figure 7 , which shows a schematic structural diagram of the antifuse array provided by an embodiment of the present disclosure. Figure 6 and Figure 7 As shown, the antifuse array 300 includes a plurality of antifuse structures 200 as in the aforementioned embodiment; wherein the plurality of antifuse structures 200 are arranged in an array along the Y-axis direction and the X-axis direction;

[0099] Every two adjacent anti-fuse structures 200 arranged along the Y-axis direction share the first gate structure 204 or the fourth gate structure 207 ;

[0100] The second gate structures 205 of the anti-fuse structures 200 in a row arranged along the X-axis direction are electrically connected, and the third gate structures 206 of the anti-fuse structures 200 in a row arranged along the X-axis direction are electrically connected.

[0101] In the present disclosure, continue to refer to Figure 6 and Figure 7 The fourth gate structure 207 of the anti-fuse structures 200 in the first row arranged along the Y-axis direction is shared with the fourth gate structure 207 of the anti-fuse structures 200 in the adjacent second row. The first gate structure 204 of the anti-fuse structures 200 in the second row arranged along the Y-axis direction is shared with the first gate structure 204 of the anti-fuse structures 200 in the adjacent third row. And so on. Every two adjacent anti-fuse structures 200 arranged along the Y-axis direction alternately share the first gate structure 204 and the fourth gate structure 207. In this way, every two adjacent programming devices arranged along the Y-axis direction can share the same programming wire FG, and thus, the programming voltage or the reading voltage can be applied to each of the two adjacent programming devices through the same programming wire FG.

[0102] In addition, in the Y-axis direction, since every two adjacent anti-fuse structures 200 share the first gate structure 204 or the fourth gate structure 207 , the area of ​​the anti-fuse array 300 can be further reduced.

[0103] In the embodiments of the present disclosure, reference Figure 6 and Figure 7 The second gate structures 205 of the multiple anti-fuse structures 200 arranged along the X-axis are electrically connected, enabling the multiple first switching devices in the same row to be turned on or off through a single control terminal. The third gate structures 206 of the multiple anti-fuse structures 200 arranged along the X-axis are electrically connected, enabling the multiple second switching devices in the same row to be turned on or off through a single control terminal.

[0104] In some embodiments, reference Figure 7 , the third conductive line 233 extends along the X-axis direction, and a row of antifuse structures 200 arranged along the X-axis direction is connected to the same third conductive line 233;

[0105] The fifth conductive line 235 extends along the X-axis direction, and a row of anti-fuse structures 200 arranged along the X-axis direction is connected to the same fifth conductive line 235 .

[0106] In the embodiments of the present disclosure, reference Figure 7 The gate conductive layers of the first programming devices of the multiple anti-fuse structures 200 arranged along the X-axis are all connected to the third conductive line 233, so that a programming voltage or a read voltage can be applied to the first programming devices in the same row through the third conductive line 233. Similarly, the gate conductive layers of the second programming devices of the multiple anti-fuse structures 200 arranged along the X-axis are all connected to the fifth conductive line 235, so that a programming voltage or a read voltage can be applied to the second programming devices in the same row through the fifth conductive line 235.

[0107] In some embodiments, reference Figure 7 , the antifuse array 300 further includes a sixth conductive line 236 located above the first conductive line 231 and connected to the first conductive line 231 ;

[0108] The sixth conductive line 236 extends along the Y-axis direction, and a row of antifuse structures 200 arranged along the Y-axis direction is connected to the same sixth conductive line 236 .

[0109] In the embodiments of the present disclosure, reference Figure 7 The sixth conductive line 236 connects multiple antifuse structures 200 in the same column and can serve as a bit line BL of the antifuse array 300 .

[0110] In some embodiments, reference Figure 7The antifuse array 300 further includes a plurality of first contact structures 241 ; the first contact structures 241 are connected between the first conductive line 231 and the sixth conductive line 236 .

[0111] In some embodiments, see Figure 7 The second conductive line 232 connects the second gate structure 205 in the first anti-fuse structure 200 in a row of anti-fuse structures 200 arranged along the X-axis direction, and the second gate structures 205 in a row of anti-fuse structures 200 arranged along the X-axis direction are all connected, so by applying voltage to the second conductive line 232, multiple first switching devices in the same row can be controlled.

[0112] Similarly, the fourth conductive line 234 is connected to the third gate structure 206 in the first anti-fuse structure 200 in a row of anti-fuse structures 200 arranged along the X-axis direction, and the third gate structures 206 of the anti-fuse structures 200 in a row arranged along the X-axis direction are all connected, so by applying voltage to the fourth conductive line 234, multiple second switching devices in the same row can be controlled.

[0113] It should be noted that the second conductive line 232 and the fourth conductive line 234 can also connect the last anti-fuse structure 200 in a row of anti-fuse structures 200 arranged along the X-axis direction. In the anti-fuse array 300, the positions of the second conductive line 232 and the fourth conductive line 234 are not specifically limited.

[0114] It should also be noted that all conductive lines in the antifuse array 300 may be electrically connected to corresponding components via contact plugs, wherein the contact plugs may be located in the interlayer dielectric layer.

[0115] It should also be noted that Figure 6 and Figure 7 Only six antifuse structures 200 are shown in the antifuse array 300 in FIG. 1 . In actual implementation, the antifuse array 300 may include multiple rows and multiple columns formed by multiple antifuse structures 200 .

[0116] Another embodiment of the present disclosure further provides an operating method of an antifuse structure, which is applicable to the aforementioned embodiment. Figure 4 and Figure 5 The antifuse structure 200 is shown. Figure 4 and Figure 5 , wherein the first gate structure 204 and the first doped region 201 constitute a first programming device, the fourth gate structure 207 and the third doped region 203 constitute a second programming device; the second gate structure 205 and the first doped region 201 and the second doped region 202 constitute a first switching device, and the third gate structure 206 and the second doped region 202 and the third doped region 203 constitute a second switching device; the operating method of the antifuse structure includes:

[0117] During a programming operation, a first voltage is applied to the first conductive line 231, a second voltage is applied to the second conductive line 232, and a third voltage is applied to the third conductive line 233 to break down the first programming device; or a first voltage is applied to the first conductive line 231, a fourth voltage is applied to the fourth conductive line 234, and a fifth voltage is applied to the fifth conductive line 235 to break down the second programming device;

[0118] It should be noted that when programming the first programming device, the first voltage is zero voltage or ground voltage, the second voltage is greater than or equal to the turn-on voltage of the first switching device, so that the first switching device can be turned on at the second voltage, and the third voltage is greater than or equal to the breakdown voltage of the first programming device, and less than the breakdown voltage of the first switching device, so that the first programming device can be broken down at the third voltage without breaking down the first switching device. Here, the third voltage can range from 5 to 5.5V, for example, it can be 5.1V, 5.3V or 5.4V, etc.

[0119] It should also be noted that when programming the second programming device, the fourth voltage is greater than or equal to the turn-on voltage of the second switching device, so that the second switching device can be turned on at the fourth voltage, and the fifth voltage is greater than or equal to the breakdown voltage of the second programming device and less than the breakdown voltage of the second switching device, so that the second programming device can be broken down at the fifth voltage without breaking down the second switching device. Here, the fifth voltage can range from 5 to 5.5V, for example, it can be 5.1V, 5.3V or 5.4V, etc.

[0120] During a read operation, a sixth voltage is applied to the third conductive line 233, a second voltage is applied to the second conductive line 232, and a current flows into the first conductive line 231 to read data from the first programming device; alternatively, a seventh voltage is applied to the fifth conductive line 235, a fourth voltage is applied to the fourth conductive line 234, and a current flows into the first conductive line 231 to read data from the second programming device;

[0121] It should be noted that when reading the first programming device, the sixth voltage is greater than the first voltage and is a positive voltage less than the breakdown voltage of the first programming device, for example, 1 V. When reading the second programming device, the seventh voltage is greater than the first voltage and is a positive voltage less than the breakdown voltage of the second programming device, for example, 1 V.

[0122] Another embodiment of the present disclosure further provides an operation method of an antifuse array, which is applied to the aforementioned embodiment. Figure 7 The antifuse array 300 is shown. Figure 7The antifuse array 300 includes a plurality of antifuse structures 200, each antifuse structure 200 including a first programming device and a second programming device; the first gate structure 204 and the first doped region 201 constitute the first programming device, and the fourth gate structure 207 and the third doped region 203 constitute the second programming device; and the operating method of the antifuse array includes:

[0123] During the programming operation, the eighth voltage is applied to the third conductive line 233 or the fifth conductive line 235 corresponding to the programming device to be programmed, the ninth voltage is applied to the second conductive line 232 or the fourth conductive line 234 corresponding to the programming device to be programmed, and the first voltage is applied to the sixth conductive line 236 corresponding to the programming device to be programmed, so as to break down the programming device to be programmed; at the same time, the tenth voltage is applied to the other sixth conductive lines 236 in the anti-fuse array so that other programming devices except the programming device to be programmed are not broken down.

[0124] It should be noted that the programming device to be programmed is any one of the multiple first programming devices or the multiple second programming devices.

[0125] It should also be noted that the first voltage is zero voltage or ground voltage, the eighth voltage is greater than or equal to the breakdown voltage of the programming device to be programmed, and less than the breakdown voltage of the switching device corresponding to the programming device to be programmed, so that the programming device to be programmed can be broken down at the eighth voltage and the switching device corresponding to it will not be broken down; the ninth voltage is greater than or equal to the turn-on voltage of the switching device corresponding to the programming device to be programmed, so that the corresponding switching device can be turned on at the ninth voltage. Here, the eighth voltage can range from 5 to 5.5V, for example, it can be 5.1V, 5.3V or 5.4V, etc.

[0126] It should also be noted that the tenth voltage is greater than the first voltage and less than the eighth voltage; the difference between the eighth voltage and the tenth voltage is less than the breakdown voltage of the programming device to be programmed, so that when the programming device to be programmed is broken down, other programming devices in the same row as the programming device to be programmed are not broken down.

[0127] During the reading operation, the eleventh voltage is applied to the third conductive line 233 or the fifth conductive line 235 corresponding to the programming device to be read, the ninth voltage is applied to the second conductive line 232 or the fourth conductive line 234 corresponding to the programming device to be read, and the first voltage is applied to the sixth conductive line 236 corresponding to the programming device to be read, and the current flowing into the sixth conductive line 236 is used to read the data in the programming device to be read; at the same time, the first voltage is applied to the other sixth conductive line 236 in the antifuse array, and the other second conductive line 232, the third conductive line 233, the fourth conductive line 234 and the fifth conductive line 235 in the antifuse array are suspended or applied with the first voltage.

[0128] It should be noted that the eleventh voltage is greater than the first voltage and less than the breakdown voltage of the programming device to be programmed. For example, the eleventh voltage may be 1V.

[0129] Yet another embodiment of the present disclosure provides a memory device, comprising the antifuse array 300 in any of the aforementioned embodiments, wherein the antifuse array 300 comprises the antifuse structure 200 in any of the aforementioned embodiments;

[0130] Among them, multiple anti-fuse structures are arranged in an array along the Y-axis direction and the X-axis direction; every two adjacent anti-fuse structures arranged along the Y-axis direction share a first gate structure or a fourth gate structure; the second gate structures of a row of anti-fuse structures arranged along the X-axis direction are electrically connected, and the third gate structures of a row of anti-fuse structures arranged along the X-axis direction are electrically connected.

[0131] In which, the anti-fuse structure includes a substrate, an active area extending along the Y-axis direction, and a first doping region, a second doping region and a third doping region formed in the active area and arranged in sequence; a first gate structure, located on the surface of the active area on the side of the first doping region away from the second doping region; a second gate structure, located on the surface of the active area between the first doping region and the second doping region; a third gate structure, located on the surface of the active area between the second doping region and the third doping region; a fourth gate structure, located on the surface of the active area on the side of the third doping region away from the second doping region; wherein the shape of the second gate structure is an arc with an opening toward the first gate structure, and the shape of the third gate structure is an arc with an opening toward the fourth gate structure.

[0132] In some embodiments, the memory may include but is not limited to random access memory (RAM), such as dynamic random access memory (DRAM).

[0133] In the disclosed embodiment, the memory includes the aforementioned antifuse array 300 . Since the aforementioned antifuse array 300 has a relatively small area, the integration of the memory can be improved, thereby effectively increasing the storage capacity of the memory and improving its performance.

[0134] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in non-targeted ways. The structural embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0135] The features disclosed in several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0136] The above are only some embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An antifuse structure, characterized in that: include: A substrate comprising an active region extending along a first direction and a first doping region, a second doping region, and a third doping region formed in the active region and arranged in sequence; a first gate structure located on a surface of the active region on a side of the first doping region away from the second doping region; a second gate structure located on a surface of the active region between the first doping region and the second doping region; a third gate structure located on a surface of the active region between the second doping region and the third doping region; a fourth gate structure, located on a surface of the active region on a side of the third doping region away from the second doping region; The second gate structure is in the shape of an arc with an opening toward the first gate structure, and the third gate structure is in the shape of an arc with an opening toward the fourth gate structure. The first direction is any direction within the plane where the substrate is located.

2. The antifuse structure according to claim 1, wherein: The antifuse structure is an axisymmetric structure, wherein a first symmetry axis of the antifuse structure extends along the first direction, and a second symmetry axis of the antifuse structure extends along the second direction; The first direction and the second direction are located in the same plane and are perpendicular to each other.

3. The antifuse structure according to claim 2, wherein: The first gate structure includes a first gate dielectric layer located on the active area and a first gate conductive layer located on the first gate dielectric layer; The second gate structure includes a second gate dielectric layer located on the active area and a second gate conductive layer located on the second gate dielectric layer; the second gate dielectric layer and the second gate conductive layer are both arc-shaped with an opening facing the first gate structure; The third gate structure includes a third gate dielectric layer located on the active area and a third gate conductive layer located on the third gate dielectric layer; the third gate dielectric layer and the third gate conductive layer are both arc-shaped with an opening facing the fourth gate structure; The fourth gate structure includes a fourth gate dielectric layer located on the active region and a fourth gate conductive layer located on the fourth gate dielectric layer.

4. The antifuse structure according to claim 2 or 3, wherein: The antifuse structure further includes: a plurality of first connection structures and first conductive lines; the first connection structures are connected between the second doped regions and the first conductive lines; a second conductive line electrically connected to the second gate structure; a third conductive line electrically connected to the first gate structure; a fourth conductive line electrically connected to the third gate structure; A fifth conductive line is electrically connected to the fourth gate structure.

5. An antifuse array, characterized in that: comprising a plurality of antifuse structures as claimed in claim 4; wherein: A plurality of the antifuse structures are arranged in an array along the first direction and the second direction; Every two adjacent anti-fuse structures arranged along the first direction share the first gate structure or the fourth gate structure; The second gate structures of the anti-fuse structures in a row arranged along the second direction are electrically connected, and the third gate structures of the anti-fuse structures in a row arranged along the second direction are electrically connected.

6. The antifuse array according to claim 5, wherein: The third conductive line extends along the second direction, and a row of the antifuse structures arranged along the second direction is connected to the same third conductive line; The fifth conductive line extends along the second direction, and a row of the antifuse structures arranged along the second direction is connected to the same fifth conductive line.

7. The antifuse array according to claim 5 or 6, wherein: Also includes: a sixth conductive line located above the first conductive line and connected to the first conductive line; The sixth conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same sixth conductive line.

8. A method for operating an antifuse structure, characterized in that: The antifuse structure according to claim 4, wherein the first gate structure and the first doped region constitute a first programming device, the fourth gate structure and the third doped region constitute a second programming device; the second gate structure, the first doped region, and the second doped region constitute a first switching device, and the third gate structure, the second doped region, and the third doped region constitute a second switching device; and the method comprises: During a programming operation, a first voltage is applied to the first conductive line, a second voltage is applied to the second conductive line, and a third voltage is applied to the third conductive line to break down the first programming device; or the first voltage is applied to the first conductive line, a fourth voltage is applied to the fourth conductive line, and a fifth voltage is applied to the fifth conductive line to break down the second programming device; During a read operation, a sixth voltage is applied to the third conductive line, the second voltage is applied to the second conductive line, and the current flows into the first conductive line to read data from the first programming device; or a seventh voltage is applied to the fifth conductive line, the fourth voltage is applied to the fourth conductive line, and the current flows into the first conductive line to read data from the second programming device; Among them, the third voltage is greater than or equal to the breakdown voltage of the first programming device and less than the breakdown voltage of the first switching device, the fifth voltage is greater than or equal to the breakdown voltage of the second programming device and less than the breakdown voltage of the second switching device; the second voltage is greater than or equal to the turn-on voltage of the first switching device, and the fourth voltage is greater than or equal to the turn-on voltage of the second switching device; the sixth voltage and the seventh voltage are both greater than the first voltage, and the first voltage is zero voltage or ground voltage.

9. A method for operating an antifuse array, characterized in that: The antifuse array according to claim 7, wherein the antifuse array comprises a plurality of antifuse structures, each antifuse structure comprises a first programming device and a second programming device; the first gate structure and the first doped region constitute the first programming device, and the fourth gate structure and the third doped region constitute the second programming device; and the method comprises: During a programming operation, an eighth voltage is applied to the third conductive line or the fifth conductive line corresponding to a programming device to be programmed, a ninth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be programmed, and a first voltage is applied to the sixth conductive line corresponding to the programming device to be programmed, so as to breakdown the programming device to be programmed; at the same time, a tenth voltage is applied to the other sixth conductive lines in the antifuse array so as to prevent other programming devices except the programming device to be programmed from being broken down; the programming device to be programmed is any one of the plurality of first programming devices or the plurality of second programming devices; During a read operation, the eleventh voltage is applied to the third conductive line or the fifth conductive line corresponding to the programming device to be read, the ninth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be read, and the first voltage is applied to the sixth conductive line corresponding to the programming device to be read, so that the current flowing into the sixth conductive line reads the data in the programming device to be read; at the same time, the first voltage is applied to the other sixth conductive line in the antifuse array, and the other second conductive line, the third conductive line, the fourth conductive line, and the fifth conductive line in the antifuse array are left floating or applied with the first voltage; Among them, the eighth voltage is greater than or equal to the breakdown voltage of the programming device to be programmed, and is less than the breakdown voltage of the switching device corresponding to the programming device to be programmed; the ninth voltage is greater than or equal to the turn-on voltage of the switching device corresponding to the programming device to be programmed; the tenth voltage and the eleventh voltage are greater than the first voltage and less than the eighth voltage; the difference between the eighth voltage and the tenth voltage is less than the breakdown voltage of the programming device to be programmed; the first voltage is zero voltage or ground voltage.

10. A memory, characterized in that: The invention comprises the antifuse array according to any one of claims 5 to 7.

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