A method, device, storage medium and vehicle for canceling sleep mode

Abstract

The present application provides a method, device, storage medium and vehicle for canceling sleep mode. The method includes determining the current sleep mode state of the multi-core heterogeneous system in response to an instruction to cancel the sleep mode; when the first domain is in the first sleep state, stopping the first sleep state of the first domain and waking up the multi-core heterogeneous system; when the second domain is in the second sleep state, after the second sleep state of the second domain ends, waking up the multi-core heterogeneous system; wherein, after the first sleep state of the first domain ends, the second domain enters the second sleep state, and the time required to complete the second sleep state of the second domain is less than the time required to complete the first sleep state of the first domain. By determining which stage of the sleep mode the multi-core heterogeneous system is currently in, and taking different processing measures according to the different stages it is currently in, the multi-core heterogeneous system can be awakened as soon as possible, thereby improving the user experience.

Description

Technical Field

[0001] The present application relates to the field of multi-core heterogeneous technology, and in particular to a method, device, storage medium and vehicle for canceling a sleep mode. Background Art

[0002] "Suspend to RAM" (STR), also known as "sleep mode" or "S3 sleep state", is an energy-saving technology that allows electronic devices or devices such as computers to retain their current working state while maintaining low power consumption. For example, when a computer enters this mode, the system saves all operating states to memory (RAM) and shuts down most other components to save power; when awakened, the computer can quickly return to its working state before hibernation. In order to stop the currently working task, multi-core heterogeneous systems usually take a long time to enter sleep mode or "S3 sleep state" (STR: Suspend to RAM), about 10 seconds. If the on-chip system needs to be awakened during the process of entering STR, it may not be responded to as quickly as possible, resulting in a poor user experience. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a method, device, storage medium and vehicle for canceling the sleep mode, so as to solve the problem that a multi-core heterogeneous system cannot get a response as soon as possible when it needs to wake up the on-chip system during the process of entering the sleep mode.

[0004] The embodiment of the present application adopts the following technical solution: a method for canceling a sleep mode, applied to a multi-core heterogeneous system, the multi-core heterogeneous system comprising a first domain and a second domain, the first domain and the second domain can perform inter-core communication, and the operation of the first domain is at least partially dependent on the second domain;

[0005] The method comprises:

[0006] In response to an instruction to cancel the sleep mode, determining a sleep mode state that the multi-core heterogeneous system is currently in;

[0007] When the first domain is in a first sleep state, stopping the first sleep state of the first domain and waking up the multi-core heterogeneous system;

[0008] When the second domain is in the second sleep state, after the second sleep state of the second domain ends, waking up the multi-core heterogeneous system;

[0009] After the first sleep state of the first domain ends, the second domain enters the second sleep state, and the time required to complete the second sleep state of the second domain is less than the time required to complete the first sleep state of the first domain.

[0010] In some embodiments, the first domain is in a first sleep state, including:

[0011] All application domains in the first domain are in a first sleep state;

[0012] in,

[0013] The first domain includes at least two application domains.

[0014] In some embodiments, the first sleep state includes a first state stage and a second state stage, wherein the first domain enters the second state stage after the first state stage ends;

[0015] All application domains of the first domain are in a first sleep state, including:

[0016] When some application domains in the first domain complete the second state stage and at least one application domain is in the first state stage or the second state stage, after the application domains in the first state stage or the second state stage complete the second state stage, a first instruction is sent to all application domains, wherein the first instruction is used to indicate that all application domains in the first domain complete the second state stage;

[0017] In response to the first instruction, all application domains of the first domain enter a mode that completes a first sleep state.

[0018] In some embodiments, some application domains complete the second state stage, and at least one application domain is in the first state stage or the second state stage, including:

[0019] The part of application domains runs a first operating system and completes the first state stage and the second state stage within a first time;

[0020] The at least one application domain runs a second operating system and completes the first state stage and the second state stage within a second time;

[0021] Wherein, the second time is greater than the first time.

[0022] In some embodiments, the second domain includes any one or more of a security domain, a multifunctional domain, and an information security domain;

[0023] After all application domains of the first domain enter a mode of completing the first sleep state, the method further includes:

[0024] Issue the fourth instruction;

[0025] In the case where the second domain includes the security domain, the multifunctional domain and the information security domain, in response to the fourth instruction, the security domain, the multifunctional domain and the information security domain sequentially enter the sleep mode.

[0026] In some embodiments, after the second sleep state of the second domain ends, waking up the multi-core heterogeneous system includes:

[0027] After the second sleep state of the second domain ends, a second instruction is issued, where the second instruction is used to indicate that the second domain has completed entering the second sleep state;

[0028] In response to the second instruction, the multi-core heterogeneous system is awakened.

[0029] In some embodiments, when the second domain is in the second sleep state, after the second sleep state of the second domain ends, waking up the multi-core heterogeneous system includes:

[0030] Setting a third time, and issuing a third instruction after the third time ends; wherein the third time is used to indicate that the second domain ends entering the second sleep state;

[0031] In response to the third instruction, the multi-core heterogeneous system is awakened.

[0032] The embodiment of the present application also provides a sleep mode cancellation device, which is applied to a multi-core heterogeneous system, and the device includes:

[0033] a determination module configured to determine the current sleep mode state of the multi-core heterogeneous system in response to an instruction to cancel the sleep mode;

[0034] A first wake-up module, configured to, when a first domain of the multi-core heterogeneous system is in a first sleep state, stop the first sleep state of the first domain and wake up the multi-core heterogeneous system;

[0035] A second wake-up module, configured to wake up the multi-core heterogeneous system when the second domain of the multi-core heterogeneous system is in a second sleep state and the second sleep state of the second domain ends;

[0036] After the first sleep state of the first domain ends, the second domain enters the second sleep state, and the time required to complete the second sleep state of the second domain is less than the time required to complete the first sleep state of the first domain.

[0037] An embodiment of the present application further provides a storage medium on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the method described in any of the above embodiments are implemented.

[0038] An embodiment of the present application also provides a vehicle, which wakes up the multi-core heterogeneous system of the vehicle by using the steps of any of the methods described in the above embodiments.

[0039] The beneficial effects of the embodiments of the present application are:

[0040] When a multi-core heterogeneous system receives an instruction to cancel the sleep mode while entering the sleep mode, it is determined which stage of the sleep mode the multi-core heterogeneous system is currently in, and different processing measures are taken according to the different stages it is currently in, so that the multi-core heterogeneous system can be awakened as soon as possible, thereby improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0042] Figure 1 A flowchart of a sleep mode cancellation method for this application;

[0043] Figure 2 A flowchart for canceling the sleep mode for different sleep mode states of a multi-core heterogeneous system corresponding to this application;

[0044] Figure 3 For this application Figure 1 A flowchart of an embodiment of step S20;

[0045] Figure 4 For this application Figure 3 A flowchart of an embodiment of step S21;

[0046] Figure 5 This is a structural block diagram of the multi-core heterogeneous system of this application;

[0047] Figure 6 For this application Figure 1 A flowchart of another embodiment of step S20;

[0048] Figure 7 For this application Figure 1 A flowchart of an embodiment of step S30;

[0049] Figure 8 For this application Figure 7 A flowchart of an embodiment of step S31;

[0050] Fig. 9This is a structural block diagram of the sleep mode cancellation device of this application. DETAILED DESCRIPTION

[0051] Various aspects and features of the present application are described herein with reference to the accompanying drawings.

[0052] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.

[0053] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0054] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0055] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art will be able to readily implement many other equivalent forms of the present application.

[0056] The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.

[0057] Specific embodiments of the present application are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments applied for are merely examples of the present application, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that obscure the present application. Therefore, the specific structural and functional details applied for herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present application in a variety of ways with substantially any suitable detailed structure.

[0058] This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present application.

[0059] First, the application scenarios and technical terms involved in the embodiments of the present application are briefly introduced.

[0060] SOC (System on Chip) refers to the integration of multiple hardware components on a single chip, such as CPU, memory controller, graphics processing unit (GPU), etc., to realize a complete computing system; SOC can contain a wafer (Die) or multiple identical or different wafers.

[0061] A multi-core heterogeneous system is composed of multiple single-core or multi-core processors of different types. Multi-core heterogeneity is a difference at the hardware level. A core heterogeneous system includes at least two processor cores with different architectures. The processor cores and the hardware resources connected to the processor cores constitute independent hardware domains.

[0062] Domain, divides the chip into different areas or functional blocks, each area or functional block is called a domain.

[0063] A hardware domain is a collection of hardware resources. Multi-core heterogeneity is a difference at the hardware level. There may be multiple hardware domains in a multi-core heterogeneous SOC. Since the processor cores are heterogeneous, there is no cache consistency hardware between them. The hardware domains composed of the terminal controller, clock controller and memory of each processor core are hard-isolated. Each processor core cannot be directly scheduled uniformly by the operating system. The hardware resources in the hardware domain of each processor core can only be accessed by its processor core.

[0064] Inter-core communication refers to the communication between different hardware domains within the SOC, including asynchronous message passing through the mailbox mechanism and data sharing across hardware domains through the shared memory mechanism.

[0065] In one of the application scenarios, the vehicle's in-vehicle smart cockpit has a system-on-chip and a multi-core heterogeneous system, and the corresponding functions of the vehicle are implemented and controlled through the system-on-chip and the multi-core heterogeneous system. When the vehicle's ignition key is switched from the ON state to the LOCK or ACC state, in order to save energy and keep the current working state of the system-on-chip and the multi-core heterogeneous system while maintaining low energy consumption, the vehicle's system-on-chip and the multi-core heterogeneous system will enter the STR mode. This process may take about ten seconds. In the process of entering the STR mode, if the user wants to start the vehicle again, so that the vehicle's key is switched to the ON state, at this time, the multi-core heterogeneous system may still be running the process of entering the STR mode, so that the multi-core heterogeneous system cannot be awakened as soon as possible, and the vehicle cannot be started as soon as possible, resulting in a poor user experience. For example, as the vehicle enters the STR mode, the display screen in the vehicle cab may be turned off. When the vehicle key is turned to the ON state, the multi-core heterogeneous system is still running the remaining processes to enter the STR mode, causing the display screen in the cab to be unable to be quickly awakened and display the corresponding content. Only after the entire STR mode is completed can the vehicle respond to the key being turned to the ON state and perform actions such as starting.

[0066] After introducing the application scenarios and design concepts of the embodiments of the present application, the technical solutions provided by the embodiments of the present application are described below.

[0067] To solve the problem in the background technology, an embodiment of the present application provides a sleep mode cancellation method, which can be applied to a multi-core heterogeneous system.

[0068] The multi-core heterogeneous system includes a first domain and a second domain, the first domain and the second domain can perform inter-core communication, and the operation of the first domain is at least partially dependent on the second domain.

[0069] Exemplarily, the first domain can be used to execute a virtualized front end, which is used to interact with a user or an upper-layer application, and the second domain can be used to execute a request from the virtualized front end. This enables the front-end application to start and load faster, reducing the user's waiting time. Specifically, virtualized front-end technology generally refers to the use of virtualization technology to isolate the front-end environment from the underlying hardware or operating system to achieve flexible allocation and management of front-end resources. The virtualized front end can achieve efficient sharing between front-end resources and upper-layer applications. For example, in a microservice architecture, the front-end application can be deployed and managed as an independent service, while sharing computing resources and storage resources with other microservices. Of course, the execution of the virtualized front end, that is, the operation of the first domain, depends to a certain extent on the operation of other domains of the system on chip.

[0070] For example, a vehicle cab can run a multi-core heterogeneous system, which includes a first domain and a second domain. There is a dependency relationship between the first domain and the second domain, and the two domains can communicate with each other so that the dependent domain can know the operation status of other domains that depend on its operation. Of course, it should be noted that the first domain and the second domain are not randomly selected, and there are differences in their functions, performances, and operations, and there is a dependency relationship between the two.

[0071] Specifically, the operation of the first domain depends on the second domain. For example, when the multi-core heterogeneous system receives an instruction to enter the sleep mode, the first domain may enter the sleep state first, and then after the first domain completes entering the sleep state, the second domain starts to enter the sleep state.

[0072] When the multi-core heterogeneous system enters sleep mode, the time required for the first domain to complete entering sleep mode is longer than the time required for the second domain to complete entering sleep mode. For example, if the multi-core heterogeneous system takes 10 seconds to complete the entire sleep mode, the time required for the first domain to complete entering sleep mode may be 8 to 9 seconds, and the time required for the second domain to complete entering sleep mode may be 1 to 2 seconds. Therefore, during the process of the multi-core heterogeneous system entering sleep mode, if an instruction to cancel the sleep mode is received, corresponding processing measures need to be adopted for the corresponding stage of the multi-core heterogeneous system entering sleep mode, so as to cancel the multi-core heterogeneous system from continuing to enter sleep mode as quickly as possible, that is, to achieve the effect of quickly waking up the multi-core heterogeneous system.

[0073] Of course, it is understandable that for different operating systems, the time required for a multi-core heterogeneous system to enter sleep mode may be different. This is only used as an example and does not constitute a limitation on the scope of protection of the claims.

[0074] Combination Figure 1 , the sleep mode cancellation method comprises the following steps:

[0075] S10, in response to an instruction to cancel the sleep mode, determining a current sleep mode state of the multi-core heterogeneous system.

[0076] Exemplarily, the multi-core heterogeneous system may receive an instruction to cancel the sleep mode, and the instruction to cancel the sleep mode may be detected by a detection device, for example, by a microcontroller unit (MCU) or other detection mechanism.

[0077] Continuing with the above embodiment, the state of the vehicle key can be detected by the MCU. When the vehicle key is switched from the LOCK state to the ON state, it indicates that the user wants to cancel the current multi-core heterogeneous system from entering the sleep mode. The multi-core heterogeneous system can be provided with a corresponding interface, which can be used to receive the instruction to cancel the sleep mode.

[0078] For example, when the vehicle key is switched to the ON state, a sleep mode cancel instruction can be generated, and the sleep mode cancel instruction can be sent to the above-mentioned interface of the multi-core heterogeneous system. After receiving the instruction to cancel the sleep mode, the interface can respond to the instruction to cancel the sleep mode. Start to detect the current sleep mode state of the multi-core heterogeneous system, and determine which stage the multi-core heterogeneous system runs to after entering the sleep mode, so as to take corresponding processing measures according to the corresponding stage. Multiple interfaces can be set in case a certain interface fails and cannot receive the corresponding sleep mode cancel instruction. The type of interface can be set according to actual needs, and no specific restrictions are made here.

[0079] S20: When the first domain is in a first sleep state, stop the first sleep state of the first domain and wake up the multi-core heterogeneous system.

[0080] Exemplarily, because the operation of the first domain is at least partially dependent on the second domain, when the multi-core heterogeneous system enters sleep mode, the first domain starts to enter sleep mode first, that is, the first domain starts to enter the first sleep state first. After the first domain completes entering the first sleep state, the first domain can send a corresponding completion signal to the second domain based on inter-core communication with the second domain, so that the second domain can start to enter sleep mode after the first domain completes the first sleep state.

[0081] The time required to complete the second sleep state of the second domain is less than the time required to complete the first sleep state of the first domain. As described in the above embodiment, if the multi-core heterogeneous system takes 10 seconds to complete the entire sleep mode, the time required for the first domain to complete entering the sleep mode may be 8 to 9 seconds, and the time required for the second domain to complete entering the sleep mode may be 1 to 2 seconds.

[0082] If the second domain of the multi-core heterogeneous system has not yet started to enter the sleep mode when the instruction to cancel the sleep mode is received, and only the first domain is in the first sleep state, the first sleep state of the first domain can be stopped immediately. Even if the first domain no longer continues to run the program or instruction to enter the sleep mode, the multi-core heterogeneous system can be awakened as soon as possible.

[0083] For example, continuing with the above embodiment, the time required for the first domain to complete entering the sleep mode is 8 seconds. When an instruction to cancel the sleep mode is received, the time it takes for the first domain to start entering the sleep mode is 2 seconds, that is, the first domain is in the first sleep mode state. At this time, the first domain can be immediately stopped from continuing to run the program or instruction to enter the sleep mode, and the first domain immediately exits the first sleep state, that is, the first sleep state of the first domain is interrupted, and the wake-up of the multi-core heterogeneous system is completed.

[0084] It should be noted that, although the time required for the first domain to enter the sleep mode is longer than that required for the second domain to enter the sleep mode, the operation of the second domain requires more operation of the hardware driver, so if the hardware driver has entered the sleep mode, it is impossible to cancel the sleep mode immediately. However, when the first domain responds to the instruction to cancel the sleep mode, it can respond to the instruction quickly and cancel the sleep mode immediately.

[0085] S30: When the second domain is in the second sleep state, waking up the multi-core heterogeneous system after the second sleep state of the second domain ends.

[0086] For example, if the second domain of the multi-core heterogeneous system is in the second sleep state when receiving the instruction to cancel the sleep mode, it means that the first domain of the multi-core heterogeneous system has completed entering the sleep mode, and the second domain has already started to enter the sleep mode. Because the second domain takes a shorter time (1 to 2 seconds) to complete entering the sleep mode than the first domain, the second sleep state of the second domain may not be interrupted. After the second domain completes entering the sleep state, the multi-core heterogeneous system is awakened in response to the instruction to cancel the sleep mode.

[0087] In addition, the operation of the second domain mostly depends on the operation of the hardware driver. When the second domain enters the second sleep state, it means that the hardware driver of the second domain may have stopped running and cannot be quickly canceled.

[0088] Continuing with the above-mentioned embodiments, compared to the process in which the multi-core heterogeneous system enters the sleep mode, after the key state of the vehicle is converted to the ON state, the multi-core heterogeneous system needs to complete the sleep mode of the entire system (for example, it takes 10 seconds) and then re-awaken the multi-core heterogeneous system. In the embodiment of the present application, when the multi-core heterogeneous system enters the sleep mode, the multi-core heterogeneous system receives an instruction to cancel the sleep mode, by determining which stage of the sleep mode the multi-core heterogeneous system is currently in, and taking different processing measures according to the different stages it is currently in, so that the multi-core heterogeneous system can be awakened as soon as possible, thereby improving the user experience. In particular, when the first domain of the multi-core heterogeneous system is in the first sleep state, the embodiment of the present application can cancel the sleep mode of the multi-core heterogeneous system more quickly, so that it can be quickly awakened, thereby improving the user experience. In addition, when canceling the sleep mode of the multi-core heterogeneous system, multiple domains of the multi-core heterogeneous system can also be linked.

[0089] In some embodiments, the first domain is in a first sleep state, including:

[0090] All application domains in the first domain are in a first sleep state;

[0091] in,

[0092] The first domain includes at least two application domains.

[0093] Exemplarily, the first domain may include application domains, and the number of application domains may be multiple, and the multiple application domains may be run by the same operating system or by different operating systems, and the speeds at which the multiple application domains complete entering the sleep mode may be the same or different. However, in the embodiment of the present application, before the second domain starts to enter the sleep mode, all application domains in the first domain need to be synchronously maintained in the first sleep state to avoid the situation where the multiple application domains in the first domain complete entering the sleep mode at different speeds, and some application domains complete entering the sleep mode at a faster speed. After completing entering the sleep mode, the multi-core heterogeneous system will start the second domain to enter the sleep mode, that is, the second domain starts to enter the second sleep state, while at this time, other application domains in the first domain have not completed entering the sleep mode, that is, other application domains in the first domain are still maintained in the first sleep state, which will cause the hardware driver of the second domain to stop, and it is no longer possible to quickly cancel the sleep mode of the multi-core heterogeneous system.

[0094] Combination Figure 2, take the first domain including two application domains (AP1 and AP2) as an example, AP1 in the first domain runs the Android operating system, and AP2 runs Linux (operating system kernel). The time to complete the sleep mode is different for the two, and AP2 can complete the sleep mode faster. When the application domain enters the sleep mode, it can include the following processes. The first process is postpone: request to postpone entering STR; the second process is Deep sleep: the application domain has stopped and the underlying suspend (such as kernel suspend: kernel sleep) can be executed. When the application domain completes the first two processes, it can enter Str finish: ap STR action execution is completed.

[0095] In the embodiment of the present application, after AP2 completes the first two processes, AP2 no longer takes any action, but waits for AP1 to complete the first two states, that is, waits for AP1 to complete the Deep sleep process. After both application domains complete the first two states, the two application domains are allowed to perform Str finish, indicating that both application domains have completed entering the sleep mode state.

[0096] The present application aligns the status of all application domains in the first domain completing entering the sleep mode, that is, before the second domain starts to enter the sleep mode, all application domains in the first domain have completed entering the sleep mode. This avoids the situation where different application domains enter the sleep mode at different speeds, resulting in the second domain of the multi-core heterogeneous system entering the sleep mode without completing the entry of the sleep mode, thus affecting the cancellation of the sleep mode by the multi-core heterogeneous system.

[0097] Combination Figure 2 In the STR process, the STR process is divided into two stages: "Phase 1" and "Phase 2". Usually, the characteristics of "Phase 1" in the process of entering STR are: it takes a long time to execute the stop application operation, but the str cancel action is easy to implement; the characteristics of "Phase 2" are: the execution time of underlying related operations is short, and the str cancel action is difficult to implement. Therefore, when the multi-core heterogeneous system receives a str cancel request in "Phase 1", the system directly sends a command to the VHAL (Vehicle Hardware Abstraction Layer) of AP1 and AP2 to implement the str cancel function. When the multi-core heterogeneous system receives a str cancel request in "Phase 2", it is ensured that the multi-core heterogeneous system can be woken up after the STR entry action is completed.

[0098] In some embodiments, the first sleep state includes a first state stage and a second state stage, wherein the first domain enters the second state stage after the first state stage ends.

[0099] Combination Figure 3 , all application domains of the first domain are in a first sleep state, including:

[0100] S21, when some application domains in the first domain complete the second state stage and at least one application domain is in the first state stage or the second state stage, after the application domain in the first state stage or the second state stage completes the second state stage, a first instruction is sent to all application domains, wherein the first instruction is used to indicate that all application domains in the first domain have completed the second state stage.

[0101] For example, again in combination with the above embodiments and Figure 2 , the first state stage is the first process (postpone) mentioned above; the second state stage is the second process (Deep sleep) mentioned above. After AP2 completes the first state stage and the second state stage in sequence, no matter whether AP1 is in the first state stage or the second state stage, AP2 remains in the waiting state and does not perform other operations. When AP1 enters the sleep mode, a postpone instruction is sent to AP1 at a certain interval (for example, every 3 seconds) to prevent the application domain from entering the sleep mode abnormally due to failure to receive the corresponding instruction during the execution of entering the sleep mode.

[0102] After both AP1 and AP2 complete the second state stage, a first instruction is sent to AP1 and AP2 at the same time, informing AP1 and AP2 to enter Str finish.

[0103] In the embodiment of the present application, after AP2 completes the first two processes, AP2 no longer takes any action, but waits for AP1 to complete the first two states, that is, waits for AP1 to complete the Deep sleep process. After both application domains complete the first two states, the two application domains enter Str finish, indicating that both application domains have completed entering the sleep mode state.

[0104] S22: In response to the first instruction, all application domains of the first domain enter a mode of completing a first sleep state.

[0105] Exemplarily, after receiving the first instruction, both AP1 and AP2 enter the Str finish stage, indicating that the states of all application domains of the first domain are synchronized, that is, they have completed the mode of entering the first sleep state. At this time, the second domain can enter its corresponding second sleep state mode after the first domain completes the mode of entering the first sleep state.

[0106] In some embodiments, in combination Figure 4, some application domains complete the second state stage, and at least one application domain is in the first state stage or the second state stage, including:

[0107] S211, the part of application domains runs a first operating system and completes the first state stage and the second state stage within a first time.

[0108] S212: The at least one application domain runs a second operating system and completes the first state stage and the second state stage within a second time.

[0109] Wherein, the second time is greater than the first time.

[0110] Exemplary, again combined Figure 2 , AP2 runs a first operating system, which may be, but is not limited to, a Linux operating system. For example, AP2 can complete the first state stage and the second state stage within 4 seconds. AP1 runs a second operating system, which may be, but is not limited to, an Android system, and AP1 needs to complete the first state stage and the second state stage within 8 seconds.

[0111] That is, the time required for AP1 to complete the first state stage and the second state stage is longer than the time required for AP2 to complete the first state stage and the second state stage. Of course, when the first domain includes more applications, some application domains may have the same time required to complete the first state stage and the second state stage. This is only used as an example and does not constitute a limitation on the scope of protection of the claims.

[0112] In addition, AP1 and AP2 may also run the same operating system, but the time required for AP1 and AP2 to complete the first state stage and the second state stage is different.

[0113] In some embodiments, in combination Figure 5 The second domain includes any one or more combinations of a security domain, a multi-function domain and an information security domain.

[0114] Combination Figure 6 , after all application domains of the first domain enter a mode of completing the first sleep state, the method further includes:

[0115] S23, issue a fourth instruction.

[0116] S24, in the case where the second domain includes the security domain, the multifunctional domain and the information security domain, in response to the fourth instruction, the security domain, the multifunctional domain and the information security domain sequentially enter the sleep mode.

[0117] Exemplarily, after all application domains of the first domain enter the mode of completing the first sleep state, a fourth instruction can be sent to the second domain based on the inter-core communication between the first domain and the second domain, and the fourth instruction is used to notify the second domain that it can start to enter the sleep mode.

[0118] After receiving the fourth instruction, the second domain begins to enter sleep mode. For example, the safety domain, the multi-function domain (mp), and the information security domain (secure) in the second domain can enter sleep mode in turn. Among them, the safety domain has an ultra-fast response speed and powerful functional safety characteristics, and each function will not fail easily. The multi-function domain uses a multi-function processor. In combination with the car, it is used to run various back-ends, such as sound, display, backlight, and management of the back-end of reversing. The operation of the security domain may also depend on the operation of the multi-function domain and the information security domain to a certain extent. The information security domain is referred to as SEC. The information security domain has a high security feature and uniformly handles data security-related matters. The information security domain uses an information security processor, which can be a collection of the information security domain (HSM), the storage service end (eMMC), and the OTA service end (eMMC). Based on the relationship between the above hardware domains in the second domain, after receiving the fourth instruction, the second domain can send an instruction to enter the sleep mode to the security domain, and after the security domain completes entering the sleep mode, it can send an instruction to enter the sleep mode to the multifunctional domain, and after the multifunctional domain completes entering the sleep mode, it can send an instruction to enter the sleep mode to the information security domain, and after the information security domain completes entering the sleep mode, the second domain completes entering the second sleep state. The above-mentioned method of entering the sleep mode of the second domain can ensure that each hardware domain in the second domain can smoothly complete entering the sleep mode, and avoid abnormalities in the process of each hardware domain entering the sleep mode, which affects the second domain entering the sleep mode.

[0119] Of course, it is understandable that the second domain may also include other hardware domains, or one or two of the above three hardware domains. This is only used as an example and does not constitute a limitation on the protection scope of the claims.

[0120] In some embodiments, in combination Figure 7 , after the second sleep state of the second domain ends, waking up the multi-core heterogeneous system, including:

[0121] S31, after the second sleep state of the second domain ends, issuing a second instruction, where the second instruction is used to indicate that the second domain has completed entering the second sleep state.

[0122] S32, in response to the second instruction, waking up the multi-core heterogeneous system.

[0123] Exemplarily, after the second domain has completed entering the sleep mode, that is, after the second sleep state of the second domain has ended, a second instruction may be issued, indicating that the second domain has completed entering the second sleep state, and the multi-core heterogeneous system may be awakened at this time. In response to the second instruction, the multi-core heterogeneous system is awakened. Here, while responding to the second instruction, the multi-core heterogeneous system simultaneously responds to the instruction to cancel the sleep mode.

[0124] Because the time for the second domain to complete entering the second sleep state is short, which may be only 1 to 2 seconds, after the second domain starts to enter the second sleep state, it will no longer respond to the instruction to cancel the sleep mode and interrupt the operation process of the second domain entering the second sleep state.

[0125] In some embodiments, in combination Figure 8 , when the second domain is in the second sleep state, after the second sleep state of the second domain ends, waking up the multi-core heterogeneous system, including:

[0126] S311, setting a third time, and issuing a third instruction after the third time ends; wherein the third time is used to indicate that the second domain ends entering the second sleep state;

[0127] S312, in response to the third instruction, waking up the multi-core heterogeneous system.

[0128] Exemplarily, the timing can be performed by setting a timer, and the timing time of the timer is 1 to 2 seconds, or it can be set according to the actual situation. Within the timing time of the timer, it is enough for the second sleep state of the second domain to end. Of course, it is not that the longer the third time is set, the better, but while ensuring that the second sleep state of the second domain can end, the shorter the third time is set, the more conducive it is for the multi-core heterogeneous system to respond to the instruction to cancel the sleep mode, and it can be awakened more quickly, meeting the user experience requirements.

[0129] Combination Fig. 9 An embodiment of the present application also provides a sleep mode cancellation device, which is applied to a multi-core heterogeneous system. The multi-core heterogeneous system includes a first domain and a second domain. The first domain and the second domain can communicate between cores, and the operation of the first domain is at least partially dependent on the second domain.

[0130] The sleep mode canceling device includes:

[0131] A determination module is configured to determine the current sleep mode state of the multi-core heterogeneous system in response to an instruction to cancel the sleep mode.

[0132] Exemplarily, the multi-core heterogeneous system may receive an instruction to cancel the sleep mode, and the instruction to cancel the sleep mode may be detected by a detection device, for example, by a microcontroller unit (MCU) or other detection mechanism.

[0133] Continuing with the above embodiment, the state of the vehicle key can be detected by the MCU. When the vehicle key is switched from the LOCK state to the ON state, it indicates that the user wants to cancel the current multi-core heterogeneous system from entering the sleep mode. The multi-core heterogeneous system can be provided with a corresponding interface, which can be used to receive the instruction to cancel the sleep mode.

[0134] For example, when the vehicle key is switched to the ON state, a sleep mode cancellation instruction may be generated, and the sleep mode cancellation instruction may be sent to the above-mentioned interface of the multi-core heterogeneous system. After receiving the sleep mode cancellation instruction, the interface may respond to the sleep mode cancellation instruction. The sleep mode state of the multi-core heterogeneous system is detected, and the stage of the multi-core heterogeneous system after entering the sleep mode is determined, so as to take corresponding processing measures according to the corresponding stage.

[0135] The first wake-up module is configured to stop the first sleep state of the first domain and wake up the multi-core heterogeneous system when the first domain of the multi-core heterogeneous system is in the first sleep state.

[0136] Exemplarily, because the operation of the first domain is at least partially dependent on the second domain, when the multi-core heterogeneous system enters sleep mode, the first domain starts to enter sleep mode first, that is, the first domain starts to enter the first sleep state first. After the first domain completes entering the first sleep state, the first domain can send a corresponding completion signal to the second domain based on inter-core communication with the second domain, so that the second domain can start to enter sleep mode after the first domain completes the first sleep state.

[0137] The time required to complete the second sleep state of the second domain is less than the time required to complete the first sleep state of the first domain. As described in the above embodiment, if the multi-core heterogeneous system takes 10 seconds to complete the entire sleep mode, the time required for the first domain to complete entering the sleep mode may be 8 to 9 seconds, and the time required for the second domain to complete entering the sleep mode may be 1 to 2 seconds.

[0138] If the second domain of the multi-core heterogeneous system has not yet started to enter the sleep mode when the instruction to cancel the sleep mode is received, and only the first domain is in the first sleep state, the first sleep state of the first domain can be stopped immediately. Even if the first domain no longer continues to run the program or instruction to enter the sleep mode, the multi-core heterogeneous system can be awakened as soon as possible.

[0139] For example, continuing with the above embodiment, the time required for the first domain to complete entering the sleep mode is 8 seconds. When an instruction to cancel the sleep mode is received, the time it takes for the first domain to start entering the sleep mode is 2 seconds, that is, the first domain is in the first sleep mode state. At this time, the first domain can be immediately stopped from continuing to run the program or instruction to enter the sleep mode, and the first domain immediately exits the first sleep state, that is, the first sleep state of the first domain is interrupted, and the wake-up of the multi-core heterogeneous system is completed.

[0140] It should be noted that, although the time required for the first domain to enter the sleep mode is longer than that required for the second domain to enter the sleep mode, the operation of the second domain requires more operation of the hardware driver, so if the hardware driver has entered the sleep mode, it is impossible to cancel the sleep mode immediately. However, when the first domain responds to the instruction to cancel the sleep mode, it can respond to the instruction quickly and cancel the sleep mode immediately.

[0141] The second wake-up module is configured to wake up the multi-core heterogeneous system after the second sleep state of the second domain ends when the second sleep state of the second domain ends.

[0142] For example, if the second domain of the multi-core heterogeneous system is in the second sleep state when receiving the instruction to cancel the sleep mode, it means that the first domain of the multi-core heterogeneous system has completed entering the sleep mode, and the second domain has already started to enter the sleep mode. Because the second domain takes a shorter time (1 to 2 seconds) to complete entering the sleep mode than the first domain, the second sleep state of the second domain may not be interrupted. After the second domain completes entering the sleep state, the multi-core heterogeneous system is awakened in response to the instruction to cancel the sleep mode.

[0143] In addition, the operation of the second domain mostly depends on the operation of the hardware driver. When the second domain enters the second sleep state, it means that the hardware driver of the second domain may have stopped running and cannot be quickly canceled.

[0144] An embodiment of the present application further provides a storage medium on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the method described in any of the above embodiments are implemented.

[0145] In various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0146] Those of ordinary skill in the art will appreciate that the various illustrative logic blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0147] The embodiments of the present application also provide a vehicle, which uses the steps of any of the methods described in the above embodiments to wake up the multi-core heterogeneous system of the vehicle. Optionally, the vehicle in the embodiments of the present application may be an "automobile", "vehicle" and "entire vehicle" or other similar terms including general motor vehicles, such as sedans, SUVs, MPVs, buses, trucks and other cargo or passenger vehicles, watercraft including various ships and boats, and aircraft, etc., including hybrid vehicles, electric vehicles, fuel vehicles, plug-in hybrid vehicles, fuel cell vehicles and other alternative fuel vehicles. Among them, a hybrid vehicle refers to a vehicle with two or more power sources, and an electric vehicle includes a pure electric vehicle, an extended-range electric vehicle, etc., which is not specifically limited in the present application.

[0148] Multiple embodiments of the present application are described in detail above, but the present application is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concept of the present application, and these variations and modifications should all fall within the scope of protection required by the present application.

Claims

1. A method for canceling a sleep mode, characterized in that: Applied to a multi-core heterogeneous system, the multi-core heterogeneous system includes a first domain and a second domain, the first domain and the second domain can perform inter-core communication, and the operation of the first domain is at least partially dependent on the second domain; The method comprises: In response to an instruction to cancel the sleep mode, determining a sleep mode state that the multi-core heterogeneous system is currently in; When the first domain is in a first sleep state, stopping the first sleep state of the first domain, even if the first domain no longer continues to execute the instruction to enter the sleep mode, waking up the multi-core heterogeneous system; When the second domain is in the second sleep state, after the second sleep state of the second domain ends, waking up the multi-core heterogeneous system; After the first domain completes entering the first sleep state, the second domain starts to enter the second sleep state, and the time required to complete the second sleep state of the second domain is less than the time required to complete the first sleep state of the first domain.

2. The method for canceling the sleep mode according to claim 1, characterized in that: The first domain completes entering the first sleep state, including: All application domains in the first domain complete entering the first sleep state; in, The first domain includes at least two application domains.

3. The method for canceling the sleep mode according to claim 2, characterized in that: The first sleep state includes a first state stage and a second state stage, wherein the first domain enters the second state stage after the first state stage ends; All application domains of the first domain complete entering the first sleep state, including: When some application domains in the first domain complete the second state stage and at least one application domain is in the first state stage or the second state stage, after the application domains in the first state stage or the second state stage complete the second state stage, a first instruction is sent to all application domains, wherein the first instruction is used to indicate that all application domains in the first domain complete the second state stage; In response to the first instruction, all application domains of the first domain enter a mode that completes a first sleep state.

4. The method for canceling the sleep mode according to claim 3, characterized in that: Part of the application domains complete the second state stage, and at least one application domain is in the first state stage or the second state stage, including: The part of application domains runs a first operating system and completes the first state stage and the second state stage within a first time; The at least one application domain runs a second operating system and completes the first state stage and the second state stage within a second time; Wherein, the second time is greater than the first time.

5. The method for canceling the sleep mode according to claim 3, characterized in that: The second domain includes any one or more combinations of a security domain, a multifunctional domain and an information security domain; After all application domains of the first domain enter a mode of completing the first sleep state, the method further includes: Issue the fourth instruction; In the case where the second domain includes the security domain, the multifunctional domain and the information security domain, in response to the fourth instruction, the security domain, the multifunctional domain and the information security domain sequentially enter the sleep mode.

6. The method for canceling the sleep mode according to claim 1, characterized in that: After the second sleep state of the second domain ends, waking up the multi-core heterogeneous system includes: After the second sleep state of the second domain ends, a second instruction is issued, where the second instruction is used to indicate that the second domain has completed entering the second sleep state; In response to the second instruction, the multi-core heterogeneous system is awakened.

7. The method for canceling the sleep mode according to claim 1, characterized in that: In a case where the second domain is in a second sleep state, after the second sleep state of the second domain ends, waking up the multi-core heterogeneous system, including: Setting a third time, and issuing a third instruction after the third time ends; wherein the third time is used to indicate that the second domain ends entering the second sleep state; In response to the third instruction, the multi-core heterogeneous system is awakened.

8. A sleep mode canceling device, characterized in that: Applied to a multi-core heterogeneous system, the device comprises: a determination module configured to determine the current sleep mode state of the multi-core heterogeneous system in response to an instruction to cancel the sleep mode; a first wake-up module configured to, when a first domain of the multi-core heterogeneous system is in a first sleep state, stop the first sleep state of the first domain, and wake up the multi-core heterogeneous system even if the first domain no longer continues to execute an instruction to enter a sleep mode; A second wake-up module, configured to wake up the multi-core heterogeneous system when the second domain of the multi-core heterogeneous system enters a second sleep state and the second sleep state of the second domain ends; After the first domain completes entering the first sleep state, the second domain starts to enter the second sleep state, and the time required to complete the second sleep state of the second domain is less than the time required to complete the first sleep state of the first domain.

9. A storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the steps of the method as claimed in any one of claims 1 to 7 are implemented.

10. A vehicle, characterized in that: The multi-core heterogeneous system of the vehicle is awakened by adopting the steps of the method as claimed in any one of claims 1 to 7.

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