Matrix operation method, processor and computing device

Abstract

The embodiment disclosed by the application belongs to the technical field of computing, and particularly relates to a matrix operation method, a processor and a computing device. The matrix operation method is executed by a processor comprising a matrix register. In the matrix operation method, first matrix data to be transposed can be stored into the matrix register, wherein the first matrix comprises N rows and M columns, and the matrix register stores the first matrix data in a two-dimensional form of N rows and M columns. Then the first matrix data can be read from the matrix register in a row-by-row or column-by-column manner, and second matrix data obtained after the first matrix data is transposed can be obtained, wherein the second matrix comprises M rows and N columns. The matrix register can be used to complete matrix transposition, and the efficiency of matrix transposition can be improved.

Description

[0001] This application is a divisional application, the original application number is 202311036871.4, the original application date is August 16, 2023, and the entire contents of the original application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of computing, in particular to a matrix operation method, a processor and a computing device. BACKGROUND

[0003] Matrix operation is a kind of operation frequently used in high performance computing (HPC) applications, including matrix transposition, addition, subtraction and multiplication, etc.

[0004] At present, when the matrix in the HPC application needs to be transposed, the processor can complete the transposition of the matrix with the help of scalar registers or vector registers, which is low in efficiency. SUMMARY

[0005] The embodiments of the present application provide a matrix operation method, a processor and a computing device, which can complete matrix transposition with the help of matrix registers, can improve the efficiency of transposing the matrix, and the corresponding technical solutions are as follows:

[0006] In a first aspect, a matrix operation method is provided, which is executed by a processor including a matrix register, and the matrix operation method comprises:

[0007] The processor stores first matrix data to the matrix register. The first matrix contains N rows and M columns, and the matrix register stores the first matrix data in the form of two dimensions of N rows and M columns. Then the processor reads the first matrix data from the matrix register in a row-by-row or column-by-column manner to obtain second matrix data containing M rows and N columns after transposing the first matrix data. M and N are positive integers, and the values of M and N can be equal or not equal.

[0008] The matrix register is a register capable of storing matrix data in the form of two dimensions. The processor can provide a read instruction for reading the matrix data stored in the matrix register by column or by row. The processor can also provide a storage instruction for storing vector data (such as a column in the matrix data) to the matrix register in the form of a row or a column. When the processor reads and stores data in the matrix register in the form of a row or a column, the difference in corresponding read performance and storage performance can be ignored.

[0009] In the scheme shown in the present application, for the first matrix data corresponding to the first matrix to be transposed, the processor can store the first matrix data to the matrix register. When each row of data stored in the matrix register is each row of data of the first matrix, the processor can read out the first matrix data stored by the matrix register in a column-by-column manner, and the second matrix data of the second matrix obtained by transposing the first matrix can be obtained. When each row of data stored in the matrix register is each column of data of the first matrix, the processor can read out the first matrix data stored by the matrix register in a row-by-row manner, and the second matrix data of the second matrix obtained by transposing the first matrix can be obtained.

[0010] It can be seen that the scheme shown in the present application only needs to store the matrix data to be transposed to the matrix register, and then change the reading mode to read out the matrix data stored in the matrix register, so that the transposition of the matrix can be realized. In this way, for a matrix of N rows and M columns, only N storage instructions plus M reading instructions (or M storage instructions plus N reading instructions) can realize the transposition operation of the matrix, which can reduce the number of instructions required for transposing the matrix and improve the efficiency of transposing the matrix.

[0011] In an implementable manner, storing the first matrix data to the matrix register comprises: storing the first matrix data stored in the memory to the matrix register in a row-by-row or column-by-column manner.

[0012] In the scheme shown in the present application, the first matrix data can be stored in the memory in an array manner. According to different storage modes, the processor can read one row of data or one column of data of the first matrix from the memory each time. For each row of data that can be read from the memory each time, the processor can store it to the matrix register in a row or column manner. That is, each row of data of the first matrix read out by the processor can be stored in the matrix register by row or by column. For each column of data that can be read from the memory each time, the processor can store it to the matrix register in a row or column manner. That is, each column of data of the first matrix read out each time can be stored in the matrix register by row or by column.

[0013] The processor can read the first matrix data stored in the matrix register in a column-by-column manner to obtain the second matrix data after transposition. The processor can read the first matrix data stored in the matrix register in a row-by-row manner to obtain the second matrix data after transposition. It can be seen that, according to the scheme shown in the present application, the processor only needs to store the matrix data to be transposed into the matrix register, and then change the reading manner to read the matrix data stored in the matrix register, so that the transposition of the matrix can be realized, and the number of instructions required for transposing the matrix can be reduced, and the efficiency of transposing the matrix can be improved.

[0014] In an implementable manner, the processor further includes a vector register. Correspondingly, storing the first matrix data into the matrix register includes: storing the first matrix data into the vector register in the form of vector data. The corresponding vector data of the first matrix data stored in the vector register is stored into the matrix register in a row or column manner.

[0015] In the scheme shown in the present application, the processor further includes a vector register, and the processor can store the matrix data into the matrix register by means of the vector register. For each row or column of data of the first matrix read from the memory, the processor can first store the row or column of data of the first matrix into the vector register in the form of a vector, and then read the row or column of data of the first matrix stored in the vector register into the matrix register, so as to store the first matrix data into the matrix register. In this way, the memory stores the matrix data into the matrix register through the vector register, which can reduce the number of data channels established between the memory and the matrix register, and can reduce the hardware cost of the processor.

[0016] In an implementable manner, the first matrix data is read from the matrix register in a row-by-row or column-by-column manner to obtain the second matrix data after transposition of the first matrix data, including: reading the first matrix data from the matrix register in a row-by-row or column-by-column manner, and storing each time read vector data into the vector register. The vector data stored in the vector register is read into the memory to obtain the second matrix data after transposition of the first matrix data.

[0017] In the scheme shown in the present application, the processor can store matrix data into the matrix register by means of the vector register, and can also read matrix data from the matrix register by means of the vector register. Wherein, for each row or column of data read from the matrix register, the processor can first store the data into the vector register in the form of a vector, and then read the row or column of data stored in the vector register into the memory, thereby realizing reading the first matrix data from the matrix register in the form of row or column. In this way, the memory stores matrix data into the matrix register by means of the vector register, and reads matrix data from the matrix register by means of the vector register, which can avoid establishing a data channel between the memory and the matrix register, and further reduce the hardware cost of the processor.

[0018] In an implementable manner, the processor further comprises a vector register. Correspondingly, reading the first matrix data from the matrix register in the form of row or column to obtain the second matrix data after transposing the first matrix data comprises: reading the first matrix data from the matrix register in the form of row or column, and storing each time reading into the vector register.

[0019] In the scheme shown in the present application, the processor further comprises a vector register, and the processor can read the matrix data stored in the matrix register into the memory by means of the vector register. Wherein, for each row or column of data read from the matrix register, the processor can first store the data into the vector register in the form of a vector, and then read the row or column of data stored in the vector register into the memory, thereby realizing reading the first matrix data from the matrix register in the form of row or column. In this way, the memory reads matrix data from the matrix register by means of the vector register, which can reduce the number of data channels established between the memory and the matrix register, and further reduce the hardware cost of the processor.

[0020] In an implementable manner, the processor further comprises a calculation unit. Correspondingly, after obtaining the second matrix data after transposing the first matrix data, the method further comprises: inputting the second matrix data into the calculation unit, and performing specified calculation on the second matrix data by the calculation unit.

[0021] In the scheme shown in the present application, the processor further comprises a calculation unit, such as a matrix calculation unit, a vector calculation unit, etc. After reading the second matrix data after transposing from the matrix data stored in the matrix register, the read second matrix data can be directly input into the calculation unit for subsequent calculation, without the need to store the read second matrix data into the memory, thereby improving the efficiency of matrix operation.

[0022] In a second aspect, a processor is provided, the processor comprising a matrix register, the processor configured to: store first matrix data to the matrix register, the first matrix comprising N rows and M columns, the matrix register configured to store the first matrix data in a two-dimensional form of N rows and M columns; and read the first matrix data from the matrix register in a row-by-row or column-by-column manner to obtain second matrix data after transposing the first matrix data, the second matrix comprising M rows and N columns.

[0023] In an implementable manner, the processor is configured to: store the first matrix data stored in the memory to the matrix register in a row-by-row or column-by-column manner.

[0024] In an implementable manner, the processor further comprises a vector register, and the processor is configured to: store the first matrix data to the vector register in a form of vector data; and store the vector data corresponding to the first matrix data stored in the vector register to the matrix register in a row or column manner.

[0025] In an implementable manner, the processor is configured to: read the first matrix data from the matrix register in a row-by-row or column-by-column manner, and store each read to the vector data to the vector register; and read the vector data stored in the vector register to the memory to obtain the second matrix data after transposing the first matrix data.

[0026] In an implementable manner, the processor further comprises a vector register, and the processor is configured to: read the first matrix data from the matrix register in a row-by-row or column-by-column manner, and store each read to the vector data to the vector register; and read the vector data stored in the vector register to the memory to obtain the second matrix data after transposing the first matrix data.

[0027] In an implementable manner, the processor further comprises a computing unit, and the processor is further configured to: input the second matrix data to the computing unit, and perform a specified computation on the second matrix data by the computing unit.

[0028] In a third aspect, a computing device is provided, the computing device comprising a memory and a processor, the processor configured to execute instructions stored in the memory to cause the processor to perform the matrix operation method according to the first aspect.

[0029] In a fourth aspect, a computer program product comprising instructions which, when executed by the computing device according to the third aspect, cause the computing device to perform the matrix operation method according to the first aspect.

[0030] In a fifth aspect, a computer-readable storage medium is provided, the computer-readable storage medium comprising computer program instructions, when executed by the computing device according to the third aspect, the computing device can perform the matrix operation method according to the first aspect. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a method for transposing a matrix using a scalar register in related technologies;

[0032] Figure 2 This is a schematic diagram of a method for transposing a matrix using a vector register in related technologies;

[0033] Figure 3 This is a schematic diagram of a computing device structure provided in an embodiment of this application;

[0034] Figure 4 This is a flowchart of a matrix operation method provided in an embodiment of this application;

[0035] Figure 5 This is a schematic diagram of a matrix transpose provided in an embodiment of this application;

[0036] Figure 6 This is a schematic diagram of a computing device structure provided in an embodiment of this application;

[0037] Figure 7 This is a schematic diagram of a matrix transpose provided in an embodiment of this application;

[0038] Figure 8 This is a schematic diagram of a computing device structure provided in an embodiment of this application;

[0039] Figure 9 This is a schematic diagram of a matrix transpose provided in an embodiment of this application;

[0040] Figure 10 This is a schematic diagram of a computing device structure provided in an embodiment of this application. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0042] Matrix operations are frequently used in computers, especially in high-performance computing (HPC) and artificial intelligence. Matrix operations include transpose, addition, subtraction, and multiplication. In related technologies, matrix operations are generally implemented using scalar processors or vector memories.

[0043] Figure 1is a schematic diagram of a method for transposing a matrix by means of a scalar register in the related art. In internal storage such as memory, cache, etc., a matrix can be stored in the form of an array. For example, a matrix If the matrix A is stored in memory by row, the matrix actually stored in memory is [1, 2, 3, 4, 5, 6, 7, 8, 9], and if the matrix A is stored in memory by column, the matrix actually stored in memory is [1, 4, 7, 2, 5, 8, 3, 6, 9]. As shown in Figure 1 If the matrix A is transposed by means of a scalar register in an example, and the matrix is stored in memory by row, that is, the matrix A stored in memory is [1, 2, 3, 4, 5, 6, 7, 8, 9], each element "1", "4", "7", "2", "5", "8", "3", "6", "9" of the matrix A stored in memory can be read in turn. After each element is read, the read element can be stored in the scalar register, and then the element stored in the scalar register is stored back in the memory. In this way, the elements "1", "4", "7", "2", "5", "8", "3", "6", "9" can be sequentially stored in the memory to obtain the matrix B after the matrix A is transposed. The matrix B is stored in memory by row, that is, the matrix B [1, 4, 7, 2, 5, 8, 3, 6, 9], that is If the matrix A is transposed in this way, 9 scalar Load instructions are required to sequentially store the elements of the matrix A in the memory into the scalar register, and 9 scalar Store instructions are required to sequentially store the elements in the scalar register back into the memory. Similarly, if a n x n matrix is transposed by means of a scalar register, n 2 scalar Load instructions and n 2 scalar Store instructions are required.

[0044] Figure 2 is a schematic diagram of a method for transposing a matrix by means of a vector register in the related art. As shown in Figure 2 If the matrix A is transposed by means of a vector register in an example, and the matrix is stored in memory by row, that is, the matrix A stored in memory is [1, 2, 3, 4, 5, 6, 7, 8, 9], each column element "1, 4, 7", "2, 5, 8", "3, 6, 9" of the matrix A stored in memory can be read in turn. Each column element read can be stored in the vector register, and then the element stored in the vector register is stored back in the memory. In this way, the elements "1, 4, 7", "2, 5, 8", "3, 6, 9" can be sequentially stored in the memory to obtain the matrix B after the matrix A is transposed. The matrix B is stored in memory by row, that is, the matrix B [1, 4, 7, 2, 5, 8, 3, 6, 9], that is So, the matrix A is transposed, 3 GatherLoad instructions are needed to store each column element of the matrix A in the memory into the vector register, and 3 vector Store instructions are needed to store the elements in the vector register back to the memory. But since the matrix A is stored by row in the memory, that is, each column element of the matrix A is not stored continuously in the memory, so the Gather Load is actually also split into 3 scalar Load instructions to obtain a column element of the matrix A. So actually, with the help of the vector register, 9 scalar Load instructions and 3 vector Store instructions are needed. Similarly, if the transpose of an n x n matrix is performed with the help of the vector register, n 2 scalar Load instructions and n vector Store instructions are needed.

[0045] The embodiment of the present application provides a matrix operation method, which can complete matrix transposition with the help of a matrix register in a processor, can reduce the number of instructions required for matrix transposition, and improves the efficiency of matrix transposition. The matrix register is a register capable of storing matrix data in a two-dimensional form distinguishing rows and columns. The processor can provide corresponding reading instructions to read the stored matrix data in the matrix register by column, and the processor also provides corresponding storage instructions to store each column data of the matrix data in the form of row or column to the matrix register, or to store each row data of the matrix data in the form of row or column to the matrix register by column. When the processor reads or stores the matrix data in the matrix register in the form of row or column, the difference between the corresponding reading performance and storage performance can be ignored. In an example, the matrix register can be a scalable matrix unit (SME) corresponding matrix register.

[0046] Figure 3 A computing device structure schematic diagram provided by the embodiment of the present application, at least including a memory and a processor. The memory can be an external memory (such as a hard disk), or a memory storage (such as a memory, a cache). The processor at least includes a matrix register, and the processor can also include a vector register and a scalar register, etc. Figure 3If only a matrix register is included in the processor, the matrix register and the memory can access each other, and data stored in the memory or the cache can be directly written into the matrix register, and data stored in the matrix register can be directly written into the memory or the cache. The processor can be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), a digital signal processor (DSP), or the like.

[0047] Figure 4 is a flowchart of a matrix operation method provided by an embodiment of the present application. The method can be executed by a processor of a computing device to complete matrix transposition by means of a matrix register, reduce the number of instructions required for matrix transposition, and improve the efficiency of matrix transposition. Referring to Figure 3 Figure 4 The method includes the following steps.

[0048] In step 401, the processor stores first matrix data in the matrix register, where the first matrix includes N rows and M columns, and the matrix register stores the first matrix data in a two-dimensional form of N rows and M columns.

[0049] In implementation, an application related to matrix operation, such as an HPC application or an application related to artificial intelligence, can be run in the computing device. When the application needs to transpose a certain matrix during running on the computing device, the application can send a matrix transposition request to the processor to make the processor transposes the corresponding matrix. The matrix operation method provided by an embodiment of the present application can form a function of implementing matrix transposition by means of assembly / intrinsic / high-level language, and serve as a dynamic / static / high-level language acceleration library of matrix operation. When the processor needs to perform matrix transposition, the function of implementing matrix transposition can be called and executed in the function library to implement the matrix operation method provided by an embodiment of the present application, such as the processing of steps 401-402.

[0050] In the embodiment of the present application, the matrix to be transposed can be referred to as a first matrix, and the matrix data corresponding to the first matrix can be referred to as first matrix data. The first matrix data can be stored in an external memory or an internal memory before transposition. The first matrix can include N rows and M columns, where M and N are both positive integers, and the values of M and N can be equal or not equal. In the present application, the matrix operation method is described in detail by taking the first matrix data stored in the memory and the first matrix data being a two-dimensional matrix as an example, and other cases are similar and will not be described in detail. ​

[0051] The first matrix data can be stored in memory either row-wise or column-wise. When the first matrix data is stored in memory row-wise, the processor can read the target matrix from memory row-wise and store each row of elements read in either row or column-wise into the matrix register. When the target matrix is ​​stored in memory column-wise, the processor can read the target matrix from memory column-wise and store each column of elements read in either row or column-wise into the matrix register.

[0052] like Figure 5 As shown, the first matrix is ​​a matrix consisting of 8 rows and 8 columns. Accordingly, the data of the first matrix can be stored in memory row by row as [00,01,02,03,04,05,06,07,10,11,12,…,75,76,77]. The processor can read one row of the first matrix data from memory at a time, such as [00,01,02,03,04,05,06,07], [10,11,12,13,14,15,16,17], etc., and can store each row of the first matrix data read in the matrix register in row form.

[0053] In one example, the first matrix can also be the individual matrices obtained by dividing the large matrix to be transposed. When reading any first matrix data, it can be read from the matrix data corresponding to the stored large matrix. The specific reading process is prior art and will not be described in detail in this application. Correspondingly, after transposing each first matrix, the transposed second matrices can be used to form the matrix after transposing the large matrix.

[0054] Step 402: Read the first matrix data from the matrix register row by row or column by column to obtain the second matrix data after transposing the first matrix data, wherein the second matrix contains M rows and N columns.

[0055] After the first matrix data is stored in the matrix register, it can be read from the matrix register row by row or column by column. Specifically, if each row or column of the first matrix data is stored in the matrix register row by row, it can be read from the matrix register column by column, thus completing the row-column transformation of the first matrix data. If each row or column of the first matrix data is stored in the matrix register column by column, it can be read from the matrix register row by row, thus completing the row-column transformation of the first matrix data, resulting in the transposed second matrix data.

[0056] like Figure 5As shown, for storing the first matrix data into the matrix register, the first matrix data can be read column by column, i.e., [00, 10, 20, 30, 40, 50, 60, 70], [01, 11, 21, 31, 41, 51, 61, 71], …, [07, 17, 27, 37, 47, 57, 67, 77] are read in sequence, to obtain the second matrix data after transposition of the first matrix data.

[0057] In this way, for the first matrix of N rows and M columns, if the corresponding first matrix data is stored in the memory by row, N storage instructions are required to store the first matrix data into the matrix register, and then M read instructions are required to read the first matrix data from the matrix register, to obtain the second matrix data after transposition. If the corresponding first matrix data is stored in the memory by column, M storage instructions are required to store the first matrix data into the matrix register, and then N read instructions are required to read the first matrix data from the matrix register, to obtain the second matrix data after transposition. It can be seen that, by using the matrix operation method provided in the present application, the transposition of the matrix can be completed by only M+N instructions, and the efficiency of the matrix transposition can be improved.

[0058] Figure 5 is a schematic diagram of matrix transposition provided in an embodiment of the present application. As shown in Figure 5 The first matrix is an 8x8 matrix, as shown in The first matrix data can be stored in the memory by row, i.e., the first matrix data is stored in the memory as [00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, …, 75, 76, 77]. When transposing the first matrix data, 8 storage instructions can be used to store each row of elements of the first matrix data in the memory into the matrix register. Then 8 read instructions are used to read each column of elements of the first matrix data stored in the matrix register. Each column of elements can be stored into the memory in the form of a matrix. In this way, the second matrix data after transposition of the first matrix data can be obtained in the memory, which is stored in the memory as [00, 10, 20, 30, 40, 50, 60, 70, 01, 11, 21, …, 57, 67, 77]. That is, the

[0059] In one example, for reading the first matrix data from the matrix register in a row-by-row or column-by-column manner, the data read each time can be stored in the memory to obtain the second matrix data after transposing the first matrix data in the memory. Then the second matrix data after transposing in the memory is input to the calculation unit in the processor for further calculation. In another example, for reading the first matrix data from the matrix register in a row-by-row or column-by-column manner, the data read each time can be directly input to the corresponding calculation unit in the processor for further calculation to improve the calculation efficiency.

[0060] Figure 6 is a schematic diagram of a computing device structure provided by an embodiment of the present application, and the processor of the computing device can further include a vector register. The vector register and the memory have a bidirectional data path, and data can be accessed by each other. The vector register and the matrix register also have a bidirectional data path, and data can be accessed by each other. The matrix register and the memory have a unidirectional data path, that is, the data in the matrix register can be stored to the memory, and the data in the memory needs to be stored to the matrix register by means of the vector register.

[0061] For Figure 6 For the computing device shown in the figure, the processing of step 401 can be replaced by: the processor stores the first matrix data in the form of vector data to the vector register, and then stores the vector data corresponding to the first matrix data stored in the vector register to the matrix register in a row or column manner.

[0062] When the first matrix data is stored in the memory by row, the processor can read the target matrix from the memory by row, and store each row of data read each time as a row vector corresponding to the first matrix to the vector register, so that a plurality of vector memories can store respective row vectors corresponding to the first matrix. Then the row vectors stored in each vector register can be stored in the matrix register by row or by column.

[0063] Figure 7 is a schematic diagram of matrix transposition provided by an embodiment of the present application. As shown in the figure, the first matrix is an 8x8 matrix, and the second matrix is an 8x8 matrix after transposing the first matrix. Figure 7 ​The first matrix data can be stored in the memory by rows, i.e., the first matrix data is stored in the memory as [00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, …, 75, 76, 77]. When transposing the first matrix data, 8 vector load instructions can be used to store each row of elements of the target matrix in the memory to the vector registers. Then 8 store instructions can be used to store the vectors in the vector registers to the matrix registers by rows. Finally, 8 read instructions can be used to read each column of data of the matrix stored in the matrix registers. The read column data can be stored in the memory in the form of a matrix. In this way, the second matrix data after the first matrix data is transposed can be obtained in the memory, and the second matrix data is stored in the memory as [00, 10, 20, 30, 40, 50, 60, 70, 01, 11, 21, …, 57, 67, 77]. That is, the second matrix data is transposed from the first matrix data.

[0064] In the embodiments of the present application, the memory can store data to the matrix register by means of the vector memory. In this way, the number of data channels between the matrix register and the memory can be reduced, the hardware cost of the processor can be reduced, and the number of instructions required for transposing the matrix can not be increased too much, and the efficiency of matrix transposition can be improved.

[0065] Figure 8 is a schematic diagram of a computing device structure provided by the embodiments of the present application, which is the same as the computing device shown in Figure 6 The same as the computing device shown in Figure 6 The difference between the computing device shown in

[0066] For the computing device shown in Figure 8 The processing of the step 402 can be replaced by: reading the first matrix data from the matrix register in a row-by-row or column-by-column manner, and storing each time read vector data to the vector register. Then the vector data stored in the vector register is read to the memory to obtain the second matrix data after the first matrix data is transposed.

[0067] If each row or column of the read first matrix data is stored in the matrix register by row, the first matrix data stored in the matrix register can be read column by column, and each column data (column vector) read each time can be stored in the vector register. Then the column vector stored in each vector register can be stored in the memory in turn. If each row or column of the read first matrix data is stored in the matrix register by column, the first matrix data stored in the matrix register can be read row by row, and each row data (row vector) read each time can be stored in the vector register. Then the row vector stored in each vector register can be stored in the memory in turn.

[0068] Figure 9 is a schematic diagram of matrix transposition provided by an embodiment of the present application. As shown in Figure 9 , the first matrix is an 8x8 matrix, and The first matrix data can be stored in the memory by row, that is, the target matrix is stored in the memory as [00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, …, 75, 76, 77]. When transposing the target matrix, each row of the first matrix data in the memory can be stored in the matrix register by 8 storage instructions. Then the first matrix data stored in the matrix register can be read column by column to the vector register by 8 read instructions. Finally, the vector stored in the vector register can be read to the memory by 8 vector Load instructions. In this way, the second matrix data after transposing the first matrix data can be obtained in the memory, which is stored in the memory as [00, 10, 20, 30, 40, 50, 60, 70, 01, 11, 21, …, 57, 67, 77]. That is, the

[0069] In the embodiment of the present application, the matrix register can store data to the memory by means of the vector memory. In this way, the number of data channels between the matrix register and the memory can be reduced, the hardware cost of the processor can be reduced, and the number of instructions required for transposing the matrix can not be increased too much, and the efficiency of matrix transposition can be improved.

[0070] Figure 10 is a schematic diagram of a computing device structure provided by an embodiment of the present application, which is the same as the computing device shown in Figure 6 and Figure 8 The same as the computing device shown in Figure 6The difference between the shown computing device and the shown computing device is that the matrix register and the memory cannot access each other, that is, if the data stored in the memory needs to be stored in the matrix register, the data in the memory can be first stored in the vector register, and then the data stored in the vector register is stored in the matrix register. Similarly, if the data stored in the memory needs to be stored in the matrix register, the data in the memory can be first stored in the vector register, and then the data stored in the vector register is stored in the matrix register.

[0071] For Figure 10 For the shown computing device, the processing of the above step 401 can be replaced by: the processor stores the first matrix data in the form of vector data in the vector register, and then stores the corresponding vector data of the first matrix data stored in the vector register in the matrix register in the form of row or column. Further processing is the same as the above Figure 6 The corresponding embodiment content is the same, and will not be repeated here.

[0072] The processing of the above step 402 can be replaced by: reading the first matrix data from the matrix register in the form of row or column, and storing each time reading the vector data to the vector register. Then read the vector data stored in the vector register to the memory to obtain the second matrix data after transposing the first matrix data. Further processing can be the same as the above Figure 6 The corresponding embodiment content is the same, and will not be repeated here.

[0073] In the embodiments of the present application, when storing data between the matrix register and the memory, the vector memory can be used. In this way, the data channel between the matrix register and the memory can be avoided, the hardware cost of the processor can be reduced, and the number of instructions required for transposing the matrix can not be increased too much, and the efficiency of matrix transposition can be improved.

[0074] The embodiments of the present application also provide a processor, which includes a matrix register and can also include a vector register. For example, the processor can be the processor shown in the above Figure 3 、 6 , 8, 10. The processor can be used for:

[0075] storing the first matrix data to the matrix register, the first matrix including N rows and M columns, and the matrix register storing the first matrix data in the form of two-dimensional N rows and M columns; reading the first matrix data from the matrix register in the form of row or column to obtain the second matrix data after transposing the first matrix data, and the second matrix including M rows and N columns.

[0076] In an implementable manner, the processor is configured to store the first matrix data stored in the memory into the matrix register in a row-by-row or column-by-column manner.

[0077] In an implementable manner, the processor further comprises a vector register, and the processor is configured to store the first matrix data into the vector register in the form of vector data. The vector data corresponding to the first matrix data stored in the vector register is stored into the matrix register in a row or column manner.

[0078] In an implementable manner, the processor is configured to read the first matrix data from the matrix register in a row-by-row or column-by-column manner, and store each read into the vector register in the form of vector data. The vector data stored in the vector register is read into the memory to obtain second matrix data after transposition of the first matrix data.

[0079] In an implementable manner, the processor further comprises a vector register, and the processor is configured to read the first matrix data from the matrix register in a row-by-row or column-by-column manner, and store each read into the vector register in the form of vector data. The vector data stored in the vector register is read into the memory to obtain second matrix data after transposition of the first matrix data.

[0080] In an implementable manner, the processor further comprises a calculation unit, and the processor is further configured to input the second matrix data into the calculation unit, and perform a specified calculation on the second matrix data by the calculation unit.

[0081] The processor provided by the embodiments of the present application can perform the matrix operation method described in the above embodiments to realize matrix transposition. The specific implementation manner can be referred to the content of the above embodiments, and will not be described here. The processor provided by the embodiments of the present application realizes matrix transposition through the matrix register, which can reduce the number of instructions required for matrix transposition, and can improve the efficiency of matrix transposition.

[0082] The embodiments of the present application further provide a computer program product comprising instructions. The computer program product can be software or a program product comprising instructions, which can run on a computing device or be stored in any available medium. When the computer program product runs on the computing device provided by the above embodiments, the computing device performs the matrix operation method provided by the above embodiments.

[0083] The embodiment of the present application further provides a computer readable storage medium. The computer readable storage medium can be any available medium or data storage device that can be used to store instructions that can be executed by a computing device, or a data center containing one or more available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk), etc. The computer readable storage medium comprises instructions for instructing the computing device to execute the matrix operation method provided by the above embodiment.

[0084] In the present application, the terms "first", "second" and the like are used to distinguish between similar or identical items or elements having substantially the same function, and it should be understood that there is no logical or chronological dependency between "first" and "second", and the number and execution order are not limited. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. In the present application, the term "at least one" means one or more, and the term "multiple" means two or more.

[0085] The above description is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any skilled person in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A matrix data processing method characterized by, The method comprises: The processor stores first matrix data stored in the memory in the form of vector data to a vector register, and stores corresponding vector data of the first matrix data stored in the vector register in the form of rows or columns to a matrix register, the first matrix data comprising N rows and M columns, the matrix register comprising N rows and M columns, and the N rows and M columns of the first matrix data being stored in the N rows and M columns of the matrix register, the vector register and the matrix register being located in the processor, and the matrix register being a register capable of storing matrix data in a two-dimensional form capable of distinguishing rows and columns; The processor reads the first matrix data from the matrix register in the form of rows or columns, and inputs each time read data to a calculation unit included in the processor for calculation, wherein the data input to the calculation unit is second matrix data after transposition of the first matrix data, and the second matrix data comprises M rows and N columns.

2. A processor, comprising: The processor comprises a matrix register, a vector register and a calculation unit, and is configured to: store first matrix data stored in the memory in the form of vector data to the vector register, and store corresponding vector data of the first matrix data stored in the vector register in the form of rows or columns to the matrix register, the first matrix data comprising N rows and M columns, the matrix register comprising N rows and M columns, and the N rows and M columns of the first matrix data being stored in the N rows and M columns of the matrix register, the matrix register being a register capable of storing matrix data in a two-dimensional form capable of distinguishing rows and columns; read the first matrix data from the matrix register in the form of rows or columns, and input each time read data to the calculation unit for calculation, wherein the data input to the calculation unit is second matrix data after transposition of the first matrix data, and the second matrix data comprises M rows and N columns.

3. A computing device, comprising: The calculation device comprises a memory and a processor, the processor comprises a matrix register, and the processor is configured to execute instructions stored in the memory, so that the processor performs the method of claim 1.

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