Antifuse structure, antifuse array, operation method thereof, and memory

Abstract

The embodiments of the present disclosure provide an antifuse structure, an antifuse array, an operation method thereof, and a memory, wherein the antifuse structure includes: a substrate, and a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure located on the surface of an active area of ​​the substrate; the active area is an axisymmetric structure, and the axis of symmetry of the active area extends along a first direction; the size of the active area in the first direction gradually decreases away from the axis of symmetry along a second direction; the size of the second gate structure in the first direction is larger than the size of the first gate structure in the first direction; the size of the third gate structure in the first direction is larger than the size of the fourth gate structure in the first direction; the first direction is any direction in the plane where the substrate is located, and the second direction and the first direction are located in the same plane and are perpendicular to each other.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and is related to but not limited to an antifuse structure, an antifuse array, an operation method thereof, and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) chips typically have redundant memory cells. These redundant cells can replace defective memory cells in the DRAM chip to repair the DRAM. Repairing DRAM chips often requires the use of one-time programming devices, such as antifuses.

[0003] An antifuse cell typically consists of an antifuse device, a select transistor, and a bit line. During programming, a high voltage is applied to the programming gate of the antifuse device, a low voltage is applied to the bit line, and the select transistor is turned on. The high voltage difference between the programming gate and the bit line causes the gate oxide layer of the programming gate to break down, completing the programming operation. With the rapid development of integrated circuit technology and the continuous reduction in chip size, the area of ​​the antifuse cell must also be reduced to save valuable space in the memory array. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an antifuse structure, an antifuse array, an operating method thereof, and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides an antifuse structure, comprising:

[0006] A substrate; the substrate includes an active region; the active region has an axisymmetric structure, and the axis of symmetry of the active region extends along a first direction; the size of the active region in the first direction gradually decreases as it moves away from the axis of symmetry along a second direction; the active region includes a first doped region, a second doped region, and a third doped region sequentially arranged along the second direction;

[0007] a first gate structure, located at least on a surface of the active region on a side of the first doping region away from the second doping region;

[0008] a second gate structure located on a surface of the active region between the first doping region and the second doping region;

[0009] a third gate structure located on a surface of the active region between the second doping region and the third doping region;

[0010] a fourth gate structure, located at least on a surface of the active region on a side of the third doping region away from the second doping region;

[0011] Wherein, the size of the second gate structure in the first direction is larger than the size of the first gate structure in the first direction; the size of the third gate structure in the first direction is larger than the size of the fourth gate structure in the first direction;

[0012] The first direction is any direction in the plane where the substrate is located, and the second direction and the first direction are located in the same plane and are perpendicular to each other.

[0013] The first gate structure covers a first corner of the active area, and a vertex angle corresponding to the first corner is an acute angle or a right angle;

[0014] The fourth gate structure covers a second corner of the active region, the second corner is opposite to the first corner, and a vertex angle corresponding to the second corner is an acute angle or a right angle.

[0015] In some embodiments, the substrate further includes a shallow trench isolation structure located between the active regions;

[0016] The first gate structure further extends into the shallow trench isolation structure along a third direction and is located on a sidewall of the first corner;

[0017] The fourth gate structure further extends into the shallow trench isolation structure along the third direction and is located on a sidewall of the second corner.

[0018] In some embodiments, a size of the first gate structure in the second direction is smaller than a size of the second gate structure in the second direction;

[0019] A size of the fourth gate structure in the second direction is smaller than a size of the third gate structure in the second direction.

[0020] In some embodiments, the antifuse structure is an axisymmetric structure, a first symmetry axis of the antifuse structure extends along the first direction, and a second symmetry axis of the antifuse structure extends along the second direction.

[0021] In some embodiments, the first gate structure includes a first gate dielectric layer located on the active region and a first gate conductive layer located on the first gate dielectric layer;

[0022] The second gate structure includes a second gate dielectric layer located on the active area and a second gate conductive layer located on the second gate dielectric layer;

[0023] The third gate structure includes a third gate dielectric layer located on the active area and a third gate conductive layer located on the third gate dielectric layer;

[0024] The fourth gate structure includes a fourth gate dielectric layer located on the active region and a fourth gate conductive layer located on the fourth gate dielectric layer.

[0025] In some embodiments, the antifuse structure further comprises:

[0026] a first connecting structure and a first conductive line; the first connecting structure is connected between the second doped region and the first conductive line;

[0027] a second conductive line electrically connected to the second gate structure;

[0028] a third conductive line electrically connected to the first gate structure;

[0029] a fourth conductive line electrically connected to the third gate structure;

[0030] A fifth conductive line is electrically connected to the fourth gate structure.

[0031] In a second aspect, an embodiment of the present disclosure provides an antifuse array, comprising a plurality of antifuse structures as described in the first aspect; wherein:

[0032] A plurality of the antifuse structures are arranged in an array along the second direction and the first direction;

[0033] A plurality of the antifuse structures arranged along the first direction constitute a row of the antifuse structures, and two adjacent rows of the antifuse structures along the second direction are arranged in a staggered manner;

[0034] Two adjacent rows of anti-fuse structures arranged along the second direction share the first gate structure or the fourth gate structure.

[0035] In some embodiments, in two adjacent rows of antifuse structures arranged along the first direction, the active regions of two antifuse structures close to each other in the second direction partially overlap in projection areas on any straight line extending along the second direction.

[0036] In some embodiments, it further includes:

[0037] A plurality of the antifuse structures arranged along the second direction constitute a column of the antifuse structures, and two adjacent columns of the antifuse structures along the first direction are arranged in a staggered manner;

[0038] The first conductive line extends along the second direction, and each column of the antifuse structures shares one first conductive line.

[0039] In some embodiments, the second conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same second conductive line;

[0040] The third conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same third conductive line;

[0041] The fourth conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same fourth conductive line;

[0042] The fifth conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same fifth conductive line; wherein the second conductive line, the third conductive line, and the fourth conductive line are all located in the same layer.

[0043] In some embodiments, further comprising: a second connecting structure, a third connecting structure, a fourth connecting structure, a fifth connecting structure, and a sixth connecting structure;

[0044] Wherein, the second connecting structure is used to connect the first gate structure and the third conductive line;

[0045] The third connecting structure is used to connect the second gate structure and the second conductive line;

[0046] The fourth connecting structure is used to connect the third gate structure and the fourth conductive line;

[0047] The fifth connecting structure is used to connect the fourth gate structure and the fifth conductive line;

[0048] The sixth connecting structure is used to connect the first connecting structure and the first conductive line.

[0049] In a third aspect, embodiments of the present disclosure provide an operating method for an antifuse structure, which is applied to the antifuse structure described in the first aspect, wherein the first gate structure and the active region below the first gate structure constitute a first programming device, the fourth gate structure and the active region below the fourth gate structure constitute a second programming device; the second gate structure, the first doped region, and the second doped region constitute a first switching device, and the third gate structure, the second doped region, and the third doped region constitute a second switching device; the method comprises:

[0050] During a programming operation, a first voltage is applied to the first conductive line, a second voltage is applied to the second conductive line, and a third voltage is applied to the third conductive line to break down the first programming device; or the first voltage is applied to the first conductive line, a fourth voltage is applied to the fourth conductive line, and a fifth voltage is applied to the fifth conductive line to break down the second programming device;

[0051] During a read operation, a sixth voltage is applied to the third conductive line, the second voltage is applied to the second conductive line, and the current flows into the first conductive line to read data from the first programming device; or a seventh voltage is applied to the fifth conductive line, the fourth voltage is applied to the fourth conductive line, and the current flows into the first conductive line to read data from the second programming device;

[0052] Among them, the third voltage is greater than or equal to the breakdown voltage of the first programming device and less than the breakdown voltage of the first switching device, the fifth voltage is greater than or equal to the breakdown voltage of the second programming device and less than the breakdown voltage of the second switching device; the second voltage is greater than or equal to the turn-on voltage of the first switching device, and the fourth voltage is greater than or equal to the turn-on voltage of the second switching device; the sixth voltage and the seventh voltage are both greater than the first voltage, and the first voltage is zero voltage or ground voltage.

[0053] In a fourth aspect, embodiments of the present disclosure provide an antifuse array operating method, which is applied to the antifuse array described in the second aspect; wherein the antifuse array includes a plurality of antifuse structures, each antifuse structure including a first programming device and a second programming device; the first gate structure and an active region located below the first gate structure constitute the first programming device, and the fourth gate structure and an active region located below the fourth gate structure constitute the second programming device; the method includes:

[0054] During a programming operation, an eighth voltage is applied to the third conductive line or the fifth conductive line corresponding to a programming device to be programmed, a ninth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be programmed, and a first voltage is applied to the first conductive line corresponding to the programming device to be programmed, so as to breakdown the programming device to be programmed; at the same time, a tenth voltage is applied to the other first conductive lines in the antifuse array so as to prevent other programming devices except the programming device to be programmed from being broken down; the programming device to be programmed is any one of the plurality of first programming devices or the plurality of second programming devices;

[0055] During a read operation, an eleventh voltage is applied to the third conductive line or the fifth conductive line corresponding to the programming device to be read, the ninth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be read, and the first voltage is applied to the first conductive line corresponding to the programming device to be read, so that data in the programming device to be programmed is read by a current flowing into the first conductive line. Simultaneously, the first voltage is applied to the other first conductive lines in the antifuse array, and the second conductive line, the third conductive line, the fourth conductive line, and the fifth conductive line in the antifuse array are left floating or are applied with the first voltage.

[0056] Among them, the eighth voltage is greater than or equal to the breakdown voltage of the programming device to be programmed, and is less than the breakdown voltage of the switching device corresponding to the programming device to be programmed; the ninth voltage is greater than or equal to the turn-on voltage of the switching device corresponding to the programming device to be programmed; the tenth voltage and the eleventh voltage are greater than the first voltage and less than the eighth voltage; the difference between the eighth voltage and the tenth voltage is less than the breakdown voltage of the programming device to be programmed; the first voltage is zero voltage or ground voltage.

[0057] In a fifth aspect, an embodiment of the present disclosure provides a memory comprising the antifuse array as described in the second aspect.

[0058] The present disclosure provides an antifuse structure, an antifuse array, an operating method thereof, and a memory, wherein the antifuse structure includes an active region, and a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure located on the active region; the active region is axially symmetrical, and the axis of symmetry of the active region extends along a first direction; the size of the active region in the first direction gradually decreases away from the axis of symmetry along a second direction; the second gate structure, together with the first doped region and the second doped region, constitutes a first switching device, and the third gate structure, together with the second doped region and the third doped region, constitutes a second switching device. Since the size of the active region in the first direction gradually decreases away from the axis of symmetry along the second direction, while being consistent with the width of the active region of the switching device in the related art, the width of the active region corresponding to the first switching device and the second switching device in the present disclosure can be made smaller, thereby reducing the area of ​​the active region and the area of ​​the antifuse structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0060] Figure 1 Schematic diagram of the structure of an antifuse array;

[0061] Figure 2 A schematic diagram of the layout structure of an antifuse structure;

[0062] Figure 3 A schematic diagram of the local structure of an antifuse array;

[0063] Figure 4 A schematic diagram of a layout structure of an antifuse structure provided in an embodiment of the present disclosure Figure 1 ;

[0064] Figure 5 A schematic diagram of a layout structure of an antifuse structure provided in an embodiment of the present disclosure Figure 2 ;

[0065] Figure 6 A cross-sectional view of an antifuse structure provided in an embodiment of the present disclosure Figure 1 ;

[0066] Figure 7 A cross-sectional view of an antifuse structure provided in an embodiment of the present disclosure Figure 2 ;

[0067] Figure 8 A schematic diagram of a layout structure of an antifuse structure provided in an embodiment of the present disclosure Figure 3 ;

[0068] Figure 9 A schematic diagram of the structure of an antifuse array provided in an embodiment of the present disclosure Figure 1 ;

[0069] Figure 10 A schematic diagram of the structure of an antifuse array provided in an embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0070] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0071] In the following description, numerous details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0072] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0073] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0074] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0075] The antifuse structure is a one-time programmable (OTP) device. Once the antifuse structure is programmed, the stored data is permanent. Due to this feature, the antifuse structure is widely used in memories such as DRAM.

[0076] Figure 1FIG. 1 is a structural diagram of an antifuse array, such as Figure 1 As shown, the antifuse array 100 includes a plurality of antifuse structures 100a arranged in a spaced relationship. The plurality of antifuse structures 100a are spaced apart along a first direction (i.e., the X-axis direction shown in the figure). In the antifuse array 100, all antifuse devices in the same row share the same programming conductor FG and the same word line XG. Therefore, when writing to a particular antifuse device, both the programming conductor FG and the word line XG must be turned on simultaneously. For antifuse devices in the same row that do not require high-voltage writing, a certain positive voltage must be applied to the corresponding bit line (BL) 109 to prevent other antifuse devices from being accidentally broken down.

[0077] Figure 2 is a schematic diagram of a layout structure of an antifuse structure 100a, such as Figure 2 As shown, the antifuse structure 100a includes a first antifuse unit 11 and a second antifuse unit 12. The first antifuse unit 11 includes a first gate 101, a first source / drain region 102, a second gate 103, and a second source / drain region 104. The first gate 101 and the active region 13 located below the first gate 101 constitute a first antifuse device, and the first source / drain region 102, the second gate 103, and the second source / drain region 104 constitute a first select transistor. The second antifuse unit 12 includes a third gate 105, a second source / drain region 104, a third source / drain region 106, and a fourth gate 107. The fourth gate 107 and the active region 13 located below the fourth gate 107 constitute a second antifuse device, and the second source / drain region 104, the third gate 105, and the third source / drain region 106 constitute a second select transistor. The first and second select transistors share the second source / drain region 104, and a bit line connection structure 108 electrically connects the second source / drain region 104 to a bit line 109. For the anti-fuse structure 100a, when writing, a high voltage (for example, about 5 to 5.5 volts) is applied to the first gate 101 of the first anti-fuse device, 0V is set at the corresponding BL terminal, and the first selection transistor is turned on, so that the thin gate oxide of the first anti-fuse device is broken down under the high voltage and the resistance is significantly reduced, thereby achieving the purpose of writing; or, when writing, a high voltage (for example, about 5 to 5.5 volts) is applied to the fourth gate 107 of the second anti-fuse device, 0V is set at the corresponding BL terminal, and the second selection transistor is turned on, so that the thin gate oxide of the second anti-fuse device is broken down under the high voltage and the resistance is significantly reduced, thereby achieving the purpose of writing.

[0078] Please continue to refer to Figure 1 and Figure 2The first gate 101, the second gate 103, the third gate 105 and the fourth gate 107 in the anti-fuse structure 100a are arranged in sequence along the second direction (i.e., the Y-axis direction shown in the figure), so that the length of the anti-fuse structure 100a is longer, thereby making the area of ​​the anti-fuse array 100 including multiple anti-fuse structures 100a larger.

[0079] Also, please continue to refer to Figure 2 When the width of the first selection transistor or the second selection transistor (i.e., the dimension along the X-axis direction) is small, the voltage division of the channel of the first selection transistor or the second selection transistor increases, so that the voltage difference across the corresponding first anti-fuse device or the second anti-fuse device becomes smaller, weakening the energy used to break down the gate oxide in the first anti-fuse device or the second anti-fuse device, resulting in the first anti-fuse device or the second anti-fuse device being difficult to write. Therefore, the first selection transistor or the second selection transistor needs to have a larger width, which limits the reduction of the area of ​​the anti-fuse structure 100a.

[0080] Figure 3 is a partial structural diagram of the antifuse array 100, refer to Figure 3 Typically, an anti-fuse doping region 301 is provided in the substrate below the first and second anti-fuse devices. Due to the extremely high doping concentration of the anti-fuse doping region 301, the doping ions in the anti-fuse doping region 301 may diffuse to the vicinity of the channel doping region 302 of the first and second selection transistors during the high-temperature process, thereby reducing the turn-on voltage of the first and second selection transistors and increasing the risk of leakage. Therefore, the distance A between the first gate 101 and the second gate 103 and the distance C between the third gate 105 and the fourth gate 107 must be maintained at a large distance, for example, significantly larger than the distance B between the second gate 103 and the third gate 105. This makes it difficult to further reduce the length of the anti-fuse structure 100a.

[0081] Based on this, embodiments of the present disclosure provide an antifuse structure, an antifuse array, an operating method thereof, and a memory, wherein the antifuse structure includes an active region, and a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure located on the active region; the active region is axially symmetrical, and the axis of symmetry of the active region extends along a first direction; the size of the active region in the first direction gradually decreases as it moves away from the axis of symmetry along a second direction; wherein the second gate structure, together with the first and second doped regions, constitutes a first switching device, and the third gate structure, together with the second and third doped regions, constitutes a second switching device. Since the size of the active region in the first direction gradually decreases as it moves away from the axis of symmetry along the second direction, while being consistent with the width of the active region of the switching device in the related art, the width of the active region corresponding to the first switching device and the second switching device in the embodiments of the present disclosure can be made smaller, thereby reducing the area of ​​the active region and the area of ​​the antifuse structure.

[0082] The antifuse structure and the antifuse array in the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0083] Before introducing the embodiments of the present disclosure, the three directions that may be used to describe the three-dimensional structure in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis and Z-axis directions. The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction intersecting (for example, perpendicular) with the top surface and the bottom surface of the substrate is defined as the third direction. In the directions of the top surface and the bottom surface of the substrate (that is, the plane where the substrate is located), two directions intersecting (for example, perpendicular to each other) are defined. For example, the direction in which the active area extends can be defined as the first direction, and the plane direction of the substrate can be determined based on the first direction and the second direction. In the embodiment of the present disclosure, the first direction, the second direction and the third direction may be perpendicular to each other. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular. In the embodiment of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

[0084] The embodiment of the present disclosure provides an anti-fuse structure 200. Figure 4 and Figure 5 A schematic diagram of the structure of the antifuse structure 200 provided in an embodiment of the present disclosure is shown in FIG. Figure 4 and Figure 5 As shown, the antifuse structure 200 includes:

[0085] The substrate includes an active region 20; the active region 20 has an axisymmetric structure, with the axis of symmetry of the active region 20 extending along the X-axis; the size of the active region 20 in the X-axis direction gradually decreases as it moves away from the axis of symmetry along the Y-axis; the active region 20 includes a first doped region 201, a second doped region 202, and a third doped region 203 sequentially spaced along the Y-axis;

[0086] A first gate structure 204 is located at least on the surface of the active region 20 on a side of the first doping region 201 away from the second doping region 202 ;

[0087] The second gate structure 205 is located on the surface of the active region 20 between the first doping region 201 and the second doping region 202 ;

[0088] A third gate structure 206 is located on the surface of the active region 20 between the second doping region 202 and the third doping region 203 ;

[0089] a fourth gate structure 207 , at least located on the surface of the active region 20 on a side of the third doping region 203 away from the second doping region 202 ;

[0090] The size of the second gate structure 205 in the X-axis direction is larger than that of the first gate structure 204 in the X-axis direction; the size of the third gate structure 206 in the X-axis direction is larger than that of the fourth gate structure 207 in the X-axis direction.

[0091] In this disclosure, please continue to refer to Figure 4 and Figure 5 The anti-fuse structure 200 includes a first anti-fuse unit and a second anti-fuse unit arranged along the Y-axis direction, and the first anti-fuse unit and the second anti-fuse unit share a second doped region 202 .

[0092] Furthermore, the first antifuse unit includes a first programming device and a first switching device; the first gate structure 204 and the active region 20 located below the first gate structure 204 form the first programming device; the second gate structure 205 and the first doped region 201 and the second doped region 202 located on both sides of the second gate structure 205 form a first switching device (switching transistor). The second antifuse unit includes a second programming device and a second switching device; the fourth gate structure 207 and the active region 20 located below the fourth gate structure 207 form a second programming device; and the third gate structure 206 and the second doped region 202 and the third doped region 203 located on both sides of the third gate structure 206 form a second switching device (switching transistor).

[0093] Please continue to refer to Figure 4 and Figure 5The first switching device and the second switching device share the second doped region 202; the second doped region 202 can serve as one of the source region or the drain region of the first switching device and the second switching device, the first doped region 201 can serve as the other of the source region or the drain region of the first switching device, and the third doped region 203 can serve as the other of the source region or the drain region of the second switching device.

[0094] It should be noted that the active area 20 in the embodiment of the present disclosure is an axisymmetric structure with the axis of symmetry extending along the X-axis direction, and the size of the active area 20 in the X-axis direction gradually decreases as it moves away from the axis of symmetry along the Y-axis direction. In other words, the active area 20 in the present application can be regarded as a square active area in the related art rotated at an acute angle to form a diamond shape. In this way, the hypotenuse of the active area 20 can be used as the width of the first switching device and the second switching device. Since the length of the hypotenuse is necessarily greater than the length of any right-angled side, in the same manner as the first switching device, the second switching device can be connected to the active area 20. Figures 1 to 3 When the width of the switching devices in the circuit is consistent, the side length of the active region of the entire anti-fuse structure can be reduced, thereby reducing the area of ​​the active region of the entire anti-fuse structure, and further reducing the area of ​​the anti-fuse structure.

[0095] In addition, the antifuse structure provided by the embodiment of the present disclosure is Figure 3 In comparison, there is no need to set the anti-fuse doping region 301, thereby reducing the number of masks and lowering the chip manufacturing cost.

[0096] In some embodiments, please refer to Figure 5 The first gate structure 204 covers the first corner A of the active region 20 (eg Figure 5 The fourth gate structure 207 covers the second corner B of the active region 20 (as shown in the dotted box at the top of the figure). Figure 5 As shown in the dotted box at the bottom, the second corner B is opposite to the first corner A, and the vertex angle corresponding to the second corner B is an acute angle or a right angle.

[0097] It should be noted that the first corner A may have a rounded chamfer, and the vertex angle corresponding to the first corner A may be the angle between the extension lines of the two straight sides forming the rounded chamfer. The second corner B may have a rounded chamfer, and the vertex angle corresponding to the second corner B may be the angle between the extension lines of the two straight sides forming the rounded chamfer.

[0098] In some embodiments, see Figures 5 to 7 ,in, Figure 6 and Figure 7 They are Figure 5The substrate further includes a shallow trench isolation structure 21 for defining the active area 20. The first gate structure 204 further extends into the shallow trench isolation structure 21 along the Z-axis and is located on the sidewall of the first corner A. The fourth gate structure 207 further extends into the shallow trench isolation structure 21 along the Z-axis and is located on the sidewall of the second corner B.

[0099] It should be noted that the active region 20 has a plurality of first corners A and second corners B from bottom to top along the Z-axis direction, the first gate structure 204 only covers a portion of the first corners A from top to bottom along the Z-axis direction, and the fourth gate structure 207 only covers a portion of the second corners B from top to bottom along the Z-axis direction. In other words, the first gate structure 204 and the fourth gate structure 207 extend into a portion of the thickness of the shallow trench isolation structure 21 along the Z-axis direction.

[0100] In the embodiment of the present disclosure, by setting the first gate structure 204 and the fourth gate structure 207 to cover the first corner A and the second corner B of the active area 20 along the Z-axis direction, a turning point (i.e., the vertex of the first corner A) can be present in the area where the first gate structure 204 covers the active area 20, and a turning point (i.e., the vertex of the second corner B) can be present in the area where the fourth gate structure 207 covers the active area 20. In this way, the breakdown points of the first gate structure 204 and the fourth gate structure 207 can be controlled near the vertex of the first corner A and the vertex of the second corner B, respectively. In this way, the resistance stability of the first programming device and the second programming device after breakdown can be made higher, and will not affect subsequent reading operations.

[0101] In some embodiments, see Figure 4 The Y-axis dimension d1 of the first gate structure 204 is smaller than the Y-axis dimension d2 of the second gate structure 205; and the Y-axis dimension d4 of the fourth gate structure 207 is smaller than the Y-axis dimension d3 of the third gate structure 206. This reduces the breakdown point range when the first and fourth gate structures 204 and 207 are broken down, improving the resistance stability of the first and second programming devices after breakdown, thereby preventing subsequent read operations from being affected.

[0102] In some embodiments, the antifuse structure 200 is an axisymmetric structure. A first axis of symmetry of the antifuse structure 200 extends along the X-axis, and a second axis of symmetry of the antifuse structure extends along the Y-axis.

[0103] In this way, on the one hand, the pattern of the layout of the anti-fuse structure 200 is made more uniform, which is conducive to further reducing the difficulty of actual process production; on the other hand, the performance of the two anti-fuse units in the anti-fuse structure 200 is made closer, so that when programming and reading the two anti-fuse units, consistent voltages can be applied to the corresponding wires, simplifying the operation method.

[0104] In some embodiments, the first gate structure 204 includes a first gate dielectric layer located on the active area 20 and a first gate conductive layer located on the first gate dielectric layer; the second gate structure 205 includes a second gate dielectric layer located on the active area 20 and a second gate conductive layer located on the second gate dielectric layer; the third gate structure 206 includes a third gate dielectric layer located on the active area 20 and a third gate conductive layer located on the third gate dielectric layer; and the fourth gate structure 207 includes a fourth gate dielectric layer located on the active area 20 and a fourth gate conductive layer located on the fourth gate dielectric layer.

[0105] In the embodiment of the present disclosure, the materials of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer can be silicon oxide or other suitable materials; the materials of the first gate conductive layer, the second gate conductive layer, the third gate conductive layer and the fourth gate conductive layer can be any material with good conductivity, such as any one or more combinations of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), copper (Cu), and polycrystalline silicon.

[0106] It should be noted that the size of the first gate dielectric layer in the Z-axis direction is smaller than the size of the second gate dielectric layer in the Z-axis direction, and the size of the fourth gate dielectric layer in the Z-axis direction is smaller than the size of the third gate dielectric layer in the Z-axis direction. This not only reduces the energy required to break down the first and second programming devices, but also prevents the switching devices corresponding to the programming devices from breaking down and causing failure of the switching devices.

[0107] In some embodiments, the second gate dielectric layer and the third gate dielectric layer can have equal thickness in the Z-axis direction, thereby allowing them to be formed in a single process, simplifying the process and making the performance of the first switching device and the second switching device more similar. The first gate dielectric layer and the fourth gate dielectric layer can also have equal thickness in the Z-axis direction, thereby allowing them to be formed in a single process, simplifying the process and making the performance of the first programming device and the second programming device more similar.

[0108] In some embodiments, see Figure 4 、 Figure 5 and Figure 8 The anti-fuse structure 200 further includes: a first connection structure 40 and a first conductive line 306 (eg Figure 8As shown); the first connection structure 40 is connected between the second doped region 202 and the first conductive line 306; wherein the first connection structure 40 includes a conductive plug 401 and a conductive pad 402.

[0109] It should be noted that the first connection structure 40 may be formed in the interlayer dielectric layer, and the first connection structure 40 is formed of any suitable conductive material, such as tungsten, titanium nitride or polysilicon.

[0110] In some embodiments, see Figure 8 The anti-fuse structure 200 further includes: a second conductive line 302 electrically connected to the second gate structure 205; a third conductive line 303 electrically connected to the first gate structure 204; a fourth conductive line 304 electrically connected to the third gate structure 206; and a fifth conductive line 305 electrically connected to the fourth gate structure 207.

[0111] It should also be noted that the second conductive line 302 being electrically connected to the second gate structure 205 means that the second conductive line 302 is connected to the second gate conductive layer in the second gate structure 205, so that the corresponding first switching device can be turned on by applying a voltage to the second conductive line 302. The fourth conductive line 304 being electrically connected to the third gate structure 206 means that the fourth conductive line 304 is connected to the third gate conductive layer in the third gate structure 206, so that the corresponding second switching device can be turned on by applying a voltage to the fourth conductive line 304. The third conductive line 303 being electrically connected to the first gate structure 204 means that the third conductive line 303 is connected to the first gate conductive layer in the first gate structure 204, so that a programming voltage or a reading voltage can be applied through the third conductive line 303 during programming or reading operations on the first programming device. The fifth conductive line 305 is electrically connected to the fourth gate structure 207, which means that the fifth conductive line 305 is connected to the fourth gate conductive layer in the fourth gate structure 207, so that a programming voltage or a reading voltage can be applied through the fifth conductive line 305 when programming or reading the second programming device.

[0112] It can be understood that the second conductive line 302 and the fourth conductive line 304 and the corresponding gate conductive layer, and the third conductive line 303 and the fifth conductive line 305 and the corresponding gate conductive layer can be electrically connected through contact plugs.

[0113] It should also be noted that the second conductive line 302, the third conductive line 303, the fourth conductive line 304 and the fifth conductive line 305 are located in the same layer, so that in actual process, they can be formed by patterning the same conductive material layer, which simplifies the process and reduces the number of layers of the interconnect structure.

[0114] In some embodiments, the material of the first conductive line 301, the second conductive line 302, the third conductive line 303, the fourth conductive line 304 and the fifth conductive line 305 can be any material with good conductivity, for example, any one or more combinations of titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium, and copper.

[0115] In another embodiment of the present disclosure, please refer to Figure 9 and Figure 10 , which shows a schematic structural diagram of the antifuse array provided by an embodiment of the present disclosure. Figure 9 and Figure 10 As shown, the antifuse array 300 includes a plurality of antifuse structures 200 as in the aforementioned embodiment; wherein the plurality of antifuse structures 200 are arranged in an array along the X-axis direction and the Y-axis direction;

[0116] A plurality of antifuse structures 200 arranged along the X-axis direction constitute a row of antifuse structures, and two adjacent rows of antifuse structures along the Y-axis direction are arranged in a staggered manner;

[0117] Two adjacent rows of anti-fuse structures arranged along the Y-axis direction share the first gate structure 204 or the fourth gate structure 207 .

[0118] In the present disclosure, continue to refer to Figure 9 and Figure 10 The fourth gate structure 207 of the first row of anti-fuse structures 200 arranged along the Y-axis direction is shared with the fourth gate structure 207 of the second adjacent row of anti-fuse structures 200. The first gate structure 204 of the second row of anti-fuse structures 200 arranged along the Y-axis direction is shared with the first gate structure 204 of the third adjacent row of anti-fuse structures 200. Similarly, two adjacent rows of anti-fuse structures arranged along the Y-axis cyclically share the first gate structure 204 and the fourth gate structure 207. In this way, in two adjacent rows of anti-fuse structures arranged along the X-axis direction, two programming devices that are close to each other in the Y-axis direction can share the same programming wire FG, and thus, a programming voltage or a read voltage can be applied to the two programming devices simultaneously through the same programming wire FG.

[0119] In addition, in two adjacent rows of antifuse structures arranged along the X-axis, since the two antifuse structures 200 close to each other in the Y-axis direction share the first gate structure 204 or the fourth gate structure 207 , the area of ​​the antifuse array 300 can be further reduced.

[0120] In the disclosed embodiment, the gate conductive layers (i.e., second gate conductive layers) of the multiple first switching devices in the multiple antifuse structures 200 arranged along the X-axis are interconnected. This allows the multiple first switching devices in the same row to be turned on or off via a single control terminal. The gate conductive layers (i.e., third gate conductive layers) of the multiple second switching devices in the multiple antifuse structures 200 arranged along the X-axis are interconnected, allowing the multiple second switching devices in the same row to be turned on or off via a single control terminal. The gate conductive layers (i.e., first gate conductive layers) of the multiple first programming devices in the multiple antifuse structures 200 arranged along the X-axis are interconnected, allowing a programming voltage or a read voltage to be applied to the multiple first programming devices in the same row. The gate conductive layers (i.e., fourth gate conductive layers) of the multiple second programming devices in the multiple antifuse structures 200 arranged along the X-axis are interconnected, allowing a programming voltage or a read voltage to be applied to the multiple second programming devices in the same row.

[0121] In some embodiments, see Figure 10 In two adjacent rows of antifuse structures arranged along the X-axis direction, the active regions 20 of the two antifuse structures 200 close to each other in the Y-axis direction partially overlap in their projected areas on any straight line extending along the Y-axis direction (or in a plane perpendicular to the X-axis direction and the substrate) (e.g. Figure 10 This can further reduce the area of ​​the active region 20, thereby reducing the area of ​​a single antifuse structure and the area of ​​the antifuse array.

[0122] In some embodiments, see Figure 9 and Figure 10 A plurality of antifuse structures 200 arranged along the Y-axis constitute a column of antifuse structures, and two adjacent columns of antifuse structures 200 along the X-axis are arranged in a staggered manner. The first conductive line 306 extends along the Y-axis, and each column of antifuse structures 200 shares a first conductive line 306 .

[0123] It can be understood that the first conductive line 306 can serve as the bit line BL of the antifuse array 300 .

[0124] In some embodiments, see Figure 9 and Figure 10The second conductive line 302 extends along the X-axis direction, and a row of anti-fuse structures 200 arranged along the X-axis direction is connected to the same second conductive line 302; the third conductive line 303 extends along the X-axis direction, and a row of anti-fuse structures 200 arranged along the X-axis direction is connected to the same third conductive line 303; the fourth conductive line extends along the X-axis direction, and a row of anti-fuse structures 200 arranged along the X-axis direction is connected to the same fourth conductive line 304; the fifth conductive line 305 extends along the X-axis direction, and a row of anti-fuse structures 200 arranged along the X-axis direction is connected to the same fifth conductive line 305; wherein the second conductive line 302, the third conductive line 303, and the fourth conductive line 304 are all located in the same layer as the first conductive line 301.

[0125] It should be noted that the second conductive line 302 leads out the gate conductive layer interconnecting the multiple first switching devices in the same row. By applying a voltage to the second conductive line 302, the multiple first switching devices in the same row can be turned on or off. The fourth conductive line 304 leads out the gate conductive layer interconnecting the multiple second switching devices in the same row. By applying a voltage to the fourth conductive line 304, the multiple second switching devices in the same row can be turned on or off. The third conductive line 303 leads out the gate conductive layer interconnecting the multiple first programming devices in the same row. It can apply a programming voltage or a read voltage to the multiple first programming devices in the same row. The fifth conductive line 305 leads out the gate conductive layer interconnecting the multiple second programming devices in the same row. It can apply a programming voltage or a read voltage to the multiple second programming devices in the same row.

[0126] In the embodiments of the present disclosure, reference Figure 9 and Figure 10 The active areas of adjacent antifuse structures 200 can be separated by shallow trench isolation structures (not shown). Multiple antifuse structures 200 in the same row are spaced the same distance apart along the X-axis. Multiple antifuse structures 200 in the same column are spaced the same distance apart along the Y-axis. This allows for a uniform layout of the antifuse array 300, effectively utilizing the layout area and reducing the complexity of the antifuse array 300 manufacturing process. Since the length and area of ​​the antifuse structures 200 are reduced, the area of ​​the antifuse array 300 is effectively reduced.

[0127] It should be noted that Figure 9 and Figure 10 Only four antifuse structures 200 are shown in the antifuse array 300 in FIG. 1 . In actual implementation, the antifuse array 300 may include multiple rows and multiple columns formed by multiple antifuse structures 200 .

[0128] In some cases, please continue to participate Figure 9 and Figure 10The antifuse array 300 also includes: a second connection structure 209, a third connection structure 210, a fourth connection structure 211, a fifth connection structure 212 and a sixth connection structure 213; wherein the second connection structure 209 is used to connect the first gate structure 204 and the third conductive line 303; the third connection structure 210 is used to connect the second gate structure 205 and the second conductive line 302; the fourth connection structure 211 is used to connect the third gate structure 206 and the fourth conductive line 304; the fifth connection structure 212 is used to connect the fourth gate structure 207 and the fifth conductive line 305; the sixth connection structure 213 is used to connect the first connection structure 40 and the first conductive line 306.

[0129] It should be noted that the second connection structure 209 , the third connection structure 210 , the fourth connection structure 211 , and the fifth connection structure 212 are located on the same layer; and the sixth connection structure 213 is located on an upper layer of the first connection structure 40 .

[0130] It should be noted that the second connection structure 209 , the third connection structure 210 , the fourth connection structure 211 , the fifth connection structure 212 and the sixth connection structure 213 are all contact plugs, and the contact plugs may be located in the interlayer dielectric layer.

[0131] The antifuse structure 200 in the antifuse array 300 provided in the embodiment of the present disclosure is similar to the antifuse structure 200 in the above embodiment. For technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0132] Another embodiment of the present disclosure further provides an operating method of an antifuse structure, which is applicable to the aforementioned embodiment. Figures 4 to 8 The anti-fuse structure 200 is shown. The first gate structure and the active region below the first gate structure constitute a first programming device, the fourth gate structure and the active region below the fourth gate structure constitute a second programming device; the second gate structure and the first and second doped regions constitute a first switching device, and the third gate structure and the second and third doped regions constitute a second switching device. The operating method of the anti-fuse structure 200 includes:

[0133] During a programming operation, a first voltage is applied to the first conductive line, a second voltage is applied to the second conductive line, and a third voltage is applied to the third conductive line to break down the first programming device; or, a first voltage is applied to the first conductive line, a fourth voltage is applied to the fourth conductive line, and a fifth voltage is applied to the fifth conductive line to break down the second programming device.

[0134] In an embodiment of the present disclosure, the first voltage is zero voltage or ground voltage. When programming the first programming device, the second voltage is greater than or equal to the turn-on voltage of the first switching device, so that the first switching device can be turned on at the second voltage. The difference between the third voltage and the first voltage is greater than or equal to the breakdown voltage of the first programming device and less than the breakdown voltage of the first switching device, so that the first programming device can be broken down at the third voltage without breaking down the first switching device. Here, the third voltage can range from 5 to 5.5V, for example, 5.1V, 5.3V, or 5.4V. When programming the second programming device, the fourth voltage is greater than or equal to the turn-on voltage of the second switching device, so that the second switching device can be turned on at the fourth voltage. The difference between the fifth voltage and the first voltage is greater than or equal to the breakdown voltage of the second programming device and less than the breakdown voltage of the second switching device, so that the second programming device can be broken down at the fifth voltage without breaking down the second switching device. Here, the fifth voltage can range from 5 to 5.5V, for example, 5.1V, 5.3V, or 5.4V.

[0135] It should be noted that during the programming operation, the voltages of programming devices and corresponding switching devices that do not require programming are set to zero voltage or ground voltage. For example, when programming the first programming device, zero voltage or ground voltage is applied to the fourth conductive line 304 and the fifth conductive line 305. For another example, when programming the second programming device, zero voltage or ground voltage is applied to the second conductive line 302 and the third conductive line 303.

[0136] During a read operation, a sixth voltage is applied to the third conductive line, a second voltage is applied to the second conductive line, and data in the first programming device is read by a current flowing into the first conductive line; alternatively, a seventh voltage is applied to the fifth conductive line, a fourth voltage is applied to the fourth conductive line, and data in the second programming device is read by a current flowing into the first conductive line; wherein the sixth voltage and the seventh voltage are both greater than the first voltage, and the first voltage is zero voltage or ground voltage.

[0137] It should be noted that when reading the first programming device, the difference between the sixth voltage and the first voltage is less than the breakdown voltage of the first programming device. For example, the sixth voltage may be 1 V. When reading the second programming device, the difference between the seventh voltage and the first voltage is less than the breakdown voltage of the second programming device. For example, the seventh voltage may be 1 V.

[0138] Another embodiment of the present disclosure further provides an operation method of an antifuse array, which is applied to the aforementioned embodiment. Figure 9 and Figure 10 The antifuse array 300 is shown. Figure 9 and Figure 10The antifuse array includes a plurality of antifuse structures 200, each antifuse structure 200 including a first programming device and a second programming device; the first gate structure and the active region below the first gate structure constitute the first programming device, and the fourth gate structure and the active region below the fourth gate structure constitute the second programming device. The operating method of the antifuse array includes:

[0139] During the programming operation, an eighth voltage is applied to the third conductive line or the fifth conductive line corresponding to the programming device to be programmed, a ninth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be programmed, and a first voltage is applied to the first conductive line corresponding to the programming device to be programmed, so as to break down the programming device to be programmed; at the same time, a tenth voltage is applied to the other first conductive lines in the anti-fuse array, so that other programming devices except the programming device to be programmed are not broken down.

[0140] It should be noted that the programming device to be programmed is any one of the multiple first programming devices or the multiple second programming devices.

[0141] In the embodiment of the present disclosure, the first voltage is zero voltage or ground voltage, the eighth voltage is greater than or equal to the breakdown voltage of the programming device to be programmed, and less than the breakdown voltage of the switching device corresponding to the programming device to be programmed, so that the programming device to be programmed can be broken down at the eighth voltage without breaking down the switching device corresponding thereto. Here, the eighth voltage can range from 5 to 5.5V, for example, 5.1V, 5.3V, or 5.4V. The ninth voltage is greater than or equal to the turn-on voltage of the switching device corresponding to the programming device to be programmed, so that the switching device corresponding to the programming device to be programmed can be turned on at the ninth voltage. The tenth voltage is greater than the first voltage, and the difference between the tenth voltage and the first voltage is less than the breakdown voltage of the programming device to be programmed. For example, the tenth voltage can be 1V.

[0142] During a reading operation, an eleventh voltage is applied to the third conductive line or the fifth conductive line corresponding to the programming device to be read, a ninth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be read, and a first voltage is applied to the first conductive line corresponding to the programming device to be read. The current flowing into the first conductive line is used to read the data in the programming device to be programmed. At the same time, the first voltage is applied to the other first conductive lines in the antifuse array, and the other second conductive lines, third conductive lines, fourth conductive lines and fifth conductive lines in the antifuse array are suspended or applied with the first voltage; wherein the first voltage is zero voltage or ground voltage.

[0143] It should be noted that the eleventh voltage is greater than the first voltage, and the difference between the eleventh voltage and the first voltage is less than the breakdown voltage of the programming device to be programmed. For example, the eleventh voltage may be 1V.

[0144] The operating method of the antifuse array 300 provided in the embodiment of the present disclosure is similar to the operating method of the antifuse structure 200 in the above embodiment. For technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0145] Another embodiment of the present disclosure further provides a memory, comprising the antifuse array 300 in any of the aforementioned embodiments (refer to Figure 9 and Figure 10 ), the antifuse array 300 includes the antifuse structure 200 in any of the aforementioned embodiments (refer to Figures 4 to 8 );

[0146] In which, the antifuse array 300 includes multiple antifuse structures 200 as in the aforementioned embodiments; wherein, the multiple antifuse structures 200 are arranged in an array along the X-axis direction and the Y-axis direction; the multiple antifuse structures 200 arranged along the X-axis direction constitute a row of antifuse structures, and the two adjacent rows of antifuse structures along the Y-axis direction are arranged in an staggered manner; the two adjacent rows of antifuse structures arranged along the Y-axis direction share the first gate structure 204 or the fourth gate structure 207.

[0147] The antifuse structure 200 includes: a substrate; the substrate includes an active region 20; the active region 20 is an axisymmetric structure, and the symmetry axis of the active region 20 extends along the X-axis; the size of the active region 20 in the X-axis direction gradually decreases as it moves away from the symmetry axis along the Y-axis; the active region 20 includes a first doping region 201, a second doping region 202, and a third doping region 203 arranged in sequence along the Y-axis; a first gate structure 204 is located at least on the surface of the active region 20 on a side of the first doping region 201 away from the second doping region 202; a second gate structure 205 is located on the first doping region 201, and the second gate structure 205 is located on the first doping region 202. The surface of the active area 20 between the second doping region 201 and the second doping region 202; the third gate structure 206 is located on the surface of the active area 20 between the second doping region 202 and the third doping region 203; the fourth gate structure 207 is located on the surface of the active area 20 at least on the side of the third doping region 203 away from the second doping region 202; wherein the size of the second gate structure 205 in the X-axis direction is larger than the size of the first gate structure 204 in the X-axis direction; the size of the third gate structure 206 in the X-axis direction is larger than the size of the fourth gate structure 207 in the X-axis direction.

[0148] In some embodiments, the memory may include but is not limited to random access memory (RAM), such as dynamic random access memory (DRAM).

[0149] In the disclosed embodiment, the memory includes the aforementioned antifuse array 300 . Since the aforementioned antifuse array 300 has a relatively small area, the integration of the memory can be improved, thereby effectively increasing the storage capacity of the memory and improving its performance.

[0150] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in non-targeted ways. The structural embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0151] The features disclosed in several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0152] The above are only some embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An antifuse structure, characterized in that: include: A substrate; the substrate includes an active area; the active area has an axisymmetric structure, and the axis of symmetry of the active area extends along a first direction; As the active region moves away from the symmetry axis along the second direction, the size of the active region in the first direction gradually decreases; the active region includes a first doping region, a second doping region, and a third doping region that are sequentially arranged along the second direction; a first gate structure, located at least on a surface of the active region on a side of the first doping region away from the second doping region; a second gate structure located on a surface of the active region between the first doping region and the second doping region; a third gate structure located on a surface of the active region between the second doping region and the third doping region; a fourth gate structure, located at least on a surface of the active region on a side of the third doping region away from the second doping region; Wherein, the size of the second gate structure in the first direction is larger than the size of the first gate structure in the first direction; the size of the third gate structure in the first direction is larger than the size of the fourth gate structure in the first direction; The first direction is any direction in the plane where the substrate is located, and the second direction and the first direction are located in the same plane and are perpendicular to each other.

2. The antifuse structure according to claim 1, wherein: The first gate structure covers a first corner of the active area, and a vertex angle corresponding to the first corner is an acute angle or a right angle; The fourth gate structure covers a second corner of the active region, the second corner is opposite to the first corner, and a vertex angle corresponding to the second corner is an acute angle or a right angle.

3. The antifuse structure according to claim 2, wherein: The substrate further includes a shallow trench isolation structure located between the active areas; The first gate structure further extends into the shallow trench isolation structure along a third direction and is located on a sidewall of the first corner; The fourth gate structure further extends into the shallow trench isolation structure along the third direction and is located on a sidewall of the second corner.

4. The antifuse structure according to any one of claims 1 to 3, wherein: The size of the first gate structure in the second direction is smaller than the size of the second gate structure in the second direction; A size of the fourth gate structure in the second direction is smaller than a size of the third gate structure in the second direction.

5. The antifuse structure according to claim 4, wherein: The antifuse structure is an axisymmetric structure, a first symmetry axis of the antifuse structure extends along the first direction, and a second symmetry axis of the antifuse structure extends along the second direction.

6. The antifuse structure according to claim 5, wherein: The first gate structure includes a first gate dielectric layer located on the active area and a first gate conductive layer located on the first gate dielectric layer; The second gate structure includes a second gate dielectric layer located on the active area and a second gate conductive layer located on the second gate dielectric layer; The third gate structure includes a third gate dielectric layer located on the active area and a third gate conductive layer located on the third gate dielectric layer; The fourth gate structure includes a fourth gate dielectric layer located on the active region and a fourth gate conductive layer located on the fourth gate dielectric layer.

7. The antifuse structure according to claim 6, wherein: The antifuse structure further includes: a first connecting structure and a first conductive line; the first connecting structure is connected between the second doped region and the first conductive line; a second conductive line electrically connected to the second gate structure; a third conductive line electrically connected to the first gate structure; a fourth conductive line electrically connected to the third gate structure; A fifth conductive line is electrically connected to the fourth gate structure.

8. An antifuse array, characterized in that: comprising a plurality of antifuse structures as claimed in claim 7; wherein: A plurality of the antifuse structures are arranged in an array along the second direction and the first direction; A plurality of the antifuse structures arranged along the first direction constitute a row of the antifuse structures, and two adjacent rows of the antifuse structures along the second direction are arranged in a staggered manner; Two adjacent rows of anti-fuse structures arranged along the second direction share the first gate structure or the fourth gate structure.

9. The antifuse array according to claim 8, wherein: In two adjacent rows of antifuse structures arranged along the first direction, projection areas of the active regions of two antifuse structures close to each other in the second direction on any straight line extending along the second direction partially overlap.

10. The antifuse array according to claim 8 or 9, wherein: A plurality of the antifuse structures arranged along the second direction constitute a column of the antifuse structures, and two adjacent columns of the antifuse structures along the first direction are arranged in a staggered manner; The first conductive line extends along the second direction, and each column of the antifuse structures shares one first conductive line.

11. The antifuse array according to claim 10, wherein: The second conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same second conductive line; The third conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same third conductive line; The fourth conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same fourth conductive line; The fifth conductive line extends along the first direction, and a row of the antifuse structures arranged along the first direction is connected to the same fifth conductive line; wherein the second conductive line, the third conductive line, and the fourth conductive line are all located in the same layer.

12. The antifuse array according to claim 11, wherein: Also includes: a second connecting structure, a third connecting structure, a fourth connecting structure, a fifth connecting structure, and a sixth connecting structure; Wherein, the second connecting structure is used to connect the first gate structure and the third conductive line; The third connecting structure is used to connect the second gate structure and the second conductive line; The fourth connecting structure is used to connect the third gate structure and the fourth conductive line; The fifth connecting structure is used to connect the fourth gate structure and the fifth conductive line; The sixth connecting structure is used to connect the first connecting structure and the first conductive line.

13. A method for operating an antifuse structure, characterized in that: The antifuse structure according to claim 7, wherein the first gate structure and the active region located below the first gate structure constitute a first programming device, the fourth gate structure and the active region located below the fourth gate structure constitute a second programming device; the second gate structure, the first doped region, and the second doped region constitute a first switching device, and the third gate structure, the second doped region, and the third doped region constitute a second switching device; and the method comprises: During a programming operation, a first voltage is applied to the first conductive line, a second voltage is applied to the second conductive line, and a third voltage is applied to the third conductive line to break down the first programming device; or the first voltage is applied to the first conductive line, a fourth voltage is applied to the fourth conductive line, and a fifth voltage is applied to the fifth conductive line to break down the second programming device; During a read operation, a sixth voltage is applied to the third conductive line, the second voltage is applied to the second conductive line, and the current flows into the first conductive line to read data from the first programming device; or a seventh voltage is applied to the fifth conductive line, the fourth voltage is applied to the fourth conductive line, and the current flows into the first conductive line to read data from the second programming device; Among them, the third voltage is greater than or equal to the breakdown voltage of the first programming device and less than the breakdown voltage of the first switching device, the fifth voltage is greater than or equal to the breakdown voltage of the second programming device and less than the breakdown voltage of the second switching device; the second voltage is greater than or equal to the turn-on voltage of the first switching device, and the fourth voltage is greater than or equal to the turn-on voltage of the second switching device; the sixth voltage and the seventh voltage are both greater than the first voltage, and the first voltage is zero voltage or ground voltage.

14. A method for operating an antifuse array, characterized in that: The antifuse array according to any one of claims 10 to 12, wherein the antifuse array comprises a plurality of antifuse structures, each antifuse structure comprising a first programming device and a second programming device; the first gate structure and an active region located below the first gate structure constitute the first programming device, and the fourth gate structure and an active region located below the fourth gate structure constitute the second programming device; the method comprising: During a programming operation, an eighth voltage is applied to the third conductive line or the fifth conductive line corresponding to a programming device to be programmed, a ninth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be programmed, and a first voltage is applied to the first conductive line corresponding to the programming device to be programmed, so as to breakdown the programming device to be programmed; at the same time, a tenth voltage is applied to the other first conductive lines in the antifuse array so as to prevent other programming devices except the programming device to be programmed from being broken down; the programming device to be programmed is any one of the plurality of first programming devices or the plurality of second programming devices; During a read operation, an eleventh voltage is applied to the third conductive line or the fifth conductive line corresponding to the programming device to be read, the ninth voltage is applied to the second conductive line or the fourth conductive line corresponding to the programming device to be read, and the first voltage is applied to the first conductive line corresponding to the programming device to be read, so that data in the programming device to be programmed is read by a current flowing into the first conductive line. Simultaneously, the first voltage is applied to the other first conductive lines in the antifuse array, and the second conductive line, the third conductive line, the fourth conductive line, and the fifth conductive line in the antifuse array are left floating or are applied with the first voltage. Among them, the eighth voltage is greater than or equal to the breakdown voltage of the programming device to be programmed, and is less than the breakdown voltage of the switching device corresponding to the programming device to be programmed; the ninth voltage is greater than or equal to the turn-on voltage of the switching device corresponding to the programming device to be programmed; the tenth voltage and the eleventh voltage are greater than the first voltage and less than the eighth voltage; the difference between the eighth voltage and the tenth voltage is less than the breakdown voltage of the programming device to be programmed; the first voltage is zero voltage or ground voltage.

15. A memory, characterized in that: The antifuse array comprises the antifuse array as claimed in any one of claims 8 to 12.

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