A method for monitoring hybrid bonded microzone stress

Abstract

The application provides a method for monitoring hybrid bonding micro-area stress. The method comprises the following steps: providing two base chips; forming a hybrid bonding metal medium structure on a bonding surface of each of the two base chips; manufacturing a metal structure in the metal medium structure into a stress characterization structure to obtain two target base chips; hybrid bonding the two target base chips; monitoring the deformation of the stress characterization structure after bonding; and obtaining the stress of the hybrid bonding micro-area of the two target base chips according to the deformation of the stress characterization structure. In the application, the metal structure in the metal medium structure for hybrid bonding is manufactured into a stress characterization structure, and the stress of the hybrid bonding micro-area can be monitored in situ through the deformation of the stress characterization structure after the two target chips are hybrid bonded, thereby solving the problem that the hybrid bonding micro-area stress is difficult to monitor in situ and online, and realizing online monitoring of the hybrid bonding micro-area stress change.

Description

A method for monitoring stress in hybrid bonded microregions Technical Field

[0001] This application relates to the field of hybrid bonding technology, and more specifically to a method for monitoring stress in hybrid bonded micro-regions. Background Technology

[0002] With Moore's Law slowing down, multi-chip integration is an important method to improve chip performance. Hybrid bonding is an important technology for realizing multi-chip integration, which can achieve high-density fine-pitch integration. However, stress problems will exist in the metal interconnect structure and its surroundings during the integration process. This is mainly because the thermal expansion coefficients of the metal, the surrounding medium, and silicon are different. Residual stress will be formed in the process, especially in the annealing process, and stress problems caused by damage will accompany the entire process. Therefore, it is very important to monitor the stress changes caused by the process in real time. However, it is currently difficult to measure the stress in the metal interconnect structure and its surroundings in situ. Although Raman and X-ray diffraction (XRD) methods can be used to measure it, the spatial resolution of the measurement is limited, and these methods rely on optical measurement, which is difficult to penetrate the three-dimensional integrated structure.

[0003] Therefore, given the difficulty in in-situ online monitoring of stress in hybrid bonded microregions, it is crucial to develop a testing method that can monitor stress in hybrid bonded microregions in situ. Summary of the Invention

[0004] The purpose of this application is to provide a method for monitoring stress in hybrid bonded microregions, in order to solve the problem that it is difficult to monitor stress in hybrid bonded microregions in situ online.

[0005] This application provides a method for monitoring stress in hybrid bonded microregions, comprising:

[0006] Two basic chips are provided;

[0007] Hybrid bonding metal dielectric structures are formed on the bonding surfaces of the two base chips respectively;

[0008] The metal structure in the aforementioned metal dielectric structure is fabricated into a stress characterization structure to obtain two target base chips;

[0009] The two target base chips are hybrid bonded, and stress is monitored to characterize the deformation of the structure after bonding.

[0010] The stress in the hybrid bonding microregion of the two target base chips is obtained based on the deformation of the stress characterization structure.

[0011] In some embodiments of this application, a metal dielectric structure for hybrid bonding is formed on the base chip, including:

[0012] A metal dielectric structure for hybrid bonding is formed on the base chip using a damascus process.

[0013] In some embodiments of this application, the formation of a metal dielectric structure for hybrid bonding on the base chip using a damascus process includes:

[0014] A dielectric layer is formed on the base chip;

[0015] The dielectric layer is patterned to form a dielectric structure;

[0016] A metal structure is formed in the dielectric structure using the damascus process, resulting in a metal dielectric structure.

[0017] In some embodiments of this application, the metal structure in the metal dielectric structure is fabricated as a stress characterization structure, including:

[0018] The middle part of the metal structure is etched to form a groove in the metal structure, and the metal structure with the groove is used as a stress characterization structure.

[0019] In some embodiments of this application, the opening shape of the groove is circular or square.

[0020] In some embodiments of this application, the dielectric structure in the metal dielectric structure is a rectangular groove, a square groove, or a circular groove.

[0021] In some embodiments of this application, the dielectric structure is made of silicon dioxide or silicon carbonitride.

[0022] In some embodiments of this application, the metal structure in the metal dielectric structure is made of copper, twinned copper, tungsten, or ruthenium.

[0023] In some embodiments of this application, the base chip is a single-crystal silicon chip.

[0024] In some embodiments of this application, the base chip is a 4-inch, 6-inch, 8-inch, or 12-inch uncut wafer or a cut chip.

[0025] Compared to existing technologies, the method for monitoring stress in hybrid-bonded microregions provided in this application includes: providing two base chips; forming hybrid-bonded metal-dielectric structures on the two base chips respectively; fabricating a stress characterization structure from the metal structure within the metal-dielectric structure to obtain two target base chips; hybrid-bonding the two target base chips, and monitoring the deformation of the stress characterization structure after bonding; and obtaining the stress in the hybrid-bonded microregion of the two target base chips based on the deformation of the stress characterization structure. In this application, the metal structure within the metal-dielectric structure used for hybrid bonding is fabricated as a stress characterization structure. After the two target chips are hybrid-bonded, the stress in the hybrid-bonded microregion can be monitored in situ by the deformation of the stress characterization structure, thereby solving the problem of difficulty in in-situ online monitoring of stress in hybrid-bonded microregions and enabling online monitoring of stress changes in hybrid-bonded microregions. Attached Figure Description

[0026] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0027] Figure 1 shows a flowchart of the method for stress characterization of hybrid bonded microregions provided in this application;

[0028] Figures 2A to 2E illustrate the formation of the metallic dielectric structure and the hybrid bonding process provided in this application;

[0029] Figure label:

[0030] Basic chip 101; dielectric structure 102; metal structure 103. Detailed Implementation

[0031] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0032] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application pertains.

[0033] Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to those processes, methods, products, or apparatuses.

[0034] To further illustrate the solutions of the embodiments of this application, a description will be provided below in conjunction with the accompanying drawings. It is understood that identical or corresponding content in the following embodiments can be referred to mutually; for the sake of simplicity, further elaboration will not be repeated hereafter.

[0035] This application provides a method for monitoring stress in hybrid bonded microregions, which will be described below with reference to the accompanying drawings.

[0036] Figure 1 shows a flowchart of the method for monitoring stress in hybrid bonding microregions provided in this application; Figures 2A to 2E show schematic diagrams of the formation of the metallic dielectric structure and the hybrid bonding process provided in this application.

[0037] As shown in Figure 1, this application provides a method for stress characterization of hybrid bonded microregions, comprising the following steps:

[0038] S1. Provides two basic chips 101;

[0039] Figure 2A shows a cross-sectional schematic diagram of the base chip 101 provided in an embodiment of this application. The base chip 101 can be an uncut complete wafer to be hybrid bonded, such as a 4-inch, 6-inch, 8-inch, or 12-inch wafer, or it can be a chip that has already been cut. Specifically, the base chip 101 can be a single-crystal silicon chip, or it can be a chip made of various substrate materials integrated using hybrid bonding technology.

[0040] S2. A hybrid bonding metal dielectric structure is formed on the bonding surfaces of the two base chips 101 respectively;

[0041] The metallic dielectric structure includes dielectric structure 102 and metallic structure 103.

[0042] Figure 2B shows a cross-sectional view after the dielectric structure is formed on the base chip. Referring to Figure 2B, the dielectric structure 102 is formed on the base chip 101. Specifically, a dielectric layer can be formed on the base chip 101 first, and then the dielectric layer can be patterned to form the dielectric structure 102. The grooves in the dielectric structure 102 are used to form a metal structure. Specifically, the dielectric structure 102 can be a rectangular groove, a square groove, or a circular groove, etc. The material used to fabricate the dielectric structure 102 can be silicon dioxide (SiO2) or silicon carbonitride (SiCN), etc., materials used for mixed bonding dielectric structures.

[0043] Figure 2C shows a cross-sectional view of the metal structure formed in the groove of the dielectric structure. Referring to Figure 2C, a metal structure 103 is formed in the groove of the dielectric structure 102. The upper surface of the metal structure 103 is lower than the upper surface of the dielectric structure 102 to facilitate subsequent hybrid bonding processes. As shown in Figure 2E, during the hybrid bonding process, the upper and lower metal structures fuse together due to thermal expansion. Specifically, the material used to fabricate the metal structure 103 can be copper, twinned copper, tungsten, or ruthenium, etc.

[0044] In some embodiments, step S2 above, which forms a metal dielectric structure for hybrid bonding on the base chip 101, can specifically be implemented by: forming a metal dielectric structure for hybrid bonding on the base chip 101 using a damascus process, specifically including the following steps:

[0045] A dielectric layer is formed on the base chip 101;

[0046] The dielectric layer is patterned to form a dielectric structure 102;

[0047] A metal structure 103 is formed in the dielectric structure 102 using the damascus process, resulting in a metal dielectric structure.

[0048] S3. The metal structure in the metal dielectric structure is fabricated into a stress characterization structure to obtain two target base chips;

[0049] Figure 2D shows a cross-sectional view of the metal structure after it has been fabricated into a stress characterization structure. Referring to Figures 2C and 2D, specifically, the middle portion of the metal structure 103 can be etched to form a groove within the metal structure 103. The metal structure with this groove serves as the stress characterization structure. The opening shape of the groove is circular or square, and the bottom of the groove can expose the dielectric layer.

[0050] In some embodiments, the groove of the metal structure can be made into a hemispherical shape, and the two metal structures can be bonded together to form a spherical cavity; alternatively, the groove of the metal structure can be made into a cube, and the two metal structures can be bonded together to form a cubic cavity.

[0051] S4. The two target base chips are hybridized and bonded, and the stress characterization structure is monitored after bonding.

[0052] S5. The stress of the two target base chip hybrid bonding microregions is obtained based on the deformation of the stress characterization structure.

[0053] For example, the equivalent thermal expansion coefficient and equivalent Young's modulus can be calculated based on the deformation of the stress-characterized structure.

[0054] Figure 2E shows a cross-sectional view of the two chips after hybrid bonding. Referring to Figure 2E, the two target chips shown in Figure 2D are hybrid bonded. After grinding, activation, and bonding processes, a stress characterization structure is formed in the hybrid bonding micro-region. Specifically, the morphological changes of the stress characterization structure before and after hybrid bonding can be observed using an electron microscope. The stress in the hybrid bonding micro-region can then be determined based on the deformation of the stress characterization structure, thus enabling stress measurement. Multiple measurements can be taken in subsequent processes to monitor the stress in the hybrid bonding micro-region.

[0055] For ease of understanding, this application also provides the following measurement procedure for the stress in hybrid bonded micro-regions:

[0056] S11 provides the basic chip 101.

[0057] S12. The dielectric structure 102 and the metal structure 103 with mixed bonding requirements are formed by the Damascus process.

[0058] S13. The metal structure 103 is patterned by etching process to form a stress characterization structure.

[0059] S14. The two basic chips 101 described above are subjected to a hybrid bonding process to form a stress characterization structure with cavities of various shapes such as rectangles, squares or spheres between the two metal structures 103. Finally, the morphological changes of the cavities of the stress characterization structure after bonding are observed by electron microscopy to achieve quantitative characterization of the stress caused by the hybrid bonding process.

[0060] The method for monitoring stress in hybrid-bonded microregions provided in this application includes: providing two base chips; forming hybrid-bonded metal-dielectric structures on the two base chips respectively; fabricating a stress characterization structure from the metal structure in the metal-dielectric structure to obtain two target base chips; hybrid-bonding the two target base chips, and monitoring the deformation of the stress characterization structure after bonding; and obtaining the stress in the hybrid-bonded microregion of the two target base chips based on the deformation of the stress characterization structure. In this application, the metal structure in the metal-dielectric structure used for hybrid bonding is fabricated as a stress characterization structure. After the two chips are hybrid-bonded, the stress in the hybrid-bonded microregion can be monitored in situ by the deformation of the stress characterization structure, thereby solving the problem that it is difficult to monitor the stress in the hybrid-bonded microregion in situ online, and enabling online monitoring of stress changes in the hybrid-bonded microregion.

[0061] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0062] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0063] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0064] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0065] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0066] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure. Different parts of different embodiments can be combined with each other without conflict, and these should all be covered within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for monitoring stress in hybrid bonded microregions, characterized in that, include: Two basic chips are provided; Hybrid bonding metal dielectric structures are formed on the bonding surfaces of two base chips, respectively. The formation of the metal dielectric structure for hybrid bonding on the base chips includes: forming a dielectric layer on the base chips; patterning the dielectric layer to form a dielectric structure; forming a metal structure within the dielectric structure using a damascus process to obtain a metal dielectric structure; fabricating the metal structure within the metal dielectric structure into a stress characterization structure to obtain two target base chips. Fabricating the metal structure within the metal dielectric structure into a stress characterization structure includes: etching the middle portion of the metal structure to form a groove within the metal structure, using the metal structure with the groove as the stress characterization structure; hybrid bonding the two target base chips, and monitoring the deformation of the stress characterization structure after bonding; obtaining the stress in the hybrid bonding micro-region of the two target base chips based on the deformation of the stress characterization structure.

2. The method for monitoring stress in hybrid bonded microregions according to claim 1, characterized in that, The opening shape of the groove is circular or square.

3. The method for monitoring stress in hybrid bonded microregions according to claim 1, characterized in that, The dielectric structure in the metal dielectric structure is a rectangular groove, a square groove, or a circular groove.

4. The method for monitoring stress in hybrid bonded microregions according to claim 3, characterized in that, The dielectric structure is made of silicon dioxide or silicon carbonitride.

5. The method for monitoring stress in hybrid bonded microregions according to claim 1, characterized in that, The metal structure in the aforementioned metal dielectric structure is made of copper, twinned copper, tungsten, or ruthenium.

6. The method for monitoring stress in hybrid bonded microregions according to claim 1, characterized in that, The base chip is a single-crystal silicon chip.

7. The method for monitoring stress in hybrid bonded microregions according to claim 1, characterized in that, The base chip is an uncut 4-inch, 6-inch, 8-inch, or 12-inch wafer or a cut chip.

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