MOS device and method for manufacturing the same

Abstract

The present application discloses a MOS device and a preparation method thereof, wherein the MOS device comprises: each source region structure comprises a first source region structure and a second source region structure, wherein the first source region structure is located on the side of the epitaxial layer away from the substrate, the second source region structure is located on the side of the epitaxial layer away from the substrate, and the surface of the first source region structure on the side away from the substrate is located in the surface of the second source region structure close to the substrate; the bottom surface and the first side surface of the gate structure are respectively in contact with the source region structure; a plurality of rectifying structures, wherein the rectifying structures are at least partially located in the epitaxial layer, the rectifying structures are in contact with the source region structure, and the rectifying structures have a doping type different from that of the epitaxial layer, wherein the plurality of rectifying structures are spaced apart in a first direction, and the first direction is parallel to the first side surface. This is to solve the problems of increased size and poor reliability caused by the use of external reverse-parallel diodes in MOS devices in related technologies, and the inability to meet the endurance requirements of devices with different withstand voltages.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a MOS device and a method for preparing the same. Background Art

[0002] SiC MOSFET mainly acts as an electronic switch in power electronic systems. When the MOSFET is in the off state, there will be a reverse leakage current between the drain and the source. If a diode is not added in reverse parallel, this leakage current may cause damage to other devices in the circuit. In addition, when SiC MOSFET is used for rectification of AC circuits, since MOSFET can only be turned on under forward voltage, an anti-parallel diode is required to provide a conduction channel under reverse voltage to achieve current rectification. Therefore, in the prior art, a diode is often integrated in reverse parallel outside the SiC MOSFET body to improve the performance of the SiC MOSFET body diode, thereby improving the working efficiency of the SiC MOSFET. However, the external anti-parallel diode will increase the occupied space of the circuit, increase the packaging cost of the device, and introduce parasitic capacitance and parasitic inductance, resulting in problems such as slow response speed of the reverse diode and poor reliability.

[0003] For SiC MOSFET power devices with different withstand voltages, diodes with different freewheeling capabilities need to be connected in parallel to protect the normal use of the device. For example, a 1200V 13mΩ MOSFET device requires a stronger endurance than a 650V 40mΩ MOSFET device. This results in a larger proportion of the freewheeling diode of the 1200V 13mΩ MOSFET device in the actual cell, which requires sacrificing the performance of the cell itself, resulting in an increase in on-resistance and a decrease in withstand voltage performance. Summary of the invention

[0004] The present application provides a MOS device and a method for preparing the same, in order to solve the problems in the related art of using an external reverse-parallel diode in the MOS device, which leads to increased size and poor reliability, and the inability to meet the endurance requirements of devices with different withstand voltages.

[0005] According to one aspect of the present application, a MOS device is provided, comprising: a substrate; an epitaxial layer, the epitaxial layer being located on one side of the substrate; at least one source region structure, each of the source region structures comprising a first source region structure and a second source region structure, the first source region structure being located on a side of the epitaxial layer away from the substrate, the second source region structure being located on a side of the epitaxial layer away from the substrate, and a surface of the first source region structure on a side away from the substrate being located in a surface of the second source region structure on a side close to the substrate; at least one gate structure, the gate structure being located on a side of the epitaxial layer away from the substrate, and a bottom surface and a first side surface of the gate structure being in contact with the source region structure, respectively; a plurality of rectifying structures, the rectifying structures being located on a side of the epitaxial layer away from the substrate, and the rectifying structures being at least partially located in the epitaxial layer, the rectifying structures being in contact with the source region structure, and the rectifying structures having a doping type different from that of the epitaxial layer, wherein the plurality of rectifying structures are spaced apart in a first direction, and the first direction is parallel to the first side surface.

[0006] Optionally, the rectifying structure is located on a side of the first source region structure away from the second source region structure, and the rectifying structure is located on a side of the second source region structure away from the first source region structure.

[0007] Optionally, each of the source region structures and the gate structure in contact with the first source region structure and the second source region structure in the source region structure constitute a first structure, and the rectifying structure and the first structure are alternately arranged in the first direction, wherein the rectifying structure is in contact with the first source region structure, the second source region structure and the gate structure on both sides in the second direction, respectively, and the second direction is the direction from the first source region structure to the second source region structure.

[0008] Optionally, each of the source region structures and the gate structure in contact with the first source region structure and the second source region structure in the source region structures constitute a first structure, the epitaxial layer has a first epitaxial region located on the side of the first structure in the first direction, and the epitaxial layer has a second epitaxial region located on the side of the first structure in the second direction, wherein the rectifying structure is located on at least both sides of the first epitaxial region in the second direction, and the rectifying structure is in contact with the second epitaxial region, and the second direction is the direction from the first source region structure to the second source region structure.

[0009] Optionally, the material of the rectifying structure is polysilicon.

[0010] Optionally, the MOS device further includes: a shielding region, the shielding region being located at least between the epitaxial layer and the second source region structure, and the shielding region being in contact with a bottom surface of the second source region structure, and the epitaxial layer having an epitaxial layer region located between the first source region structure and the shielding region.

[0011] Optionally, the epitaxial layer includes: a drift layer, which is in contact with the substrate; and a current spreading layer, which is located on a side of the drift layer away from the substrate, wherein the bottom surface of the rectifying structure is in contact with the drift layer, and the bottom surface of the first source region structure is in contact with the drift layer.

[0012] Optionally, the doping concentration of the current spreading layer is greater than the doping concentration of the epitaxial layer.

[0013] According to another aspect of the present application, a method for preparing a MOS device is provided, which is used to prepare any one of the MOS devices described above, and the method comprises: providing a substrate; forming an epitaxial layer on one side of the substrate; forming at least one source region structure on a side of the epitaxial layer away from the substrate, the source region structure comprising a first source region structure and a second source region structure, the first source region structure being located on a side of the epitaxial layer away from the substrate, the second source region structure being located on a side of the epitaxial layer away from the substrate, and a surface of the first source region structure on a side away from the substrate being located in a surface of the second source region structure on a side close to the substrate; forming at least one gate structure on a side of the epitaxial layer away from the substrate, the gate structure being located on a side of the epitaxial layer away from the substrate, and a bottom surface and a first side surface of the gate structure being in contact with the source region structure respectively; forming a plurality of rectifying structures on a side of the epitaxial layer away from the substrate, the rectifying structures being in contact with at least the source region structure and the epitaxial layer, and the rectifying structures having a doping type different from that of the epitaxial layer, wherein the plurality of rectifying structures are spaced apart in a first direction, and the first direction is parallel to the first side surface.

[0014] Optionally, the step of forming a plurality of the rectifying structures includes: forming a mask layer on the epitaxial layer;

[0015] A plurality of spacer regions spaced apart and distributed along the first direction are formed in the mask layer by using a photolithography process; the epitaxial layer below the spacer regions is etched by using an etching process to form a plurality of first grooves spaced apart and distributed along the first direction; a semiconductor material is filled in the first grooves by using a filling process; and the remaining mask layer is removed.

[0016] Through the technical solution of the present application, a MOS device is provided, in which a rectifying structure and an epitaxial layer have different doping types, and a heterojunction Schottky barrier diode structure (heterostructure Schottky barrier diode, referred to as heterojunction SBD) can be formed at the contact surface of the two, so that the heterojunction SBD can be integrated inside the MOS device, and the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode can be effectively improved. At the same time, the external anti-parallel diode is replaced by the internally integrated heterojunction SBD, which can improve the switching efficiency and the surge resistance of the body diode without increasing the cell size of the MOS device and reducing the packaging cost of the device, thereby improving the reverse recovery characteristics of the device and enhancing the reliability of the MOS device. In addition, the device can correspond to different electrical performance powers according to different usage scenarios. By arranging the rectifying structure at intervals along the first direction parallel to the first side, the volume ratio of the heterojunction SBD and the cell can be optimized, and the rectifying diode layout can be appropriately adjusted on the basis of ensuring the on-resistance and breakdown voltage of the cell. Without changing the process flow, the volume and performance of the MOS device can be optimized to meet the endurance of devices with different voltage resistances. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 is a schematic cross-sectional structure diagram of a first MOS device provided according to an embodiment of the present application;

[0019] Figure 2 is a schematic cross-sectional structure diagram of a second MOS device provided according to an embodiment of the present application;

[0020] Figure 3 is a schematic cross-sectional structure diagram of a third MOS device provided according to an embodiment of the present application;

[0021] Figure 4 is a schematic cross-sectional structure diagram of a fourth MOS device provided according to an embodiment of the present application;

[0022] Figure 5 is a top view of a first MOS device provided according to an embodiment of the present application;

[0023] Figure 6 is a top view of a second MOS device provided according to an embodiment of the present application;

[0024] Figure 7 is a top view of a third MOS device provided according to an embodiment of the present application;

[0025] Figure 8 is a top view of a fourth MOS device provided according to an embodiment of the present application;

[0026] Fig. 9 is a top view of a fifth MOS device provided according to an embodiment of the present application;

[0027] Fig.10 is a schematic cross-sectional structure diagram of a fifth MOS device provided according to an embodiment of the present application;

[0028] Fig.11 is a schematic cross-sectional structure diagram of a sixth MOS device provided according to an embodiment of the present application;

[0029] Fig.12 is a flow chart of a method for preparing a MOS device according to an embodiment of the present application;

[0030] Fig.13 A schematic diagram of the cross-sectional structure of a substrate obtained in each of the first eight steps in a method for preparing a MOS device provided in an embodiment of the present application is shown;

[0031] Fig.14 A schematic diagram of the cross-sectional structure of a substrate obtained in each of the last seven steps in a method for preparing a MOS device provided in an embodiment of the present application is shown.

[0032] The above drawings include the following reference numerals:

[0033] 10. substrate; 20. epitaxial layer; 2001. mask layer; 2002. spacing region; 201. first epitaxial region; 202. second epitaxial region; 204. first groove; 2041. first sidewall; 21. drift layer; 22. current spreading layer; 23. preliminary epitaxial layer; 30. source region structure; 301. first heavily doped region; 302. second heavily doped region; 303. body region; 31. first source region structure; 32. second source region structure; 33. first trench; 40. gate structure; 401. gate; 4011. second sidewall; 4012. third Side; 402, first gate dielectric; 4021, first sub-gate dielectric layer; 4022, second sub-gate dielectric layer; 41, first side; 50, rectifying structure; 501, first trench; 60, first structure; 70, shielding area; 80, second gate dielectric; 81, third sub-gate dielectric; 811, first low-pressure epoxy alkyl silicone oil layer; 812, second low-pressure epoxy alkyl silicone oil layer; 82, fourth sub-gate dielectric; 821, first tetraethyl orthosilicate layer; 822, second tetraethyl orthosilicate layer; 91, first conductive layer; 92, second conductive layer; 93, third conductive layer. DETAILED DESCRIPTION

[0034] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] As described in the background technology, in the prior art, when the MOSFET is in the off state, there will be a reverse leakage current between the drain and the source. If a diode is not added in reverse parallel, this leakage current may cause damage to other devices in the circuit. In addition, when SiC MOSFET is used for rectification of an AC circuit, since MOSFET can only be turned on under a forward voltage, an anti-parallel diode is required to provide a conduction channel under a reverse voltage, thereby realizing current rectification. Therefore, in the prior art, a diode is often integrated in an anti-parallel connection outside the SiC MOSFET body to improve the performance of the SiC MOSFET body diode, thereby improving the working efficiency of the SiC MOSFET, but the external anti-parallel diode will increase the occupied space of the circuit, increase the packaging cost of the device, and introduce parasitic capacitance and parasitic inductance, resulting in a slow response speed of the reverse diode, poor reliability and other problems. Moreover, for SiC MOSFET power devices with different withstand voltage devices, diodes with different freewheeling capabilities need to be connected in parallel to protect the normal use of the device. For example, a 1200V 13mΩ MOSFET device requires a stronger endurance than a 650V 40mΩ MOSFET device. This results in a larger proportion of the freewheeling diode of the 1200V 13mΩ MOSFET device in the actual cell, which requires sacrificing the performance of the cell itself, resulting in increased on-resistance and reduced withstand voltage performance. In order to solve the above technical problems, the present application provides a MOS device and a method for preparing a MOS device.

[0038] According to one aspect of the present application, a MOS device is provided, such as Figures 1 to 9 As shown, Figures 1 to 4 is a cross-sectional view of the above MOS device, which includes: a substrate 10; an epitaxial layer 20, the epitaxial layer 20 is located on one side of the substrate 10; at least one source region structure 30, each source region structure 30 includes a first source region structure 31 and a second source region structure 32, the first source region structure 31 is located on the side of the epitaxial layer 20 away from the substrate 10, the second source region structure 32 is located on the side of the epitaxial layer 20 away from the substrate 10, and the surface of the first source region structure 31 on the side away from the substrate 10 is located near the second source region structure 32. The surface of the epitaxial layer 20 is close to the substrate 10; at least one gate structure 40, the gate structure 40 is located on the side of the epitaxial layer 20 away from the substrate 10, and the bottom surface and the first side surface 41 of the gate structure 40 are respectively in contact with the source region structure 30; a plurality of rectifying structures 50, the rectifying structure 50 is located on the side of the epitaxial layer 20 away from the substrate 10, and the rectifying structure 50 is at least partially located in the epitaxial layer 20, the rectifying structure 50 is in contact with the source region structure 30, and the rectifying structure 50 has a doping type different from that of the epitaxial layer 20, wherein, as Figures 5 to 9 As shown, Figures 5 to 9The top view of the above MOS device shows that the rectifying structure 50 is arranged at intervals in the first direction A, and the first direction A is parallel to the first side surface 41 of the gate structure 40, and the top view of the MOS device shows that the first source region structure 31 and the second source region structure 32 are respectively on both sides of the gate structure 40 in the first direction A. In the above MOS device, the rectifying structure is equivalent to SBD, that is, the SBD pole is integrated inside the above MOS device, and the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode are effectively improved without increasing the cell width of the SiC MOSFET. At the same time, replacing the anti-parallel diode outside the body with the internally integrated heterojunction SBD can improve the switching efficiency and the surge resistance of the body diode without increasing the cell size of the MOS device and reducing the packaging cost of the device, improve the reverse recovery characteristics of the device, and enhance the reliability of the MOS device. In addition, the device can correspond to different electrical performance powers according to different usage scenarios. By arranging the rectifying structure at intervals along the first direction parallel to the first side, the volume ratio of the heterojunction SBD and the cell can be optimized, and the rectifying diode layout can be appropriately adjusted on the basis of ensuring the on-resistance and breakdown voltage of the cell. Without changing the process flow, the volume and performance of the MOS device can be optimized to meet the endurance of devices with different voltage resistances.

[0039] Specifically, in the prior art, for planar MOS, there is a problem that the electric field strength generated by the oxide layer above the gate region is high and the on-resistance is large; while the on-resistance of the trench MOS device is smaller, but there is a problem that the electric field strength at the corner below the trench is much greater than that at other positions. Under the same applied voltage and the same gate oxide thickness, the electric field strength at the corner of the trench is about 3 times that of the electric field in the middle of the planar MOS gate oxide, and the gate oxide is easily broken down in advance. In the above embodiment, by setting the first source region structure in the trench and the second source region structure on the side away from the substrate, the MOS device has the characteristics of both a planar MOS device and a trench MOS device, and has both a planar channel and a vertical channel, with a smaller on-resistance and a better balanced electric field distribution, so that the electric field originally concentrated in the oxide layer below the gate region and the corner of the trench is dispersed, reducing the risk of the gate being broken down in advance. At the same time, since the semi-planar and semi-trench structure changes the gate shape, the overlapping area between the gate and the drain is reduced, so the gate-drain charge Q gd , gate-drain capacitance C gd (also called Miller capacitance) are effectively reduced, which improves the switching speed of the device and reduces switching losses.

[0040] For example, Figures 1 to 4As shown, the first source region structure 31 and the second source region structure 32 both include a first heavily doped region 301, a second heavily doped region 302 and a body region 303, the first heavily doped region 301 and the body region 303 have a first doping type, the second heavily doped region 302 has a second doping type, and the body region 303 is located at least on one side of the first heavily doped region 301 and the second heavily doped region 302 close to the substrate 10.

[0041] Specifically, the doping concentration of the body region is 0.5×10 16 cm -3 ~1.5×10 17 cm -3 The thickness of the body region is 0.7 μm~0.8 μm; the doping concentration of the first heavily doped region is 0.5×10 18 cm -3 ~1.5×10 19 cm -3 The thickness of the first heavily doped region is 0.2 μm to 0.3 μm; the doping concentration of the second heavily doped region is 0.5×10 19 cm -3 ~1.5×10 20 cm -3 The thickness of the second heavily doped region is 0.2μm~0.3μm; the width ratio of the second heavily doped region to the first heavily doped region in the second direction is 1:1.5~1:1, and the thickness ratio in the direction perpendicular to the contact surface between the substrate and the epitaxial layer is 1:1~1:3, thereby ensuring that the first heavily doped region in the second direction and in the direction perpendicular to the contact surface between the substrate and the epitaxial layer can prevent the carriers of the second heavily doped region from moving in other directions, so that they can only move on a specified path, which can reduce device power consumption and leakage current, and complete the activation of the heavily doped region and facilitate process preparation.

[0042] Another exemplary example is Figures 1 to 4 As shown, the gate structure 40 includes a gate 401 and a first gate dielectric 402 . The first gate dielectric 402 is at least located between the gate 401 and the source region structure 30 , wherein the first gate dielectric 402 is in contact with at least the body region 303 and the second heavily doped region 302 .

[0043] Specifically, the material of the above-mentioned gate includes metal, polysilicon material or metal silicide. Among them, the metal material may include but is not limited to aluminum, copper, tantalum and tungsten or alloy material; the polysilicon material may include polysilicon and doped polysilicon material; the metal silicide uses a metal material with a higher melting point, such as tungsten, titanium, cobalt or nickel to dope polysilicon to form a metal silicide, which has good conductivity and high temperature resistance. For the above-mentioned gate materials, this application does not make specific restrictions. The material of the first gate dielectric may include but is not limited to any one or more of silicon oxide, aluminum oxide, titanium oxide, germanium oxide, gallium oxide, hafnium oxide, and indium tin oxide, which is not specifically limited in this application. A thicker insulating dielectric layer is formed at the bottom and corners of the gate trench structure to avoid the risk of device breakdown.

[0044] In some optional embodiments, such as Figure 5 As shown, the rectifying structure 50 is located on the side of the second source region structure 32 away from the first source region structure 31, and the rectifying structure 50 is only in contact with the second source region structure 32, and the plurality of rectifying structures 50 in contact with the second source region structure 32 and the epitaxial layer 20 are arranged alternately in the first direction A. Figure 1 for Figure 5 The cross-sectional view of the MOS device at aa′ is shown in FIG. Figure 1 As shown, the side of the second source region structure 32 away from the first source region structure 31 contacts the rectifying structure 50 , and the side of the first source region structure 31 away from the second source region structure 32 contacts the epitaxial layer 20 ; Figure 4 for Figure 5 The cross-sectional view of the MOS device at bb′ is shown in FIG. Figure 4 As shown, the side of the first source region structure 31 away from the second source region structure 32 and the side of the second source region structure 32 away from the first source region structure 31 are respectively in contact with the epitaxial layer 20. In this structure, a plurality of rectifier structures 50 are formed at intervals on the side of the second source region structure 32 away from the first source region structure 31. At this time, the volume of the heterojunction SBD structure accounts for a small proportion, so that the MOS device has a stronger pressure-bearing capacity.

[0045] In other optional embodiments, such as Figure 6 As shown, the rectifying structure 50 is located on the side of the first source region structure 31 away from the second source region structure 32, and the rectifying structure 50 is only in contact with the first source region structure 31, and the plurality of rectifying structures 50 in contact with the first source region structure 31 are arranged alternately with the epitaxial layer 20 in the first direction A. Figure 2 for Figure 6 The cross-sectional view of the MOS device at cc′ is shown in FIG. Figure 2 As shown, the side of the first source region structure 31 away from the second source region structure 32 contacts the rectifying structure 50 , and the side of the second source region structure 32 away from the first source region structure 31 contacts the epitaxial layer 20 ; Figure 4for Figure 6 The cross-sectional view of the MOS device at dd′ is shown in FIG. Figure 4 As shown, the side of the first source region structure 31 away from the second source region structure 32 and the side of the second source region structure 32 away from the first source region structure 31 are respectively in contact with the epitaxial layer 20. In this structure, a plurality of rectifier structures 50 arranged at intervals are formed only on the side of the first source region structure 31 away from the second source region structure 32. At this time, the volume of the heterojunction SBD structure accounts for a small proportion, resulting in a reduced proportion of the freewheeling diode, so that the MOS device has a stronger pressure-bearing capacity.

[0046] In some other optional embodiments, Figure 7 As shown, the rectifying structure 50 is located on the side of the first source region structure 31 away from the second source region structure 32, and the rectifying structure 50 is located on the side of the second source region structure 32 away from the first source region structure 31. Among them, the plurality of rectifying structures 50 in contact with the first source region structure 31 and the epitaxial layer 20 are alternately arranged in the first direction A, and the plurality of rectifying structures 50 in contact with the second source region structure 32 and the epitaxial layer 20 are alternately arranged in the first direction A. Among them, Figure 3 for Figure 7 The cross-sectional view of the MOS device at ee′ is shown in FIG. Figure 3 As shown, the side of the first source region structure 31 away from the second source region structure 32 and the side of the second source region structure 32 away from the first source region structure 31 are in contact with the rectifying structure 50 respectively; Figure 4 for Figure 7 The cross-sectional view of the MOS device at ff′ is shown in FIG. Figure 4 As shown, the side of the first source region structure 31 away from the second source region structure 32 and the side of the second source region structure 32 away from the first source region structure 31 are respectively in contact with the epitaxial layer 20. In this structure, a plurality of rectifier structures 50 are formed at intervals on the side of the first source region structure 31 away from the second source region structure 32 and on the side of the second source region structure 32 away from the first source region structure 31. At this time, the volume proportion of the heterojunction SBD structure is increased, and the conduction capability of the device is improved.

[0047] In some optional embodiments, such as Figure 8 As shown, each source region structure 30 and the gate structure 40 in contact with the first source region structure 31 and the second source region structure 32 in the source region structure 30 constitute a first structure 60, and the rectifying structure 50 and the first structure 60 are alternately arranged in the first direction A, wherein the rectifying structure 50 is in contact with the first source region structure 31, the second source region structure 32 and the gate structure 40 on both sides of the rectifying structure 50 in the second direction B, and the second direction B is the direction from the first source region structure 31 to the second source region structure 32.

[0048] Specifically, Fig.10 for Figure 8The cross-sectional view of the MOS device at gg′ is shown in FIG. Fig.10 As shown, the rectifying structure 50 is located on the side of the epitaxial layer 20 facing away from the substrate 10; Figure 4 for Figure 8 The cross-sectional view of the MOS device at hh′ is shown in FIG. Figure 4 As shown, the side of the first source region structure 31 away from the second source region structure 32 and the side of the second source region structure 32 away from the first source region structure 31 are respectively in contact with the epitaxial layer 20. In this structure, a rectifying structure 50 is formed between adjacent first structures 60 in the first direction A. At this time, the volume proportion of the heterojunction SBD structure increases, and the proportion of the freewheeling diode also increases accordingly, so that the MOS device has a stronger pressure-bearing capacity and the conduction capacity is improved.

[0049] In some optional embodiments, such as Fig. 9 As shown, each source region structure 30 and the gate structure 40 in contact with the first source region structure 31 and the second source region structure 32 in the source region structure 30 constitute a first structure 60, the epitaxial layer has a first epitaxial region 201 located on the side of the first structure 60 in a first direction A, and the epitaxial layer has a second epitaxial region 202 located on the side of the first structure 60 in a second direction B, wherein the rectifying structure 50 is located on both sides of the first epitaxial region 201 at least in the second direction B, and the rectifying structure 50 is in contact with the second epitaxial region 202, and the second direction B is the direction from the first source region structure 31 to the second source region structure 32.

[0050] Specifically, Fig.11 for Fig. 9 The cross-sectional view of the MOS device at jj′ is shown in FIG. Fig.11 As shown, the rectifying structure 50 is located on the side of the epitaxial layer 20 facing away from the substrate 10 , and the rectifying structure 50 is located on both sides of the second epitaxial region 202 ; Figure 4 for Fig. 9 The cross-sectional view of the MOS device at position ii′ is shown in FIG. Figure 4 As shown, the side of the first source region structure 31 away from the second source region structure 32 and the side of the second source region structure 32 away from the first source region structure 31 are respectively in contact with the epitaxial layer 20. In this structure, the volume proportion of the heterojunction SBD structure can be adjusted, and the proportion of the freewheeling diode is also relatively large, so that the MOS device has a stronger conduction capability.

[0051] In addition, Figures 5 to 9In the illustrated embodiment, those skilled in the art can further adjust the volume proportions of the rectifying structure 50, the source region structure 30 and the gate structure in each embodiment according to actual product requirements, further optimize the volume proportions of the heterojunction SBD and the cell, and appropriately adjust the rectifying diode layout on the basis of ensuring the on-resistance and breakdown voltage of the cell, so as to optimize the volume and performance of the MOS device without changing the process flow, and meet the endurance requirements of devices with different withstand voltages.

[0052] In the present application, the distribution of the rectifying structure and the first structure is not limited to the above-mentioned embodiments. Those skilled in the art can appropriately adjust the layout of the rectifying structure according to the pressure-bearing capacity and conduction capacity of the device required by different products, and optimize the volume and performance of the MOS device without changing the process flow to meet the endurance of different voltage-resistant devices.

[0053] In some optional embodiments, the material of the rectifying structure is polysilicon.

[0054] Specifically, polysilicon is a stable form of single silicon and has the properties of a semiconductor. Moreover, when a polysilicon material having a first doping type contacts an epitaxial layer having a second doping type, a space charge region will be formed at the contact interface due to the different energy band structures of the two, and the charge distribution in the space charge region will lead to the formation of a potential barrier. When a forward voltage is applied to the MOS device, the formed potential barrier is reduced, so that carriers can flow from the epitaxial layer to the rectifying structure to form a forward current; when a forward and reverse voltage is applied to the MOS device, the potential barrier will increase, preventing the flow of carriers, thereby forming a reverse cutoff, that is, a Schottky diode structure is formed at the contact between the polysilicon material of the first doping type and the epitaxial layer having the second doping type, that is, a heterojunction SBD is integrated inside the device, and the Schottky diode structure can reduce the conduction efficiency of the MOS device and increase the breakdown voltage of the device, and can reduce the forward voltage drop of the device, thereby improving the reliability of the MOS device.

[0055] Exemplarily, when the material of the rectifying structure is P-type polysilicon, the doping element is B, the epitaxial layer is N-type silicon carbide material, and the polysilicon material has a higher doping concentration, a heterojunction Schottky diode is formed at the bottom of the rectifying structure, which can enable the MOS device to reduce the on-resistance of the device while maintaining a high breakdown voltage, reduce the loss of current flowing through the device, and improve the conduction characteristics. In addition, by adjusting the depth and concentration of the rectifying structure, the forward voltage drop of the device can be further optimized.

[0056] In addition, the doping concentration of polysilicon material is 1.0×10 19 cm -3 ~1.0×10 20 cm -3The depth of the rectifying structure is 0.5~1.5um and the length is 0.3μm~0.8μm. The heterojunction Schottky diode composed of the rectifying structure and the epitaxial layer can replace the body diode composed of the source structure and the epitaxial layer, which can solve the problem of bipolar deterioration effect caused by the impact of the device under large current and multi-carrier injection in reverse.

[0057] In some optional embodiments, such as Figures 1 to 4 As shown, the above-mentioned MOS device also includes: a shielding region 70, the shielding region 70 is located at least between the epitaxial layer 20 and the second source region structure 32, and the shielding region 70 is in contact with the bottom surface of the second source region structure 32, and the epitaxial layer 20 has an epitaxial layer region located between the first source region structure 31 and the shielding region 70.

[0058] Specifically, in the trench gate structure MOSFET device in the prior art, the electric field concentration at the corner of the gate oxide layer causes the gate dielectric layer to break down. In addition, the planar MOS gate dielectric is also prone to breakdown, causing the device to break down at a voltage lower than the rated breakdown voltage, seriously affecting the forward blocking characteristics and long-term reliability of the device. Although the MOS device of the present application combines the planar gate MOS with the trench gate MOS device, there is still a hidden danger of causing the gate dielectric in the gate structure to break down. To this end, a shielding area is added between the second source region structure and the epitaxial layer, and the shielding area does not contact the first source region structure, which can better shield the potential and reduce the interference of the gate electric field on the channel charge. In addition, there is an epitaxial layer area in contact with the gate structure between the first source region and the shielding area, which can increase the capacitance accumulation on the surface of the gate structure, reduce the gate surface electric field, and enhance the reliability of the device.

[0059] The shielding area has a different doping type from the epitaxial layer, with a doping concentration of 0.5×10 18 cm -3 ~1.5×10 19 cm -3 The injection depth is 0.5μm~1.8μm.

[0060] In other optional embodiments, such as Figures 1 to 4 As shown, the epitaxial layer 20 includes: a drift layer 21, which is in contact with the substrate 10; a current spreading layer 22, which is located on the side of the drift layer 21 away from the substrate 10, wherein the bottom surface of the rectifying structure 50 is in contact with the drift layer 21, and the bottom surface of the first source region structure 31 is in contact with the drift layer 21.

[0061] Specifically, adding a shielding area to the device can reduce the surface electric field of the gate structure and increase the reliability of the device. However, if the gate structure is in contact with the drift layer, the doping concentration of the drift layer is low, resulting in the current being concentrated at the contact surface between the drift layer and the gate structure, causing the on-resistance of the device to increase. To this end, a current spreading layer is added on the side of the drift layer away from the substrate to reduce the on-resistance of the device and ensure a more uniform distribution of the current in the device.

[0062] In addition, the substrate 10 and the drift layer 21 have the same doping type, and the doping concentration of the drift layer 21 is 1.0×10 15 cm -3 ~1.0×10 16 cm -3 , wherein the doping concentration of the substrate 10 is higher than the doping concentration of the drift layer 21, and the resistivity of the substrate 10 is 0.016Ωcm~0.024Ωcm. The doped substrate 10 can reduce the on-resistance of the MOS device, and the substrate 10 has a high concentration so that an ohmic contact is formed at the drain end, further reducing the on-resistance of the device, thereby improving the performance of the device. In addition, the role of the drift layer 21 is to bear the main breakdown voltage. Those skilled in the art can meet the breakdown voltage of the product by adjusting the thickness of the drift layer 21. For example, when the thickness of the drift layer 21 is 9μm~11μm, the breakdown voltage of the MOS device is 1200V, and when the thickness of the drift layer 21 is 5μm~7μm, the breakdown voltage of the MOS device is reduced to 650V.

[0063] In some other specific embodiments, the doping concentration of the current spreading layer is greater than the doping concentration of the epitaxial layer.

[0064] Specifically, the doping concentration of the current spreading layer is 1.0×10 6 cm -3 ~1.0×10 17 cm -3 , thickness 0.5μ.~2.0μm.

[0065] Among them, the current spreading layer has a higher doping concentration, which can increase the number of carriers in the current spreading layer, thereby improving the conductivity of the carriers, thereby reducing the on-resistance of the device and helping the device to better transmit current. In addition, the on-resistance of the device can be adjusted by adjusting the doping concentration and thickness of the current spreading layer.

[0066] In some other embodiments, Figures 1 to 4As shown, the MOS device also includes: a second gate dielectric 80. The second gate dielectric 80 is at least located at the third side 4012 and the top surface of the gate 401 opposite to the second side 4011, and the second gate dielectric 80 is in contact with the gate 401, the first gate dielectric 402 and the first source region structure 31 respectively. The material of the second gate dielectric may include but is not limited to SIO2, Al2O3, AlN, HfO2 and Si3N4, which is not specifically limited in this application. The thickness of the second gate oxide layer and the thickness of the first gate oxide layer in the second direction are 6000A-12000A and 400A-800A respectively, and the thickness of the second gate oxide layer and the thickness of the first gate oxide layer in the third direction are 6000A-12000A and 400A-800A respectively, and the third direction is perpendicular to the surface of the substrate in contact with the epitaxial layer.

[0067] In some optional embodiments, such as Figures 1 to 4 As shown, the above MOS device further includes: a first conductive layer 91, such as Figures 1 to 4 and Figure 10 to Figure 11 As shown, the MOS device further includes: a second conductive layer 92 and a third conductive layer 93. The first conductive layer 91 is located on the side of the first heavily doped region 301 and part of the second heavily doped region 302 away from the substrate, and the first conductive layer 91 forms an ohmic contact with the source region structure 30. The second conductive layer 92 is respectively located on the side of the first conductive layer 91, the gate structure 40, the second gate dielectric 80 and the source region structure 30 away from the substrate 10, and the second conductive layer 92 is respectively in contact with the first conductive layer 91, the second gate dielectric 80 and part of the source region structure 30; the third conductive layer 93 is located on the side of the substrate 10 away from the epitaxial layer 20, wherein the second conductive layer 92 and the third conductive layer 93 are respectively used as the source electrode and the drain electrode of the MOS device, and play the role of current input and output of the MOS device.

[0068] Specifically, the material of the first conductive layer includes a metal material. The first conductive layer contacts the first heavily doped region and part of the second heavily doped region, forming a metal material-semiconductor material structure and a barrier layer. Since the doping concentration of the first heavily doped region and the second heavily doped region is 1.0×10 19 cm -3 ~1.0×10 20 cm -3 , with a higher doping concentration, carriers can pass through the barrier by tunneling effect, thus forming a low-resistance ohmic contact, thereby reducing the on-resistance of the device.

[0069] In some specific embodiments, the material of the first conductive layer includes but is not limited to Ni and Ti, and the thickness is 200 nm to 400 nm. Those skilled in the art can make a selection according to the product, and this application does not specifically limit it.

[0070] In addition, the materials of the second conductive layer and the third conductive layer include, but are not limited to, alloy materials composed of any one or more of Ag, Cu, Al, Au, Ti, Ni, Pt and Pb metals. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application. Among them, the thickness of the second conductive layer is 2μm~6μm, and the thickness of the third conductive layer is 200nm~400nm. Exemplarily, the material of the second conductive layer can be AlCu, and the material of the third conductive layer can be TiNiAg. Both AlCu and TiNiAg have good electrical conductivity, which improves the electrical conductivity of the device.

[0071] According to another aspect of the present application, a method for preparing a MOS device is provided, which is used to prepare any MOS device, such as Fig.12 As shown, the preparation method comprises:

[0072] Step S101: providing a substrate;

[0073] Step S102: forming an epitaxial layer on one side of the substrate;

[0074] Step S103: forming at least one source region structure on a side of the epitaxial layer facing away from the substrate, the source region structure comprising a first source region structure and a second source region structure, the first source region structure being located on a side of the epitaxial layer facing away from the substrate, the second source region structure being located on a side of the epitaxial layer facing away from the substrate, and a surface of the first source region structure on a side facing away from the substrate being located within a surface of the second source region structure on a side close to the substrate;

[0075] Step S104: forming at least one gate structure on a side of the epitaxial layer away from the substrate, the gate structure being located on the side of the epitaxial layer away from the substrate, and the bottom surface and the first side surface of the gate structure are in contact with the source region structure respectively;

[0076] Step S105: forming a plurality of rectifying structures on a side of the epitaxial layer away from the substrate, wherein the rectifying structures are in contact with at least the source region structure and the epitaxial layer, and have a doping type different from that of the epitaxial layer, wherein the plurality of rectifying structures are spaced apart in a first direction, and the first direction is parallel to the first side surface.

[0077] By adopting the above-mentioned preparation method of the embodiment of the present application, on the basis of the traditional MOS device, the SBD pole tube is integrated inside the MOS device, and the problems of excessive forward turn-on voltage drop and long reverse recovery time of the parasitic body diode are effectively improved without increasing the width of the SiC MOSFET cell. At the same time, the external anti-parallel diode is replaced by the internally integrated heterojunction SBD, which can improve the switching efficiency and the surge resistance of the body diode without increasing the cell size of the MOS device and reducing the packaging cost of the device, improve the reverse recovery characteristics of the device, and enhance the reliability of the MOS device. In addition, the same preparation process is adopted to prepare the rectifier structure arranged at intervals along the first direction parallel to the first side surface to optimize the volume proportion of the heterojunction SBD and the cell, so as to meet the power of the power device with different electrical properties in different usage scenarios, ensure that the rectifier diode layout is appropriately adjusted on the basis of the cell on-resistance and breakdown voltage, realize the optimization of the volume and performance of the MOS device, and meet the endurance of different withstand voltage devices.

[0078] The following will describe in more detail the exemplary embodiments of the method for preparing the MOS device provided by the present application in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0079] First, if Fig.13 As shown in (a), step S101 is performed: providing a substrate 10.

[0080] Specifically, the materials of the substrate 10 include silicon carbide, silicon, gallium nitride, gallium oxide, aluminum oxide, aluminum nitride and the like. Personnel skilled in the art may make reasonable selections based on actual needs, and no specific limitation is imposed on the application.

[0081] Exemplarily, the substrate includes a doped SiC substrate having a resistivity of 0.016 Ωcm to 0.024 Ωcm to form a high-power MOS device.

[0082] After providing the substrate, as Fig.13 As shown in (b), step S102 is performed: an epitaxial layer 20 is formed on one side of the substrate 10 .

[0083] The epitaxial layer 20 may include a drift layer 21 and a current spreading layer 22 , or may be only the drift layer 21 .

[0084] Specifically, first, a drift layer 21 is formed on a substrate; and then a current spreading layer 22 is formed on the drift layer 21 .

[0085] Specifically, the drift layer 21 may be an epitaxial layer having the same doping type as the substrate 10, or may be made of the same semiconductor material as the substrate. The doping concentration of the drift layer 21 is 1.0×10 15 cm -3 ~1.0×10 16 cm -3 , and the doping concentration of the drift layer 21 is lower than the doping concentration of the substrate, and bears the main breakdown voltage in the MOS device. In addition, those skilled in the art can adjust the thickness of the drift layer 21 to meet the breakdown voltage of the product. For example, when the thickness of the drift layer 21 is 9μm~11μm, the breakdown voltage of the MOS device is 1200V, and when the thickness of the drift layer 21 is 5μm~7μm, the breakdown voltage of the MOS device is reduced to 650V.

[0086] In addition, the current spreading layer 22 has the same doping type as the substrate 10, and may also have the same semiconductor material as the substrate. The doping concentration of the current spreading layer 22 is greater than the doping concentration of the drift layer 21. 16 cm -3 ~1.0×10 17 cm -3 , thickness 0.5μm~2.0μm.

[0087] In some optional embodiments, the process of forming a drift layer and a current spreading layer includes but is not limited to a deposition process and an epitaxial growth process. In the epitaxial growth process, the doping concentration of impurities is relatively easy to control and the activation rate is relatively fixed, so it is easy to achieve the target doping distribution. It is not only suitable for silicon-based power devices, but also can avoid the difficulty of injection doping of silicon carbide power devices and improve the efficiency of their terminal structure. The deposition process is relatively mature, simple to operate and has low cost. The deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD). Physical vapor deposition (PVD) includes but is not limited to magnetron sputtering process, reactive sputtering process, DC sputtering process, AC sputtering process, vacuum coating process, arc evaporation process, and chemical vapor deposition (CVD) includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), and laser-induced chemical vapor deposition (LCVD). Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0088] In some optional embodiments, after forming the epitaxial layer, step S1021 is further included. Fig.13 As shown in (c), a first groove 204 is formed in the epitaxial layer 20 to facilitate the subsequent formation of a first source region structure and a second source region structure.

[0089] It should be noted that if the epitaxial layer includes a drift layer and a current spreading layer, the depth of the first groove is greater than the thickness of the current spreading layer.

[0090] In some other optional implementations, after step S102, step S1022 is further included. Fig.13 As shown in (d), a shielding region 70 is formed at the lower corner of the first sidewall 2041 of the first groove 204 by using an ion implantation process.

[0091] Specifically, if the epitaxial layer includes a drift layer and a current spreading layer, the shielding region is at least partially located in the current spreading layer.

[0092] Specifically, the shielding region has a different doping type from the epitaxial layer, with a doping concentration of 0.5×10 18 cm -3 ~1.5×10 19 cm -3 , the injection depth is 0.5μm~1.8μm.

[0093] Then, proceed to step S103, as Fig.13 (e) to Fig.13 As shown in (f), a source region structure 30 is formed.

[0094] Specifically, the steps of forming the source region structure include: first, Fig.13 As shown in (e), an ion implantation process is used to form a body region 303 in the epitaxial layer 20; then, as shown in Fig.13 As shown in (f), ion implantation process is used to implant ions of different doping types into the body region 303 to form a first heavily doped region 301 and a second heavily doped region 302 .

[0095] More specifically, the steps of forming the first source region structure and the second source region structure include: first, Fig.13 As shown in (e), the body region 303 is formed by ion implantation process on the partial bottom of the first groove 204 and the preliminary epitaxial layer 23, wherein the preliminary epitaxial layer 23 is the epitaxial layer located at the first sidewall 2041 of the first groove 204; then, as shown in Fig.13 As shown in (f), ion implantation process is used to perform ion implantation of different doping types in the body region 303 to form a first heavily doped region 301 and a second heavily doped region 302. The first source region structure 31 or the second source region structure 32 includes the first heavily doped region 301, the second heavily doped region 302 and the body region 303, and the first source region structure 31 is a source region structure located at the bottom of the first groove 204, and the second source region structure 32 is a source region structure located at the sidewall of the first groove 204. The first source region structure 31 and the second source region structure 32 constitute the source region structure 30.

[0096] Among them, the process of forming the body region, the first heavily doped region, the second heavily doped region and the current extension layer includes but is not limited to the ion implantation process and the diffusion process, wherein the ion implantation process is to inject a high-energy ion beam into the semiconductor material, and is a process in which ions and semiconductor atoms collide and embed ions into the semiconductor crystal. The ion implantation process can accurately control the concentration and depth, and ion doping can be achieved at a lower temperature. The ion implantation equipment is expensive and the cost is high. The diffusion process is a process in which impurity atoms are allowed to diffuse freely along the thermal gradient of the crystal while maintaining thermal equilibrium in the semiconductor through high temperature or chemical reaction to achieve doping. The diffusion process does not require expensive equipment, requires higher control temperature and time conditions, and cannot accurately control the distribution and concentration of impurity atoms. Those skilled in the art can make reasonable selections according to actual needs, and no specific restrictions are made without application.

[0097] It should be noted that if the epitaxial layer includes a drift layer and a current spreading layer, the depth of the first source region structure in the third direction should be greater than the thickness of the current spreading layer, that is, the bottom surface of the first source region structure contacts the drift layer.

[0098] After the source region structure is formed, step S104 is performed: forming a gate structure.

[0099] Specifically, the steps of forming the gate structure include: Fig.13 As shown in (g), an oxidation process is used to form a first sub-gate dielectric layer 4021 and a second sub-gate dielectric layer 4022 connected to each other on at least a portion of the first source region structure 31 and on a side of the second source region structure 32 close to the first source region structure 31, wherein the first sub-gate dielectric layer 4021 is in contact with a portion of the first source region structure 31, the second sub-gate dielectric layer 4022 is in contact with the second source region structure 32, and the first sub-gate dielectric layer 4021 and the second sub-gate dielectric layer 4022 constitute a first gate dielectric 402; then, as shown in Fig.13 As shown in (h), the gate 401 is formed by a deposition process on a side of the first sub-gate dielectric layer 4021 facing away from the substrate 10 and a side of the second sub-gate dielectric layer 4022 facing away from the second source region structure 32 .

[0100] The gate material may include doped polysilicon material, which has good stability and compatibility and can improve the conductivity and stability of the MOS device. The thickness of the first sub-gate dielectric perpendicular to the first surface is 400A~800A, and the thickness of the first sub-gate dielectric parallel to the first surface is 400A~800A.

[0101] After the gate structure is formed, step S105: forming a rectifying structure.

[0102] Specifically, the steps of forming a plurality of rectifying structures include: first, Fig.14(a) shows that Fig.13 (h) A mask layer 2001 is formed on the semiconductor structure shown; Fig.14 As shown in (b), a plurality of spacer regions 2002 spaced apart and distributed along a first direction are formed in the mask layer 2001 by using a photolithography process, wherein: Fig.14 (b) for Fig.14 (a) is a schematic diagram of a top view of the structure after the spacing area 2002 is formed on the substrate; Fig.14 As shown in (c), the epitaxial layer below the spacing region is etched by an etching process to form a plurality of first trenches 501 spaced apart and distributed along a first direction; Fig.14 As shown in (d), a semiconductor material is filled in the first trench 501 by a filling process, and the remaining mask layer 2001 is removed. The semiconductor material and the epitaxial layer have different doping types to form a rectifying structure 50.

[0103] Specifically, the material of the rectifying structure can be polysilicon, and the doping concentration of the polysilicon material is 1.0×10 19 cm -3 ~1.0×10 20 cm -3 The depth of the rectifying structure is 0.5~1.5um and the length is 0.3~0.8um. ​​The heterojunction Schottky diode composed of the rectifying structure and the epitaxial layer can replace the body diode composed of the source structure and the epitaxial layer, which can solve the problems of bipolar deterioration effect caused by the impact of the device under large current and multi-carrier injection in reverse.

[0104] In some optional embodiments, the arrangement of the plurality of rectifying structures is as follows: Figure 5 As shown, the rectifying structure 50 is located on the side of the second source region structure 32 away from the first source region structure 31 , and the rectifying structure 50 is only in contact with the second source region structure 32 . The multiple rectifying structures 50 in contact with the second source region structure 32 are alternately arranged with the epitaxial layer 20 in the first direction A.

[0105] In some other optional embodiments, the arrangement of the plurality of rectifying structures is as follows: Figure 6 As shown, the rectifying structure 50 is located on the side of the first source region structure 31 away from the second source region structure 32, and the rectifying structure 50 is only in contact with the first source region structure 31. The multiple rectifying structures 50 in contact with the first source region structure 31 are alternately arranged with the epitaxial layer 20 in the first direction A.

[0106] In some other optional embodiments, the arrangement of the plurality of rectifying structures is as follows: Figure 7 As shown, the rectifying structure 50 is located on a side of the first source region structure 31 away from the second source region structure 32 , and the rectifying structure 50 is located on a side of the second source region structure 32 away from the first source region structure 31 .

[0107] In some further optional embodiments, the arrangement of the plurality of rectifying structures is as follows: Figure 8 As shown, each source region structure 30 and the gate structure 40 in contact with the first source region structure 31 and the second source region structure 32 in the source region structure 30 constitute a first structure 60, and the rectifying structure 50 and the first structure 60 are alternately arranged in the first direction A, wherein the rectifying structure 50 is in contact with the first source region structure 31, the second source region structure 32 and the gate structure 40 on both sides of the rectifying structure 50 in the second direction B, and the second direction B is the direction from the first source region structure 31 to the second source region structure 32.

[0108] In some other optional embodiments, the arrangement of the plurality of rectifying structures is as follows: Fig. 9 As shown, each source region structure 30 and the gate structure 40 in contact with the first source region structure 31 and the second source region structure 32 in the source region structure 30 constitute a first structure 60, the epitaxial layer 20 has a first epitaxial region 201 located on the side of the first structure 60 in the first direction A, and the epitaxial layer 20 has a second epitaxial region 202 located on the side of the first structure 60 in the second direction B, wherein the rectifying structure 50 is located on at least both sides of the first epitaxial region 201 in the second direction B, and the rectifying structure 50 is in contact with the second epitaxial region 202, and the second direction B is the direction from the first source region structure 31 to the second source region structure 32.

[0109] In some optional embodiments, after performing step S105, the preparation method further includes step S1051: Fig.14 As shown in (e), a second gate dielectric 80 is formed by a deposition process, wherein the second gate dielectric 80 is at least located on the third side surface 4012 and the top surface of the gate 401 opposite to the second side surface 4011, and the second gate dielectric 80 is in contact with the gate 401, the first gate dielectric 402 and the first source region structure 31 respectively.

[0110] The material of the second gate dielectric may include but is not limited to SIO2, Al2O3, AlN, HfO2 and Si3N4, which is not specifically limited in this application. Fig.14As shown in (e), the steps of forming the second gate dielectric 80 include: first, forming a first low-pressure epoxy alkyl silicone oil layer 811 (LPTEOS layer) at least on the third side surface 4012 of the gate 401 by a deposition process and forming a second low-pressure epoxy alkyl silicone oil layer 812 at least on the top surface of the gate 401, wherein the first low-pressure epoxy alkyl silicone oil layer 811 is in contact with the first source region structure 31, the first sub-gate dielectric layer 4021 and the gate 401 respectively, and the second low-pressure epoxy alkyl silicone oil layer 812 is in contact with the second source region structure 32, the second sub-gate dielectric layer 4022 and the gate 401; then Afterwards, a first PETEOS layer 821 (PETEOS layer) is formed on the side of the first low-pressure epoxyalkyl silicone oil layer 811 away from the gate 401 by a deposition process, and a second PETEOS layer 822 is formed on the side of the second low-pressure epoxyalkyl silicone oil layer 812 away from the substrate 10, wherein the first low-pressure epoxyalkyl silicone oil layer 811 and the first PETEOS layer 821 constitute a third sub-gate dielectric 81, the second low-pressure epoxyalkyl silicone oil layer 812 and the second PETEOS layer 822 constitute a fourth sub-gate dielectric 82, and the third sub-gate dielectric 81 and the fourth sub-gate dielectric 82 constitute a second gate dielectric 80.

[0111] Among them, the thicknesses of the first low-pressure epoxy alkyl silicone oil layer 811 and the first tetraethyl orthosilicate layer 821 in the direction parallel to the first surface are 1000A~4000A and 5000~8000A respectively, the thicknesses of the second low-pressure epoxy alkyl silicone oil layer 812 and the second tetraethyl orthosilicate layer 822 in the direction perpendicular to the first surface are 1000A~4000A and 5000~8000A respectively, and the thickness of the third sub-gate dielectric 81 in the direction parallel to the first surface is 6000A-12000A, and the thickness of the fourth sub-gate dielectric 82 in the direction perpendicular to the first surface is 6000A~12000A.

[0112] The above method is used to form the LPTEOS layer and the PETEOS layer in a two-step deposition process, which can not only reduce the preparation cost but also make the MOS device have better voltage resistance performance.

[0113] In some other optional embodiments, the above preparation method further includes step S1052: Fig.14 As shown in (f), a first conductive layer 91 is formed.

[0114] Specifically, Fig.14As shown in (f), the first conductive layer 91 is located on the side of the first heavily doped region 301 and part of the second heavily doped region 302 away from the substrate 10, and the first conductive layer 91 forms an ohmic contact with the first source region structure 31 and the second source region structure 32 respectively. The material of the first conductive layer 91 includes but is not limited to Ni and Ti, and the thickness is 200nm~400nm. The first conductive layer contacts the first heavily doped region 301 and the second heavily doped region 302, forming an ohmic contact, thereby reducing the on-resistance of the MOS device.

[0115] Exemplarily, a first conductive layer is formed using metal Ni, and a method for preparing the first conductive layer includes: first, forming NiSi with a thickness of about 200nm~400nm on the surface of the first heavily doped region and the second heavily doped region at 600℃~800℃, then stripping off unreacted Ni with a Ni etching solution, and performing high-temperature annealing at 900℃~1000℃ to form a first conductive layer of metal Ni.

[0116] In the above embodiment, the above preparation method further includes step S1043: Fig.14 As shown in (g), the second conductive layer 92 and the third conductive layer 93 are formed.

[0117] Specifically, Fig.14 As shown in (g), the second conductive layer 92 is respectively located on the side of the first conductive layer 91, the gate structure 40, the second gate dielectric 80, the first source region structure 31, the second source region structure 32 and the rectifying structure 50 away from the substrate 10, and the second conductive layer 92 is respectively in contact with the first conductive layer 91, the second gate dielectric 80 and a portion of the first source region structure 31, a portion of the second source region structure 32 and the rectifying structure 50; the third conductive layer 93 is located on the side of the substrate 10 away from the epitaxial layer 20, wherein the second conductive layer 92 and the third conductive layer 93 respectively serve as the source electrode and the drain electrode of the MOS device, playing the role of current input and output of the MOS device.

[0118] Among them, the materials of the second conductive layer and the third conductive layer include but are not limited to alloy materials composed of any one or more of Ag, Cu, Al, Au, Ti, Ni, Pt and Pb metals. Technical personnel in this field can make reasonable selections according to actual needs, and no specific limitations are made without application.

[0119] Exemplarily, the material of the second conductive layer includes AlCu with a thickness of 2 μm to 9 μm, and the material of the third conductive layer includes TiNiAg with a thickness of 200 nm to 400 nm. Both AlCu and TiNiAg have good conductivity, which improves the conductivity of the device.

[0120] The MOS device formed by the MOS device preparation method of the present application will be described below in conjunction with an embodiment.

[0121] The method for preparing a MOS device provided in this embodiment includes the following steps: Figure 13 to Figure 14 As shown:

[0122] Provide an N-type SiC substrate 10, whose resistivity is 0.02Ωcm, such as Fig.13 (a) as shown;

[0123] An N-type SiC drift layer 21 is formed on the N-type SiC substrate 10 by using an epitaxial growth process. The doping concentration of the N-type SiC drift layer 21 is 1.0×10 15 cm -3 ,like Fig.13 (b) as shown;

[0124] The N-type SiC current spreading layer 22 is formed on the N-type SiC drift layer 21 by a deposition process. The doping concentration of the N-type SiC current spreading layer 22 is 1.0×10 15 cm -3 , wherein the N-type SiC drift layer 21 and the N-type SiC current spreading layer 22 constitute the N-type SiC epitaxial layer 20, as shown Fig.13 (b) as shown;

[0125] A first groove 204 is formed on the N-type SiC epitaxial layer 20 by an etching process. Fig.13 (c) as shown;

[0126] The P-type shielding region 70 is formed at the corner of the first sidewall 2041 of the first groove 204 by an ion implantation process. The doping concentration of the P-type shielding region 70 is 1.0×10 19 cm -3 , with a depth of 1 μm, such as Fig.13 (d) shown.

[0127] The P-type body region 303 is formed on the bottom of the first groove 204 and the preliminary epitaxial layer 23 by ion implantation. The doping concentration of the P-type body region 303 is 1.0×10 17 cm -3 , with a depth of 0.7 μm, wherein the preliminary epitaxial layer 23 is an epitaxial layer located at the first sidewall 2041 of the first groove 204, such as Fig.13 (e) as shown;

[0128] The P-type body region 303 is doped with Al ions and N ions respectively by ion implantation to form a P-type first heavily doped region 301 and an N-type second heavily doped region 302. The doping concentration of the P-type first heavily doped region 301 is 1.0×10 19 cm -3, with a depth of 0.3 μm, an N-type second heavily doped region 302, with a depth of 0.3 μm, wherein the P-type body region 303, the first heavily doped region 301 and the N-type second heavily doped region 302 at the bottom of the first groove 204 constitute a first source region structure 31, and the P-type body region 303, the first heavily doped region 301 and the N-type second heavily doped region 302 at the sidewall of the first groove 204 constitute a first source region structure 31 and a second source region structure 32, as shown in FIG. Fig.13 (f) as shown;

[0129] An oxidation process is used to form a first sub-gate dielectric layer 4021 and a second sub-gate dielectric layer 4022 connected to each other on at least a portion of the first source region structure 31 and the side of the second source region structure 32 close to the first source region structure 31, wherein the materials of the first sub-gate dielectric layer 4021 and the second sub-gate dielectric layer 4022 are both silicon oxide materials, the first sub-gate dielectric layer 4021 and the second sub-gate dielectric layer 4022 constitute the first gate dielectric 402, the second sub-gate dielectric layer 4022 has a thickness of 600A on the side perpendicular to the second source region structure 32, and the first sub-gate dielectric has a thickness of 600A on the contact surface parallel to the substrate 10 and the epitaxial layer 20, such as Fig.13 (g) as shown;

[0130] A P-type polysilicon material is deposited on the side of the first sub-gate dielectric layer 4021 facing away from the substrate 10 and the side of the second sub-gate dielectric layer 4022 facing away from the second source region structure 32 by a deposition process to form a gate 401. Fig.13 (h) as shown;

[0131] A mask layer 2001 is formed on the semiconductor structure, such as Fig.14 (a) as shown;

[0132] A plurality of spaced-apart regions 2002 are formed in the mask layer 2001 along the first direction A by using a photolithography process. Fig.14 (b) as shown;

[0133] The epitaxial layer below the spacer region is etched by an etching process to form a plurality of first trenches 501 spaced apart along a first direction. Fig.14 (c) as shown;

[0134] The first trench is filled with P-type polysilicon by a filling process, and the doping concentration of P-type polysilicon is 1.0×10 19 cm -3 ,like Fig.14 (d) as shown;

[0135] A first low-pressure epoxy alkyl silicone oil layer 811 (LPTEOS layer) is formed at least on the third side surface 4012 of the gate 401 by a deposition process, and a second low-pressure epoxy alkyl silicone oil layer 812 is formed at least on the top surface of the gate 401, wherein the first low-pressure epoxy alkyl silicone oil layer 811 is in contact with the first source region structure 31, the first sub-gate dielectric layer 4021 and the gate 401, respectively, and the second low-pressure epoxy alkyl silicone oil layer 812 is in contact with the second source region structure 32, the second sub-gate dielectric layer 4022 and the gate 401, as shown in FIG. Fig.14 (e) as shown;

[0136] A first PETEOS layer 821 (PETEOS layer) is formed on a side of the first low-pressure epoxyalkyl silicone oil layer 811 away from the gate 401 by a deposition process, and a second PETEOS layer 822 is formed on a side of the second low-pressure epoxyalkyl silicone oil layer 812 away from the substrate 10, wherein the first low-pressure epoxyalkyl silicone oil layer 811 and the first PETEOS layer 821 constitute a third sub-gate dielectric 81, and the second low-pressure epoxyalkyl silicone oil layer 812 and the second PETEOS layer 822 constitute a fourth sub-gate dielectric 82. The third sub-gate dielectric 81 and the fourth sub-gate dielectric 82 are both treated at 100° C. to form SiO2 to form a second gate dielectric 80, as shown in FIG. Fig.14 (e) as shown;

[0137] NiSi is formed on the surface of the P-type first heavily doped region 301 and the N-type second heavily doped region by a deposition process at 700° C., and then unreacted Ni is stripped off by a Ni etching solution, and a high-temperature annealing treatment is performed at 950° C. to form a first conductive layer 91 of metal Ni. Fig.14 (f) as shown;

[0138] An AlCu layer with a thickness of 4 μm is formed on the side of the semiconductor structure away from the substrate 10 by a deposition process to form a second conductive layer 92. Fig.14 (g) as shown;

[0139] A TiNiAg alloy layer with a thickness of 300 nm is formed on the side of the substrate 10 away from the epitaxial layer 20 by a deposition process to form a third conductive layer 93. Fig.14 (g) shown.

[0140] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0141] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A MOS device, characterized in that: include: substrate; An epitaxial layer, the epitaxial layer is located on one side of the substrate, the epitaxial layer includes a drift layer, and the drift layer is in contact with the substrate; at least one source region structure, each of the source region structures comprising a first source region structure and a second source region structure, the first source region structure being located on a side of the epitaxial layer away from the substrate, the second source region structure being located on a side of the epitaxial layer away from the substrate, and a surface of the first source region structure on a side away from the substrate being located within a surface of the second source region structure on a side close to the substrate; at least one gate structure, the gate structure being located on a side of the epitaxial layer facing away from the substrate, and the bottom surface and the first side surface of the gate structure being in contact with the source region structure respectively; a plurality of rectifying structures, wherein the rectifying structures are located on a side of the epitaxial layer away from the substrate, and the rectifying structures are at least partially located in the epitaxial layer, the rectifying structures are in contact with the source region structure, and the rectifying structures have a doping type different from that of the epitaxial layer, wherein the plurality of rectifying structures are spaced apart in a first direction, and the first direction is parallel to the first side surface; a shielding region, wherein the shielding region is at least located between the epitaxial layer and the second source region structure, and the shielding region contacts a bottom surface of the second source region structure, and the epitaxial layer has an epitaxial layer region located between the first source region structure and the shielding region; A current spreading layer is located on a side of the drift layer away from the substrate, wherein a bottom surface of the rectifying structure contacts the drift layer, and a bottom surface of the first source region structure contacts the drift layer.

2. The MOS device according to claim 1, characterized in that: The rectifying structure is located on a side of the first source region structure away from the second source region structure, and the rectifying structure is located on a side of the second source region structure away from the first source region structure.

3. The MOS device according to claim 1, characterized in that: Each of the source region structures and the gate structure in contact with the first source region structure and the second source region structure in the source region structures constitute a first structure, and the rectifying structure and the first structure are alternately arranged in the first direction, wherein the rectifying structure is in contact with the first source region structure, the second source region structure and the gate structure on both sides in the second direction, respectively, and the second direction is the direction from the first source region structure to the second source region structure.

4. The MOS device according to claim 1, characterized in that: Each of the source region structures and the gate structure in contact with the first source region structure and the second source region structure in the source region structures constitute a first structure, the epitaxial layer has a first epitaxial region located on the side of the first structure in the first direction, and the epitaxial layer has a second epitaxial region located on the side of the first structure in the second direction, wherein the rectifying structure is located on at least both sides of the first epitaxial region in the second direction, and the rectifying structure is in contact with the second epitaxial region, and the second direction is the direction from the first source region structure to the second source region structure.

5. The MOS device according to any one of claims 1 to 4, characterized in that: The material of the rectifying structure is polysilicon.

6. The MOS device according to claim 1, characterized in that: The doping concentration of the current spreading layer is greater than the doping concentration of the epitaxial layer.

7. A method for preparing a MOS device, characterized in that: Used to prepare the MOS device according to any one of claims 1 to 6, the preparation method comprising: providing a substrate; forming an epitaxial layer on one side of the substrate, wherein the epitaxial layer includes a drift layer, and the drift layer is in contact with the substrate; At least one source region structure is formed on a side of the epitaxial layer away from the substrate, the source region structure includes a first source region structure and a second source region structure, the first source region structure is located on a side of the epitaxial layer away from the substrate, the second source region structure is located on a side of the epitaxial layer away from the substrate, and a surface of the first source region structure on a side away from the substrate is located in a surface of the second source region structure on a side close to the substrate; At least one gate structure is formed on a side of the epitaxial layer away from the substrate, the gate structure is located on a side of the epitaxial layer away from the substrate, and a bottom surface and a first side surface of the gate structure are in contact with the source region structure respectively; A plurality of rectifying structures are formed on a side of the epitaxial layer away from the substrate, the rectifying structures are in contact with at least the source region structure and the epitaxial layer, and the rectifying structures have a doping type different from that of the epitaxial layer, wherein the plurality of rectifying structures are spaced apart in a first direction, and the first direction is parallel to the first side surface forming a shielding region, wherein the shielding region is at least located between the epitaxial layer and the second source region structure, and the shielding region is in contact with a bottom surface of the second source region structure, and the epitaxial layer has an epitaxial layer region located between the first source region structure and the shielding region; A current spreading layer is formed, where the current spreading layer is located on a side of the drift layer away from the substrate, wherein a bottom surface of the rectifying structure contacts the drift layer, and a bottom surface of the first source region structure contacts the drift layer.

8. The preparation method according to claim 7, characterized in that: The steps of forming a plurality of the rectifying structures include: forming a mask layer on the epitaxial layer; Using a photolithography process to form a plurality of spaced-apart regions distributed at intervals along the first direction in the mask layer; Etching the epitaxial layer below the spacing region by an etching process to form a plurality of first grooves spaced apart and distributed along the first direction; Filling the first trench with semiconductor material using a filling process; The remaining mask layer is removed.

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