Optogenetic control device

Abstract

This invention discloses an optogenetic control device, relating to the field of electroencephalogram (EEG) monitoring. The device includes a data acquisition unit comprising a sensing electrode and a first amplifier. The sensing electrode is used to monitor EEG signals. The positive terminal of the sensing electrode is connected to the non-inverting input terminal of the first amplifier, and the negative terminal is grounded. A level signal generator has its input terminal connected to the output terminal of the first amplifier, used to convert the output signal of the first amplifier into high and low level signals. An output unit includes a light-emitting diode (LED) and a transistor. The transistor is disposed in the conduction circuit of the LED, and its gate is connected to the output terminal of the level signal generator. This invention, through the data acquisition unit, level signal generator, and output unit, not only enables real-time monitoring of EEG signals but also allows for optogenetic therapy of the brain producing abnormal EEG signals.

Description

Technical Field

[0001] This invention relates to the field of electroencephalogram (EEG) monitoring technology, and in particular to an optogenetic control device. Background Technology

[0002] Electroencephalogram (EEG) signals are a direct reflection of brain activity. Monitoring these signals allows for the assessment of brain health and provides crucial information for the diagnosis and treatment of related diseases. One treatment for brain-related diseases is optogenetic therapy. Optogenetics involves introducing light-sensitive proteins into nerve cells and using light signals to control the activity of specific nerve cells. Light-sensitive proteins undergo structural changes under light irradiation, altering ion channels in the cell membrane and triggering the transmission of nerve signals. Currently, there is no device that can effectively combine EEG signal monitoring with optogenetic therapy. Current optogenetic devices lack time-response capability; they can only be continuously switched on or off and cannot respond to EEG signals. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention is proposed.

[0004] Therefore, the problem to be solved by this invention is how to make a real-time response to electroencephalogram (EEG) signals in an optogenetic device, so as to achieve time resolution of optogenetic technology.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: an optogenetic control device, comprising: a acquisition unit including a sensing electrode and a first amplifier, wherein the sensing electrode is used to monitor electroencephalogram (EEG) signals; the positive terminal of the sensing electrode is connected to the non-inverting input terminal of the first amplifier, and the negative terminal is grounded; a level signal generator, the input terminal of which is connected to the output terminal of the first amplifier, for converting the output signal of the first amplifier into high and low level signals; and an output unit including a light-emitting diode (LED) and a transistor, wherein the transistor is disposed in the conduction circuit of the LED, and the gate of the transistor is connected to the output terminal of the level signal generator.

[0006] In a preferred embodiment of the optogenetic control device of the present invention, the acquisition unit further includes a first resistor and a second resistor, wherein a first end of the first resistor is grounded and a second end is connected to the inverting input terminal of the first amplifier; a first end of the second resistor is connected to the power supply of the first amplifier, and a second end is connected to the second end of the second resistor and the inverting input terminal of the first amplifier.

[0007] In a preferred embodiment of the optogenetic control device of the present invention, a voltage follower circuit is further provided between the acquisition unit and the level signal generator. The input terminal of the voltage follower circuit is connected to the output terminal of the first amplifier, and the output terminal of the voltage follower circuit is connected to the input terminal of the level signal generator.

[0008] In a preferred embodiment of the optogenetic control device of the present invention, a second amplifier and a third resistor are further provided between the acquisition unit and the level signal generator. The non-inverting input terminal of the second amplifier is connected to the output terminal of the first amplifier, and the output terminal of the second amplifier is connected to the input terminal of the level signal generator. The first terminal of the third resistor is connected to the inverting input terminal of the second amplifier, and the second terminal is connected to the output terminal of the second amplifier.

[0009] In a preferred embodiment of the optogenetic control device of the present invention, the level signal generator is a square wave generator.

[0010] In a preferred embodiment of the optogenetic control device of the present invention, the level signal generator is a microcontroller.

[0011] In a preferred embodiment of the optogenetic control device of the present invention, the level signal generator includes an NE555 timer chip and an external charging and discharging circuit.

[0012] In a preferred embodiment of the optogenetic control device of the present invention, the level signal generator includes an NE555 timer chip, a first capacitor, a second capacitor, a fourth resistor, a fifth resistor, a sixth resistor, a first diode, and a second diode; the positive terminal of the first capacitor is connected to the trigger input pin and threshold input pin of the NE555 timer chip, the positive terminal of the first diode, and the negative terminal of the second diode, and the negative terminal of the first capacitor is grounded; the positive terminal of the second capacitor is connected to the voltage control input pin of the NE555 timer chip, and the negative terminal is grounded; the first terminal of the fourth resistor is connected to a power supply, and the second terminal is connected to the first terminals of the fifth resistor and the sixth resistor respectively; the second terminals of the fifth resistor and the sixth resistor are connected to the negative terminal of the first diode and the positive terminal of the second diode respectively.

[0013] In a preferred embodiment of the optogenetic control device of the present invention, the positive terminal of the light-emitting diode is connected to a power source, and the negative terminal is connected to the source of the transistor; the drain of the transistor is grounded, and the gate is connected to the output terminal of the level signal generator.

[0014] In a preferred embodiment of the optogenetic control device of the present invention, the output unit further includes a seventh resistor and an eighth resistor. The first end of the seventh resistor is connected to the output terminal of the level signal generator, and the second end is connected to the gate of the transistor. The first end of the eighth resistor is connected to the second end of the seventh resistor and the gate of the transistor, and the second end is grounded.

[0015] The beneficial effects of this invention are as follows: This invention, through the acquisition unit, level signal generator, and output unit, can not only realize real-time monitoring of EEG signals, but also perform optogenetic therapy on the brain that produces abnormal EEG signals. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the circuit structure of the optogenetic control device described in Example 1.

[0018] Figure 2 This is a schematic diagram of the voltage follower circuit in Example 2.

[0019] Figure 3 This is a schematic diagram of the level signal generator circuit described in Example 3. Detailed Implementation

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0022] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it an embodiment that is mutually exclusive, either alone or selectively, with other embodiments.

[0023] Example 1

[0024] Reference Figure 1This is the first embodiment of the present invention, which provides an optogenetic control device, which includes a data acquisition unit 100, a level signal generator 200 and an output unit 300.

[0025] Specifically, the acquisition unit 100 includes a sensing electrode 101 and a first amplifier 102. The sensing electrode 101 is attached to the brain being measured, and the electroencephalogram (EEG) signal is sensed by the sensing electrode 101 in the form of a voltage. The first amplifier 102 is an LMV358 integrated operational amplifier chip. The sensing electrode 101 is integrated into a connector P1, where pin 3 is the positive terminal of the voltage signal terminal of the sensing electrode 101, and pin 4 is the negative terminal of the voltage signal terminal of the sensing electrode 101.

[0026] Pin 3 of connector P1 (positive terminal of sensing electrode 101) is connected to the non-inverting input terminal of the first amplifier 102, and pin 4 of connector P1 (negative terminal of sensing electrode 101) is grounded.

[0027] The acquisition unit 100 also includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is grounded, and the second end is connected to the inverting input terminal of the first amplifier 102.

[0028] The first terminal of the second resistor R2 is connected to the power supply VCC of the first amplifier 102, and the second terminal is connected to the second terminal of the second resistor R2 and the inverting input terminal of the first amplifier 102. The second resistor R2 is a variable resistor. The voltage output from the output terminal of the first amplifier 102 is defined as Vo1.

[0029] A voltage comparator is formed by the first resistor R1, the second resistor R2, and the first amplifier 102. The voltage threshold of the comparator can be set using a voltage divider circuit with the first resistor R1 and the second resistor R2. The threshold voltage of the comparator can be calculated using the following formula:

[0030]

[0031] In practical applications, VCC is powered by 5V, the first resistor R1 has a resistance of 1KΩ, and the second resistor R2 has a maximum resistance of 10MΩ. The comparator's threshold voltage range can be continuously adjusted between 0.1mV and 5V.

[0032] When the input voltage of the sensing electrode 101 is higher than the threshold value, the comparator outputs a supply voltage Vo1 = 5V. When the electrode input voltage is lower than the threshold value, the output Vo1 = 0V.

[0033] Furthermore, a voltage follower circuit 400 is also provided after the acquisition unit 100. In this embodiment, the voltage follower circuit 400 includes a second amplifier 401 and a third resistor R3, and the non-inverting input terminal of the second amplifier 401 is connected to the output terminal of the first amplifier 102;

[0034] The first end of the third resistor R3 is connected to the inverting input terminal of the second amplifier 401, and the second end is connected to the output terminal of the second amplifier 401.

[0035] The second amplifier 401 is an LMV358 integrated operational amplifier chip, and its output voltage is Vo2. The output voltage of the voltage follower circuit 400 is equal to the output voltage of the acquisition unit 100, i.e., Vo2 = Vo1. Its main function is to isolate the input and output parts of the circuit and reduce high-frequency interference of the electrode signal.

[0036] Furthermore, a square wave generator is also provided after the voltage follower circuit 400. In this embodiment, the square wave generator includes an NE555 timer chip 201, a first capacitor C1, a second capacitor C2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first diode D1, and a second diode D2.

[0037] The positive terminal of the first capacitor C1 is connected to the trigger input pin 2 of the NE555 timer chip 201. The threshold input pin 6 (TH), the positive terminal of the first diode D1, and the negative terminal of the second diode D2 are connected. The negative terminal of the first capacitor C1 is grounded. The first capacitor C1 is an electrolytic capacitor.

[0038] The positive terminal of the second capacitor C2 is connected to the voltage control input pin 5 (VC) of the NE555 timer chip 201, and the negative terminal is grounded.

[0039] The first end of the fourth resistor R4 is connected to the power supply VCC, and the second end is connected to the first end of the fifth resistor R5 and the sixth resistor R6 respectively.

[0040] The second terminals of the fifth resistor R5 and the sixth resistor R6 are connected to the cathode of the first diode D1 and the anode of the second diode D2, respectively. Both the fifth resistor R5 and the sixth resistor R6 are adjustable resistors.

[0041] The NE555 timer chip 201 has its positive power supply pin 8 (VCC) and discharge pin 7 (DIS) connected to the power supply VCC, and its ground pin 1 (GND) grounded. Output pin 3 (OUT) is used to output a square wave signal.

[0042] The output voltage of the forward circuit controls the enable pin of the NE555 timer chip 201. The high or low level of the voltage determines whether the NE555 timer chip 201 starts working. When the forward circuit outputs a high level, the enable pin is active. The circuit controls the threshold state of the NE555 timer chip 201 through the charging and discharging process of the first capacitor C1, thereby causing the output pin 3 of the NE555 timer chip 201 to repeatedly output high and low level signals, forming a square wave. When the first capacitor C1 is charging, the circuit outputs a high level. The charging duration is controlled by the RC charging constant, i.e.:

[0043] T c =ln(3)·(R4+R5)·C1

[0044] When the voltage across the first capacitor C1 reaches the control threshold of the NE555 timer chip 201, it triggers discharge, and the circuit outputs a low level. The discharge duration is:

[0045] T d =ln(3)·(R4+R6)·C1

[0046] By adjusting the values ​​of the fifth resistor R5 and the sixth resistor R6, the duration of the high and low levels output by the circuit can be changed, thereby controlling the frequency of the output square wave. Therefore, the frequency of the circuit's output square wave is:

[0047]

[0048] In practical applications, controlling R5 = R6 generates a square wave signal with a 50% duty cycle. When using... Figure 1 With the circuit parameters shown, the calculated frequency range of the circuit output is approximately 0.96Hz to 106.3Hz.

[0049] The output unit 300 includes a light-emitting diode 301, a transistor 302, a seventh resistor R7 and an eighth resistor R8. The positive terminal of the light-emitting diode 301 is connected to a power supply, and the negative terminal is connected to the source of the transistor 302. The drain of the transistor 302 is grounded.

[0050] The first end of the seventh resistor R7 is connected to the output of the level signal generator 200, and the second end is connected to the gate of the transistor 302. The first end of the eighth resistor R8 is connected to the second end of the seventh resistor R7 and the gate of the transistor 302, and the second end is grounded. The output pin 3 (OUT) of the NE555 timer chip 201 is connected to the gate of the transistor 302 through the seventh resistor R7.

[0051] Transistor 302 is an N-type MOSFET. When the level signal generator 200 outputs a square wave, within the high-level range of the square wave, transistor 302 is turned on, the circuit is turned on, and LED 301 lights up. Within the low-level range of the square wave, transistor 302 is turned off, the circuit is turned off, and LED 301 is turned off. Therefore, when the level signal generator 200 outputs a square wave, LED 301 will blink, and the blinking frequency is the same as the square wave frequency.

[0052] It should be noted that the light-emitting diode 301 is also integrated in the connector P1 and the light emitted can penetrate the sensing electrode 101 to irradiate the photosensitive protein, thereby achieving the therapeutic purpose.

[0053] In summary, the sensing electrode 101 monitors EEG signals in real time. When an abnormal signal is detected, the light-emitting diode 301 will not only flash as an alarm, but also irradiate the photosensitive protein at a specific frequency to achieve the therapeutic purpose.

[0054] Example 2

[0055] Reference Figure 2 This is the second embodiment of the present invention, which is based on the previous embodiment. Unlike the previous embodiment, in this embodiment, the voltage follower circuit 400 includes a second amplifier 401, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a third resistor R3, a third capacitor C3, a third diode D3, and a fourth diode D4.

[0056] Among them, the first end of the third resistor R3 is connected to the inverting input terminal of the second amplifier 401, and the second end is connected to the output terminal of the second amplifier 401.

[0057] The first terminals of the ninth resistor R9 and the tenth resistor R10 are both connected to the output terminal of the first amplifier 102. The second terminal of the ninth resistor R9 is connected to the positive terminal of the third capacitor C3 and the non-inverting input terminal of the second amplifier 401. The second terminal of the tenth resistor R10 is connected to the negative terminal of the third capacitor C3 and grounded.

[0058] The cathode of the third diode 402 is connected to the power supply VCC, and the anode is connected to the output terminal of the second amplifier 401; the cathode of the fourth diode 403 is connected to the output terminal of the second amplifier 401, and the anode is grounded. The third diode 402 and the fourth diode 403 form an electrostatic clamp.

[0059] The first end of the eleventh resistor R11 is connected to the output of the second amplifier 401, and the second end is connected to the input of the level signal generator 200.

[0060] Example 3

[0061] Reference Figure 3This is the third embodiment of the present invention, based on Embodiment 1. Unlike Embodiment 1, in this embodiment, the peripheral charging and discharging circuit includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifth diode D5, a sixth diode D6, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. The thirteenth resistor R13 is a variable resistor.

[0062] Among them, the first end of the twelfth resistor R12 is connected to the external reset pin 4 (RST) of the NE555 timer chip 201, and the second end is connected to the first end of the thirteenth resistor R13.

[0063] The third terminal of the thirteenth resistor R13 is connected to the discharge pin 7 (DIS) of the NE555 timer chip 201, and the second terminal is connected to the first terminal of the fourteenth resistor R14.

[0064] The negative terminal of the fifth diode D5 is connected to the second end of the fourteenth resistor R14, and the positive terminal is connected to the positive terminal of the fourth capacitor C4. The negative terminal of the fourth capacitor C4 is grounded. The negative terminal of the fifth diode D5 is also connected to the threshold input pin 6 (THR) and trigger input pin 2 (TR) of the NE555 timer chip 201.

[0065] The positive terminal of the sixth diode D6 is connected to the third terminal of the thirteenth resistor R13, and the negative terminal is connected to the positive terminal of the fifth diode D5.

[0066] The positive terminal of the sixth capacitor C6 is connected to the positive power supply pin 8 (VCC) of the NE555 timer chip 201, and the negative terminal is grounded.

[0067] The positive terminal of the fifth capacitor C5 is connected to the voltage control input pin 5 (VC) of the NE555 timer chip 201, and the negative terminal is grounded.

[0068] From the circuit connection described above, the high-level time (charging time) of the output square wave can be obtained as follows:

[0069] T1=(R12+R13′)·C4·ln(2)

[0070] The low-level time (discharge time) of the output square wave is:

[0071] T2=(R14+R13″)·C4·ln(2)

[0072] The period T is:

[0073] T=(R12+R14+R13)·C·ln(2)

[0074] The duty cycle q is:

[0075]

[0076] The duty cycle can be adjusted by adjusting the position of the middle tap of the thirteenth resistor R13.

[0077] Example 4

[0078] This is the fourth embodiment of the present invention, based on Embodiment 1. Unlike Embodiment 1, in this embodiment, the level signal generator 200 can directly employ a microcontroller, which includes...

[0079] The central processing unit (CPU) is used to execute program code and control the operation of the entire system.

[0080] A digital-to-analog converter is used to convert analog voltage signals into digital signals;

[0081] Timer / counter, used to generate PWM signals with a specific frequency;

[0082] Input / output port: Reads analog signals and outputs PWM signals;

[0083] The interrupt controller is used to handle timer interrupts and achieve precise time control.

[0084] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An optogenetic control device, characterized in that: include, The acquisition unit (100) includes a sensing electrode (101) and a first amplifier (102). The sensing electrode (101) is used to monitor electroencephalogram (EEG) signals. The positive terminal of the sensing electrode (101) is connected to the non-inverting input terminal of the first amplifier (102), and the negative terminal is grounded. A level signal generator (200) has its input terminal connected to the output terminal of the first amplifier (102) and is used to convert the output signal of the first amplifier (102) into a high or low level signal. The output unit (300) includes a light-emitting diode (301) and a transistor (302), wherein the transistor (302) is disposed in the conduction loop of the light-emitting diode (301), and the gate of the transistor (302) is connected to the output terminal of the level signal generator (200); The level signal generator (200) includes an NE555 timer chip (201), a first capacitor (C1), a second capacitor (C2), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), a first diode (D1), and a second diode (D2). The positive terminal of the first capacitor (C1) is connected to the trigger input pin and the threshold input pin of the NE555 timer chip (201), the positive terminal of the first diode (D1), and the negative terminal of the second diode (D2), and the negative terminal of the first capacitor (C1) is grounded. The positive terminal of the second capacitor (C2) is connected to the voltage control input pin of the NE555 timer chip (201), and the negative terminal is grounded. The first terminal of the fourth resistor (R4) is connected to the power supply, and the second terminal is connected to the first terminals of the fifth resistor (R5) and the sixth resistor (R6), respectively. The second terminals of the fifth resistor (R5) and the sixth resistor (R6) are connected to the negative terminal of the first diode (D1) and the positive terminal of the second diode (D2), respectively.

2. The optogenetic control device as described in claim 1, characterized in that: The acquisition unit (100) further includes a first resistor (R1) and a second resistor (R2). The first end of the first resistor (R1) is grounded, and the second end is connected to the inverting input terminal of the first amplifier (102). The first end of the second resistor (R2) is connected to the power supply of the first amplifier (102), and the second end is connected to the second end of the second resistor (R2) and the inverting input terminal of the first amplifier (102).

3. The optogenetic control device as described in claim 1, characterized in that: A voltage follower circuit (400) is also provided between the acquisition unit (100) and the level signal generator (200). The input terminal of the voltage follower circuit (400) is connected to the output terminal of the first amplifier (102), and the output terminal of the voltage follower circuit (400) is connected to the input terminal of the level signal generator (200).

4. The optogenetic control device as described in claim 1, characterized in that: A second amplifier (401) and a third resistor (R3) are also provided between the acquisition unit (100) and the level signal generator (200). The non-inverting input terminal of the second amplifier (401) is connected to the output terminal of the first amplifier (102), and the output terminal of the second amplifier (401) is connected to the input terminal of the level signal generator (200). The first terminal of the third resistor (R3) is connected to the inverting input terminal of the second amplifier (401), and the second terminal is connected to the output terminal of the second amplifier (401).

5. The optogenetic control device as described in claim 1, characterized in that: The level signal generator (200) is a square wave generator.

6. The optogenetic control device as described in claim 1, characterized in that: The level signal generator (200) is a microcontroller.

7. The optogenetic control device as described in claim 1, characterized in that: The level signal generator (200) includes an NE555 timer chip (201) and an external charging and discharging circuit.

8. The optogenetic control device as described in claim 1, characterized in that: The positive terminal of the light-emitting diode (301) is connected to a power source, and the negative terminal is connected to the source of the transistor (302); the drain of the transistor (302) is grounded, and the gate is connected to the output terminal of the level signal generator (200).

9. The optogenetic control device as described in claim 1, characterized in that: The output unit (300) further includes a seventh resistor (R7) and an eighth resistor (R8). The first end of the seventh resistor (R7) is connected to the output terminal of the level signal generator (200), and the second end is connected to the gate of the transistor (302). The first end of the eighth resistor (R8) is connected to the second end of the seventh resistor (R7) and the gate of the transistor (302), and the second end is grounded.

Images