Data storage method and device for multi-core heterogeneous chip, chip and electronic equipment

Abstract

The invention provides a data storage method for a multi-core heterogeneous chip, the multi-core heterogeneous chip at least comprises a real-time domain and a first hardware domain, and the method comprises the steps that an analog-to-digital conversion module on the real-time domain detects the power supply voltage of the multi-core heterogeneous chip; comparing the power supply voltage with a voltage threshold value; under the condition that the power supply voltage is smaller than the threshold voltage, the real-time domain sends a first command to the first hardware domain, and the first command is used for indicating the first hardware domain to enter a dormant state; in the dormant state, partial functions or all functions of the first hardware domain are in a non-running state; the real-time domain obtains the operation authority of a memory corresponding to the multi-core heterogeneous chip; the real-time domain stores data corresponding to the first hardware domain to the memory; wherein when the multi-core heterogeneous chip runs, the power consumption of the real-time domain is smaller than that of the first hardware domain.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a data storage method, device, chip and electronic device for a multi-core heterogeneous chip. Background Art

[0002] Multi-core heterogeneous chips integrate multiple processor cores of different architectures or types. Since different processor cores have different processing capabilities, multi-core heterogeneous chips have higher performance and power efficiency. Multi-core heterogeneous chips are also widely used in products such as smart vehicles. There is a need for data interaction between different processor cores of multi-core heterogeneous chips. If a multi-core heterogeneous chip experiences abnormal power failure or power outage, key information may be lost, such as the vehicle's navigation information, the vehicle's real-time status parameters, and the vehicle's operating data. Therefore, quickly storing data in multi-core heterogeneous chips is an urgent problem to be solved. Summary of the invention

[0003] The embodiments of the present application provide a data storage method, device, chip and electronic device for a multi-core heterogeneous chip, which can quickly and accurately store data in the multi-core heterogeneous chip.

[0004] The technical solution of the embodiment of the present application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a data storage method for a multi-core heterogeneous chip, wherein the multi-core heterogeneous chip includes at least a real-time domain and a first hardware domain, and the method includes:

[0006] The analog-to-digital conversion module in the real-time domain detects the power supply voltage of the multi-core heterogeneous chip; compares the power supply voltage with a voltage threshold;

[0007] When the power supply voltage is less than the threshold voltage, the real-time domain sends a first command to the first hardware domain, wherein the first command is used to instruct the first hardware domain to enter a sleep state; in the sleep state, some or all functions of the first hardware domain are in a non-operating state;

[0008] The real-time domain obtains the operation authority of the memory corresponding to the multi-core heterogeneous chip;

[0009] The real-time domain stores the data corresponding to the first hardware domain into the memory;

[0010] When the multi-core heterogeneous chip is running, the power consumption of the real-time domain is less than the power consumption of the first hardware domain.

[0011] In some optional embodiments, the first command includes a first subcommand and a second subcommand; the real-time domain sends the first command to the first hardware domain, including:

[0012] The real-time domain sends a first subcommand to the first hardware domain, where the first subcommand is used to instruct an intellectual property (IP) core of the first hardware domain to enter a dormant state;

[0013] The real-time domain sends a second subcommand to the first hardware domain, where the second subcommand is used to instruct a central processing unit (CPU) of the first hardware domain to enter a sleep state.

[0014] In some optional embodiments, the real-time domain obtains the operation permission of the memory corresponding to the multi-core heterogeneous chip, including:

[0015] The real-time domain modifies configuration information of a register on the multi-core heterogeneous chip, where the modified configuration information is used to indicate that the real-time domain has operation authority for the memory;

[0016] The operation authority at least includes: an authority to write data to the memory.

[0017] In some optional embodiments, the real-time domain stores the data corresponding to the first hardware domain in the memory, including: the real-time domain stores the data corresponding to the first hardware domain in a boot partition of the memory.

[0018] In some optional embodiments, the real-time domain stores the data corresponding to the first hardware domain in the memory, including:

[0019] The real-time domain stores data corresponding to the first hardware domain in a first partition of the memory.

[0020] In some optional embodiments, the method further comprises:

[0021] Comparing the data corresponding to the first hardware domain stored in the boot partition with the data corresponding to the first hardware domain stored in the first partition to obtain a comparison result;

[0022] The reliability of the data stored in the memory is confirmed based on the comparison result.

[0023] In a second aspect, an embodiment of the present application provides a data storage device of a multi-core heterogeneous chip, wherein the multi-core heterogeneous chip includes at least a real-time domain and a first hardware domain, and the data storage device of the multi-core heterogeneous chip includes:

[0024] An analog-to-digital conversion module, used to detect the power supply voltage of the multi-core heterogeneous chip;

[0025] A comparison module, used for comparing the power supply voltage with a voltage threshold;

[0026] a sending module, configured to send a first command to the first hardware domain when the power supply voltage is less than the threshold voltage, wherein the first command is used to instruct the first hardware domain to enter a dormant state; in the dormant state, some or all functions of the first hardware domain are in a non-operating state;

[0027] An acquisition module, used to obtain the operation permission of the memory corresponding to the multi-core heterogeneous chip;

[0028] A storage module, used for storing the data corresponding to the first hardware domain into the memory;

[0029] When the multi-core heterogeneous chip is running, the power consumption of the real-time domain is less than the power consumption of the first hardware domain.

[0030] In some optional embodiments, the first command includes a first subcommand and a second subcommand; the sending module is used to send the first subcommand to the first hardware domain, and the first subcommand is used to instruct the IP core of the first hardware domain to enter a dormant state;

[0031] The sending module is used to send a second subcommand to the first hardware domain, where the second subcommand is used to instruct the CPU of the first hardware domain to enter a sleep state.

[0032] In some optional embodiments, the acquisition module is used to modify the configuration information of the register on the multi-core heterogeneous chip, and the modified configuration information is used to indicate that the real-time domain has the operation permission for the memory;

[0033] The operation authority at least includes: an authority to write data to the memory.

[0034] In some optional embodiments, the storage module is used to store the data corresponding to the first hardware domain in the boot partition of the memory.

[0035] In some optional embodiments, the storage module is used to store data corresponding to the first hardware domain in a first partition of the memory.

[0036] In some optional embodiments, the data storage device of the multi-core heterogeneous chip further includes: a processing module, configured to compare the data corresponding to the first hardware domain stored in the boot partition with the data corresponding to the first hardware domain stored in the first partition to obtain a comparison result;

[0037] The reliability of the data stored in the memory is confirmed based on the comparison result.

[0038] In a third aspect, an embodiment of the present application provides a multi-core heterogeneous chip, wherein the multi-core heterogeneous chip comprises:

[0039] processor, memory, and bus;

[0040] The memory stores executable instructions;

[0041] The processor communicates with the memory via the bus, and when the processor executes the executable instructions stored in the memory, the above-mentioned data storage method for the multi-core heterogeneous chip is implemented.

[0042] In a fourth aspect, an embodiment of the present application provides a component on a transportation device, wherein the component includes a multi-core heterogeneous chip, and the multi-core heterogeneous chip can implement the above-mentioned multi-core heterogeneous chip data storage method.

[0043] In a fifth aspect, an embodiment of the present application provides an electronic device, which includes a multi-core heterogeneous chip, and the multi-core heterogeneous chip can implement the above-mentioned multi-core heterogeneous chip data storage method.

[0044] The data storage method of a multi-core heterogeneous chip provided in an embodiment of the present application, the multi-core heterogeneous chip includes at least a real-time domain and a first hardware domain, the method includes: the analog-to-digital conversion module on the real-time domain detects the power supply voltage of the multi-core heterogeneous chip; compares the power supply voltage with the voltage threshold; when the power supply voltage is less than the threshold voltage, the real-time domain sends a first command to the first hardware domain, the first command is used to instruct the first hardware domain to enter a dormant state; in the dormant state, some or all functions of the first hardware domain are in a non-operating state; the real-time domain obtains the operation permission of the memory corresponding to the multi-core heterogeneous chip; the real-time domain stores the data corresponding to the first hardware domain in the memory; wherein, when the multi-core heterogeneous chip is running, the power consumption of the real-time domain is less than the power consumption of the first hardware domain. In the embodiment of the present application, there is no need to introduce an external circuit or a backup battery, and the real-time domain in the multi-core heterogeneous chip can be used to perform data storage; the analog-to-digital conversion module inside the real-time domain is used to monitor the power supply voltage of the multi-core heterogeneous chip, so that the monitoring speed is faster and the real-time performance is stronger. When it is detected that the power supply voltage of the multi-core heterogeneous chip is lower than the threshold voltage, all high-power IP cores are turned off, the overall power consumption of the multi-core heterogeneous chip is reduced, the power failure of the multi-core heterogeneous chip is slowed down, and the effective operation time slot of the CPU is greatly improved, thereby realizing rapid data storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a schematic diagram of a processing flow of a data storage method for a multi-core heterogeneous chip provided in an embodiment of the present application;

[0046] Figure 2It is another processing flow diagram of the data storage method of the multi-core heterogeneous chip provided in the embodiment of the present application;

[0047] Figure 3 This is a schematic diagram of a specific processing flow for data storage in a real-time domain provided by an embodiment of the present application;

[0048] Figure 4 It is a schematic diagram of time slots for data storage in the prior art;

[0049] Figure 5 It is a schematic diagram of time slots for data storage using an embodiment of the present application;

[0050] Figure 6 It is a detailed processing flow diagram of the data storage method of the multi-core heterogeneous chip provided in the embodiment of the present application;

[0051] Figure 7 It is a schematic diagram of the composition structure of the data storage device of the multi-core heterogeneous chip provided in the embodiment of the present application;

[0052] Figure 8 It is a schematic diagram of the structure of a multi-core heterogeneous chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0054] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0055] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0057] It should be understood that in the various embodiments of the present application, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0058] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0059] 1) In the embodiments of the present application, a multi-core heterogeneous chip refers to a chip that integrates two or more processor cores in a single chip, and each processor core can act as an independent processor to independently run the instructions stored in the memory corresponding to the processor core. Multi-core heterogeneous chips can bring more combined advantages such as performance, cost, power consumption, and size. Different architectures perform their respective functions and each plays the unique advantages of the original architecture.

[0060] The multi-core heterogeneous chip in the embodiment of the present application can be applied to transportation equipment, including but not limited to balancing vehicles, cars, buses, subways, trains, and airplanes.

[0061] 2) Hardware domain, which is a set of hardware collections. The hardware collection may include hardware resources such as processor cores, interrupt controllers, clock controllers, and memory. The number of processor cores in the hardware collection may be one or more. One hardware domain runs one operating system, and different hardware domains may run different operating systems. Hardware domains may include real-time domains, which run real-time operating systems. Real-time operating systems are operating systems designed specifically to handle real-time tasks.

[0062] The IP cores in each hardware domain are divided into large cores and small cores. The large cores are suitable for running operating systems with high performance, while the small cores are suitable for running operating systems with low performance, high speed and greater security. Information is transmitted between different hardware domains through inter-core communication channels.

[0063] 3) IP core refers to the mature design of a circuit module with independent functions in a chip, which is verified, reusable and has specific functions. The circuit module design can be applied to other chip design projects that contain the circuit module, thereby reducing the design workload, shortening the design cycle, and improving the success rate of chip design. IP core can also be understood as an intermediate component of chip design.

[0064] 4) Inter-core communication: There is a need for information communication between different hardware domains. The communication method between hardware domains is called inter-core communication. Inter-core communication has more advantages than communication between chips. For example, it does not need to transmit data outside the chip, which greatly improves the security and speed of data transmission. There are many forms of inter-core communication, such as the Mailbox mechanism suitable for transmitting instructions and the shared memory mechanism suitable for sharing data.

[0065] Mailbox is a mechanism or data structure used for communication between different processing cores. It can be used to pass messages and trigger events between different processors, cores or hardware modules.

[0066] Mailbox can be viewed as a shared, bidirectional communication interface that contains one or more registers for storing messages or control information. The sender can write messages into the registers of the Mailbox, and the receiver can read these messages and process them accordingly. That is, the sender can control the receiver or instruct the receiver to perform corresponding operations by writing messages or control information into the registers of the Mailbox.

[0067] In semiconductor chips, Mailbox is often used for communication between processors, such as between multi-core processors, SoCs, or multiple independent functional modules. Through the Mailbox mechanism, different processing units can work together, share data, synchronize operations, and trigger events, thereby achieving more efficient system collaboration and resource sharing.

[0068] It should be noted that the implementation of Mailbox may vary depending on the chip architecture, communication protocol or design requirements, but in general, it exists to achieve reliable and efficient communication and data exchange between processing units.

[0069] In related technologies, with the popularity of smart cars, there are more and more electronic devices such as vehicle terminals, which usually store important parameters of the vehicle, such as real-time status parameters of the vehicle, navigation information, etc. However, when a vehicle collides or the electronic device suddenly loses power, it is particularly important to store the important parameters of the vehicle. If a multi-core heterogeneous system is running on the chip of the vehicle, multiple operating systems will run on one chip, and each operating system will run independently of each other. The data in each operating system is numerous and complex; therefore, the data that needs to be saved is also huge.

[0070] Usually, a peripheral circuit can be used to monitor the analog-to-digital converter (ADC), but the response time of the ADC is relatively slow.

[0071] Alternatively, a backup battery can be used for power-off protection, but the backup battery circuit is complex and costly, and if you forget to replace the backup battery, the battery will be dead and power-off protection cannot be provided.

[0072] It is also possible to implement power-off protection based on supercapacitors. For example, by utilizing the common functions of the vehicle power supply, the supercapacitor can be used as a conventional power filter capacitor to implement the power-off protection function of the vehicle computer. However, this method introduces an external circuit, which not only increases the cost, but also increases the complexity of the circuit.

[0073] The data storage method for a multi-core heterogeneous chip provided in the embodiment of the present application can at least solve the above problems.

[0074] A processing flow diagram of a data storage method for a multi-core heterogeneous chip provided in an embodiment of the present application is as follows: Figure 1 As shown, the multi-core heterogeneous chip includes at least a real-time domain and a first hardware domain, and the method includes at least the following steps:

[0075] Step S101: an analog-to-digital conversion module in a real-time domain detects a power supply voltage of a multi-core heterogeneous chip.

[0076] In the embodiment of the present application, the IP core in the real-time domain can be a small core, and the real-time domain runs a fast, low-performance, and more secure operating system. Therefore, the power supply voltage of the multi-core heterogeneous chip is monitored by using the analog-to-digital conversion module inside the real-time domain, making the monitoring faster and more real-time.

[0077] Step S102, comparing the power supply voltage with the threshold voltage.

[0078] In some embodiments, the power supply voltage of the multi-core heterogeneous chip detected by the analog-to-digital conversion module is compared with a voltage threshold in the real-time domain, wherein the voltage threshold is determined according to a VCC range on a datasheet of the multi-core heterogeneous chip.

[0079] As an example, the data sheet of a multi-core heterogeneous chip may be shown in Table 1:

[0080] Table 1. Data sheet of multi-core heterogeneous chips with 3.3V operating voltage

[0081]

[0082]

[0083] For the voltage values ​​shown in Table 1, the allowable fluctuation range of the 3.3V operating voltage is between 80%*3.3 and 109%*3.3, and the threshold voltage can be set to 2.7V.

[0084] Step S103, when the power supply voltage is less than the threshold voltage, the real-time domain sends a first command to the first hardware domain, the first command is used to instruct the first hardware domain to enter a sleep state; in the sleep state, some or all functions of the first hardware domain are in a non-operating state.

[0085] In some embodiments, the power consumption of the first hardware domain is greater than the power consumption of the real-time domain. The real-time domain may send the first command to the first hardware domain by means of inter-core communication. The first hardware domain may be any hardware domain other than the real-time domain in a multi-core heterogeneous chip. As an example, the first hardware domain may be a central control domain, an instrument domain, or a multi-function domain in a smart car.

[0086] In some embodiments, when the first hardware domain enters the sleep state, the CPU in the first hardware domain may enter the sleep state, or the high-power IP core in the first hardware domain may enter the sleep state. The IP core and CPU in the sleep state are in a non-working or non-operating state. In the embodiment of the present application, the high-power IP core is controlled to enter the sleep state by the first command, so as to extend the time slot for data storage.

[0087] In a specific implementation, the first command may be an rpmsg command, and the first command may include a first subcommand and a second subcommand, and the first subcommand and the second subcommand may be sent by the real-time domain respectively. The real-time domain may first send the first subcommand to the first hardware domain, and the first subcommand is used to instruct the IP core of the first hardware domain to enter a sleep state; the real-time domain then sends the second subcommand to the first hardware domain, and the second subcommand is used to instruct the CPU of the first hardware domain to enter a sleep state. The IP core is a high-power IP core, such as Direct Memory Access (DMA) or Ethernet.

[0088] In the embodiment of the present application, by first controlling the high-power IP core to enter a sleep state, power consumption can be quickly reduced, and the power failure of the VCCD can be slowed down, so that the CPU controllable time is greatly increased, the security of the data is improved, and more data can be safely stored.

[0089] Step S104: the real-time domain obtains the operation permission of the memory corresponding to the multi-core heterogeneous chip.

[0090] In some embodiments, the real-time domain modifies configuration information of registers on the multi-core heterogeneous chip, and the modified configuration information is used to indicate that the real-time domain has operation permissions for the memory; the operation permissions include at least: permissions to write data to the memory.

[0091] In some embodiments, the operation permission may also include: permission to read data from the memory.

[0092] In some embodiments, the memory may be a flash memory or an embedded multimedia card (EMMC). The memory may be any form of device or component capable of storing data.

[0093] Step S105: the real-time domain stores the data corresponding to the first hardware domain into the memory.

[0094] In some embodiments, the data corresponding to the first hardware domain may be data stored in a double data rate synchronous dynamic random access memory (Double Data Rate, DDR).

[0095] In some embodiments, the real-time domain stores the data corresponding to the first hardware domain in a boot partition of the memory. Taking the memory as EMMC as an example, since the boot partition of EMMC has high stability, the data corresponding to the first hardware domain is stored in the boot partition of EMMC, so that in the subsequent analysis and data recovery process of the data corresponding to the first hardware domain, the speed of loading the data corresponding to the first hardware domain is faster.

[0096] In some embodiments, the data corresponding to the first hardware domain may include: data stored in an electronic device associated with the first hardware domain, or data stored in a component in the first hardware domain.

[0097] As an example, the multi-core heterogeneous chip can be a chip in a smart car, and the electronic device associated with the first hardware domain can be a driving recorder or other vehicle-mounted terminal. Accordingly, the data corresponding to the first hardware domain can be: vehicle navigation information, vehicle real-time status parameters, and vehicle key operating data.

[0098] In the embodiment of the present application, the time slot for data storage can be further extended by utilizing a real-time domain with relatively low power consumption to perform data storage of a multi-core heterogeneous chip.

[0099] Another processing flow diagram of the data storage method of the multi-core heterogeneous chip provided in the embodiment of the present application is as follows: Figure 2 As shown, the multi-core heterogeneous chip includes at least a real-time domain and a first hardware domain, and the method includes at least the following steps:

[0100] Step S201: an analog-to-digital conversion module in a real-time domain detects a power supply voltage of a multi-core heterogeneous chip.

[0101] Step S202, comparing the power supply voltage with the threshold voltage.

[0102] Step S203, when the power supply voltage is less than the threshold voltage, the real-time domain sends a first command to the first hardware domain, the first command is used to instruct the first hardware domain to enter a sleep state; in the sleep state, some or all functions of the first hardware domain are in a non-operating state.

[0103] Step S204: the real-time domain obtains the operation permission of the memory corresponding to the multi-core heterogeneous chip.

[0104] Step S205: The real-time domain stores the data corresponding to the first hardware domain into the memory.

[0105] In some embodiments, the specific implementation process of steps S201 to S205 is the same as that of steps S101 to S105, and will not be repeated here.

[0106] Step S206: The real-time domain stores the data corresponding to the first hardware domain in the first partition of the memory.

[0107] In some embodiments, the first partition is different from the boot partition, and the first partition may be a USER partition of the memory.

[0108] Step S207: Compare the data corresponding to the first hardware domain stored in the boot partition with the data corresponding to the first hardware domain stored in the first partition to obtain a comparison result.

[0109] In some embodiments, in the scenario of subsequent data analysis, data recovery, multi-core heterogeneous chip restart, or electronic device restart, the data corresponding to the first hardware domain stored in the boot partition can be compared with the data corresponding to the first hardware domain stored in the first partition to confirm whether the data corresponding to the first hardware domain stored in the boot partition is consistent with the data corresponding to the first hardware domain stored in the first partition.

[0110] Step S208: confirming the reliability of the data stored in the memory based on the comparison result.

[0111] In some embodiments, if the comparison result indicates that the data corresponding to the first hardware domain stored in the boot partition is consistent with the data corresponding to the first hardware domain stored in the first partition, then the data corresponding to the first hardware domain stored in the boot partition is confirmed to be reliable, and data analysis can be performed based on the data corresponding to the first hardware domain stored in the boot partition.

[0112] Based on the above steps S205 and S206, taking the memory as EMMC as an example, the specific processing flow of data storage in the real-time domain can be as follows: Figure 3 As shown, including at least:

[0113] Step S301, open the EMMC boot partition.

[0114] Step S302, storing the data in the DDR into the EMMC boot partition.

[0115] Step S303, switch the EMMC to the USER partition.

[0116] Step S304, storing the data in the DDR into the EMMC USER partition.

[0117] Step S305: the real-time domain enters the verification process.

[0118] The following is based on Figure 4 and Figure 5 The data storage method provided in the embodiment of the present application is described as being able to extend the time slot for data storage. Figure 4 Schematic diagram of the time slot of data storage in the prior art. The time for the voltage to drop from 2.9V to the threshold voltage 2.7V is t0, which is about 50us. Figure 5 A schematic diagram of a time slot for data storage using an embodiment of the present application. The time for the voltage to drop from 2.9V to the threshold voltage of 2.7V is t0, which is approximately 2000us.

[0119] The time consumption of the data storage method provided in the embodiment of the present application is analyzed below. When an abnormality occurs in the multi-core heterogeneous chip, the VCC voltage is reduced from 3.3V to 2.9V.

[0120] 1) The time required for the ADC module in the real-time domain to detect a 2.9V low-voltage event is approximately 0.5us.

[0121] 2) The real-time domain controls the high-power IP cores and CPUs in other hardware domains in the multi-core heterogeneous chip to enter sleep mode, which takes about 5us.

[0122] 3) The time required for the real-time domain to obtain the operation permission of the memory is less than 1us. Taking the storage of 256k data in the boot partition of EMMC as an example, it takes about 10us for the 64-bit DDR4-3200 memory to transfer 256KB of data. The bus width of EMMC HS400 is 8 bits, the clock frequency is 200MHz, and it takes 256*1024 / (400*1024*1024)=625us to store 256KB of data in DDR mode.

[0123] At this time, the total time required is approximately: 0.5us+5us+1us+10us+625us=641.5us.

[0124] 4) The time required to store the data into the USER partition of EMMC is also 641.5us.

[0125] Therefore, the time required to store the data in the EMMC is 2*641.5=1283us. In the embodiment of the present application, the time slot for reducing from 2.9V to 2.7V is 2000us, and after transmitting 256KB of data, there is about 700us of time margin left.

[0126] However, in the prior art, using the above algorithm for calculating the data storage duration, only 16KB of data can be stored.

[0127] The following takes the real-time domain in a multi-core heterogeneous chip as a security domain (safety domain), and the first hardware domains are respectively the secure domain, the AP1 domain, and the AP2 domain as an example to illustrate the detailed processing flow of the data storage method for a multi-core heterogeneous chip provided in an embodiment of the present application. In an embodiment of the present application, the core corresponding to the real-time domain is the safety core, and the cores corresponding to the first hardware domain are respectively the secure core, the AP1 core, and the AP2 core. The secure core runs the FreeRTOS system, the AP1 core runs the Android system, and the AP2 core runs the linusOX system. The detailed processing flow of the data storage method for a multi-core heterogeneous chip provided in an embodiment of the present application, such as Figure 6 As shown, at least the following steps are included:

[0128] Step S401, the multi-core heterogeneous system corresponding to the multi-core heterogeneous chip is powered on.

[0129] Step S402, the safety core is started.

[0130] Step S403: The safety core detects that the power supply voltage of the multi-core heterogeneous chip is less than a threshold voltage.

[0131] Step S404, the safety core controls the IP cores other than the CPU in the secure core to enter a dormant state.

[0132] Step S405 , the safety core controls the IP cores other than the CPU in the AP1 core and the AP2 core to enter a dormant state.

[0133] In the embodiment of the present application, there is no execution order for step S404 and step S405. Step S404 may be executed first, and then step S405; step S405 may be executed first, and then step S404; and step S404 and step S405 may be executed simultaneously.

[0134] Step S406, the safety core controls the CPU in the secure core to enter a sleep state.

[0135] Step S407 : the safety core controls the CPUs in the AP1 core and the AP2 core to enter a sleep state.

[0136] In the embodiment of the present application, there is no execution order for step S406 and step S407. Step S406 may be executed first, and then step S407; step S407 may be executed first, and then step S406; and step S406 and step S407 may be executed simultaneously.

[0137] It should be noted that, in the embodiment of the present application, the time for executing step S404 and step S405 is earlier than the time for executing step S406 and step S407.

[0138] Step S408: The safety core saves the data to the boot partition of the memory.

[0139] The embodiment of the present application also provides a data storage device of a multi-core heterogeneous chip, wherein the multi-core heterogeneous chip includes at least a real-time domain and a first hardware domain. The composition structure diagram of the data storage device of the multi-core heterogeneous chip is as follows: Figure 7 As shown, including:

[0140] The analog-to-digital conversion module 501 is used to detect the power supply voltage of the multi-core heterogeneous chip;

[0141] A comparison module 502, configured to compare the power supply voltage with a voltage threshold;

[0142] A sending module 503 is used to send a first command to the first hardware domain when the power supply voltage is less than the threshold voltage, wherein the first command is used to instruct the first hardware domain to enter a dormant state; in the dormant state, some or all functions of the first hardware domain are in a non-operating state;

[0143] An acquisition module 504 is used to acquire the operation permission of the memory corresponding to the multi-core heterogeneous chip;

[0144] A storage module 505, configured to store the data corresponding to the first hardware domain into the memory;

[0145] When the multi-core heterogeneous chip is running, the power consumption of the real-time domain is less than the power consumption of the first hardware domain.

[0146] In some optional embodiments, the first command includes a first subcommand and a second subcommand; the sending module is used to send the first subcommand to the first hardware domain, and the first subcommand is used to instruct the IP core of the first hardware domain to enter a dormant state;

[0147] The sending module 503 is used to send a second subcommand to the first hardware domain, where the second subcommand is used to instruct the CPU of the first hardware domain to enter a sleep state.

[0148] In some optional embodiments, the acquisition module 504 is used to modify the configuration information of the register on the multi-core heterogeneous chip, and the modified configuration information is used to indicate that the real-time domain has the operation permission for the memory;

[0149] The operation authority at least includes: an authority to write data to the memory.

[0150] In some optional embodiments, the storage module 505 is used to store the data corresponding to the first hardware domain in the boot partition of the memory.

[0151] In some optional embodiments, the storage module 505 is used to store the data corresponding to the first hardware domain in the first partition of the memory.

[0152] In some optional embodiments, the data storage device of the multi-core heterogeneous chip further includes: a processing module 506, configured to compare the data corresponding to the first hardware domain stored in the boot partition with the data corresponding to the first hardware domain stored in the first partition to obtain a comparison result;

[0153] The reliability of the data stored in the memory is confirmed based on the comparison result.

[0154] In the embodiment of the present application, the data storage device of the multi-core heterogeneous chip can be located in the real-time domain of the multi-core heterogeneous chip.

[0155] The present application also provides a multi-core heterogeneous chip, and a schematic diagram of the structure of the multi-core heterogeneous chip, such as Figure 8 As shown, it includes: a processor 410, a memory 450 and a bus 440; each module in the multi-core heterogeneous chip is coupled together through the bus 440. It can be understood that the bus 440 is used to realize the connection and communication between these modules. In addition to the data bus, the bus 440 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 8 Various buses are labeled as bus 440.

[0156] The processor 410 has signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware models, etc., where the general-purpose processor can be a microprocessor or any conventional processor, etc.

[0157] The memory 450 stores executable instructions for implementing the cross-hardware domain shared memory management method provided in the embodiment of the present application. The cross-hardware domain shared memory management method can be implemented by Figure 7The analog-to-digital conversion module 501, the comparison module 502, the sending module 503, the acquisition module 504 and the storage module 505 in the data storage device of the multi-core heterogeneous chip shown are implemented; the memory 450 can be removable, non-removable or a combination thereof. Exemplary hardware devices include solid-state memory, hard disk drive, optical disk drive, etc. The memory 450 optionally includes one or more storage devices that are physically far away from the processor 410.

[0158] In some embodiments, memory 450 is capable of storing data to support various operations, examples of which include programs, modules, and data structures, or a subset or superset thereof.

[0159] In some embodiments, the multi-core heterogeneous chip may further include:

[0160] Operating system 451, including system programs for processing various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks;

[0161] The network communication module 452 is used to reach other computing devices via one or more (wired or wireless) network interfaces 420. Exemplary network interfaces 420 include: Bluetooth, Wireless Authentication (WiFi), and Universal Serial Bus (USB).

[0162] An embodiment of the present application also provides a component on a transportation device, wherein the component includes a multi-core heterogeneous chip, and the multi-core heterogeneous chip can execute the data storage method of the multi-core heterogeneous chip.

[0163] In some optional embodiments, the components may be components at the circuit board level, components at the automotive electrical system level, or components of an automotive assembly. As an example, the components may be the engine, chassis, body, and electrical and electronic equipment of the vehicle. The electrical and electronic equipment of the vehicle may include headlights for lighting, management equipment for controlling the engine, central control equipment for receiving broadcasts, navigation, listening to music, entertainment, etc.

[0164] The embodiment of the present application also provides an electronic device, the electronic device includes a multi-core heterogeneous chip, and the multi-core heterogeneous chip can execute the data storage method of the multi-core heterogeneous chip. The electronic device can be a transportation device, and the transportation device includes but is not limited to a balance car, a car, a bus, a train or an airplane.

[0165] The present application embodiment provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored. When the executable instructions are executed by a processor, the processor will be triggered to execute the data storage method of the multi-core heterogeneous chip provided in the present application embodiment, for example, Figures 1 to 6 A data storage method for a multi-core heterogeneous chip is shown.

[0166] In some embodiments, the computer-readable storage medium may be a ferroelectric random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disk, or a CD-ROM; it may also be various devices including one or any combination of the above memories.

[0167] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, model, subroutine or other unit suitable for use in a computing environment.

[0168] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0169] An embodiment of the present application provides a computer program product, which includes a computer program / instruction. When the computer program / instruction is executed by a processor, the data storage method for a multi-core heterogeneous chip described in the present application is implemented.

[0170] The above are only embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present application are included in the protection scope of the present application.

Claims

1. A data storage method for a multi-core heterogeneous chip, It is characterized in that The multi-core heterogeneous chip includes at least a real-time domain and a first hardware domain, and the method includes: The analog-to-digital conversion module in the real-time domain detects the power supply voltage of the multi-core heterogeneous chip; Comparing the power supply voltage with a voltage threshold; When the power supply voltage is less than the threshold voltage, the real-time domain sends a first command to the first hardware domain, wherein the first command is used to instruct the first hardware domain to enter a sleep state; in the sleep state, some or all functions of the first hardware domain are in a non-operating state; The real-time domain obtains the operation authority of the memory corresponding to the multi-core heterogeneous chip; The real-time domain stores the data corresponding to the first hardware domain into the memory; When the multi-core heterogeneous chip is running, the power consumption of the real-time domain is less than the power consumption of the first hardware domain.

2. The method according to claim 1, It is characterized in that The first command includes a first subcommand and a second subcommand; the real-time domain sends the first command to the first hardware domain, including: The real-time domain sends a first subcommand to the first hardware domain, where the first subcommand is used to instruct the intellectual property IP core of the first hardware domain to enter a dormant state; The real-time domain sends a second subcommand to the first hardware domain, where the second subcommand is used to instruct a central processing unit (CPU) of the first hardware domain to enter a sleep state.

3. The method according to claim 1, It is characterized in that The real-time domain obtains the operation authority of the memory corresponding to the multi-core heterogeneous chip, including: The real-time domain modifies configuration information of a register on the multi-core heterogeneous chip, where the modified configuration information is used to indicate that the real-time domain has operation authority for the memory; The operation authority at least includes: an authority to write data to the memory.

4. The method according to claim 1, It is characterized in that The real-time domain stores the data corresponding to the first hardware domain in the memory, including: The real-time domain stores the data corresponding to the first hardware domain in the boot partition of the memory.

5. The method according to claim 4, It is characterized in that The real-time domain stores the data corresponding to the first hardware domain in the memory, including: The real-time domain stores data corresponding to the first hardware domain in a first partition of the memory.

6. The method according to claim 5, It is characterized in that The method further comprises: Comparing the data corresponding to the first hardware domain stored in the boot partition with the data corresponding to the first hardware domain stored in the first partition to obtain a comparison result; The reliability of the data stored in the memory is confirmed based on the comparison result.

7. A data storage device for a multi-core heterogeneous chip, It is characterized in that The multi-core heterogeneous chip includes at least a real-time domain and a first hardware domain, and the data storage device of the multi-core heterogeneous chip includes: An analog-to-digital conversion module, used to detect the power supply voltage of the multi-core heterogeneous chip; A comparison module, used for comparing the power supply voltage with a voltage threshold; a sending module, configured to send a first command to the first hardware domain when the power supply voltage is less than the threshold voltage, wherein the first command is used to instruct the first hardware domain to enter a dormant state; in the dormant state, some or all functions of the first hardware domain are in a non-operating state; An acquisition module, used to obtain the operation permission of the memory corresponding to the multi-core heterogeneous chip; A storage module, used for storing the data corresponding to the first hardware domain into the memory; When the multi-core heterogeneous chip is running, the power consumption of the real-time domain is less than the power consumption of the first hardware domain.

8. A multi-core heterogeneous chip, It is characterized in that The multi-core heterogeneous chip includes: a processor, a memory and a bus; The memory stores executable instructions; The processor communicates with the memory via the bus, and when the processor executes the executable instructions stored in the memory, the data storage method for a multi-core heterogeneous chip according to any one of claims 1 to 6 is implemented.

9. A component of a traffic device, It is characterized in that The component includes a multi-core heterogeneous chip, and the multi-core heterogeneous chip can implement the data storage method of the multi-core heterogeneous chip according to any one of claims 1 to 6.

10. An electronic device, It is characterized in that The electronic device comprises a multi-core heterogeneous chip, and the multi-core heterogeneous chip can implement the data storage method of the multi-core heterogeneous chip according to any one of claims 1 to 6.

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