A storage device and data reading method thereof

Abstract

The present invention provides a storage device and a data reading method thereof, wherein the storage device comprises: a flash memory particle, provided with a page register, the page register is used to temporarily store host data in a storage page of the flash memory particle; a main controller, provided with a read cache area, the read cache area is used to temporarily store part of the host data in the page register; wherein the main controller is used to respond to a read instruction of the host to obtain a logical address segment; the main controller is also used to sequentially query the mapping relationship of the logical address segment to obtain the host data in the storage page corresponding to the starting logical block address in the query, and write the host data into the page register; the main controller is also used to write part of the physical block address mapped by the logical address segment in the page register into the read cache area; the main controller is also used to transmit the data in the read cache area to the host when the read cache area is full. The present invention can improve the data processing speed and enhance the reading performance of the storage device.

Description

Technical Field

[0001] The present invention relates to the field of static storage technology, and in particular to a storage device and a data reading method thereof. Background Art

[0002] When the host initiates a read command to obtain data from the storage device, the storage device will follow the Logical Block Addressing (LBA) sequence to organize the required data and then transmit it to the host. However, if the LBA data recorded in a page in the NAND Flash storage device is not physically continuous, this may cause the storage device to repeatedly read the same page to ensure that the data is submitted in the correct LBA data order. This process will consume additional reading time and significantly weaken the reading performance of the storage device. For example, in a video playback scenario, it may cause loading delays and unsmooth playback, affecting the user experience. Therefore, there is room for improvement. Summary of the invention

[0003] The present invention provides a storage device and a data reading method thereof, so as to solve the technical problem in the prior art that the reading performance of the storage device is reduced due to repeated reading of the same page.

[0004] The present invention provides a storage device, comprising:

[0005] The flash memory particle is provided with a page register, and the page register is used to temporarily store the host data in the storage page of the flash memory particle;

[0006] A main controller is provided with a read cache area, wherein the read cache area is used to temporarily store part of the host data in the page register;

[0007] Wherein, the main controller is used to respond to a read instruction of the host to obtain a logical address segment, wherein the logical address segment represents a plurality of continuous sequences of logical block addresses;

[0008] The main controller is also used to query the mapping relationship of the logical address segments in sequence to obtain the host data in the storage page corresponding to the starting logical block address in the query, and write the host data into the page register, wherein the host data in the storage page includes a plurality of physical block addresses;

[0009] The main controller is further used to write part of the physical block addresses mapped by the logical address segment in the page register into the read cache area, wherein the part of the physical block addresses includes the physical block addresses mapped by the starting logical block address and the physical block addresses mapped by other logical block addresses, and the other logical block addresses meet the following conditions: their serial numbers are within the range of the logical address segment, and their serial numbers are less than or equal to the sum of the serial number of the starting logical block address and the number of sectors in the read cache area;

[0010] The main controller is further configured to transmit the data in the read cache area to the host when the read cache area is full.

[0011] In one embodiment of the present invention, the main controller is further configured to obtain a storage page corresponding to the starting logic block address when a mapping relationship of the starting logic block address exists in a data mapping table stored therein;

[0012] The main controller is further configured to query whether the data mapping table stored in the flash memory particle has a mapping relationship of the starting logical block address when the data mapping table stored therein does not have a mapping relationship of the starting logical block address.

[0013] In one embodiment of the present invention, the main controller is further used to determine whether the mapping relationship between the other logical block address and the storage page corresponding to the start logical block address is the latest mapping relationship when the data mapping table stored therein has the mapping relationship of the other logical block address;

[0014] The main controller is further configured to write the physical block address mapped by the other logical block address into the read cache area when there is a latest mapping relationship between the other logical block address and the storage page corresponding to the start logical block address.

[0015] In one embodiment of the present invention, the main controller is further used to determine whether the data mapping table stored in the flash memory particle has a mapping relationship for the other logical block addresses when it is determined that the data mapping table stored therein does not have a mapping relationship for the other logical block addresses.

[0016] In one embodiment of the present invention, the main controller is further configured to obtain a storage page corresponding to the starting logic block address when a mapping relationship of the starting logic block address exists in a data mapping table stored in the flash memory particle;

[0017] The main controller is further configured to write all-0 data into a sector corresponding to the read cache area with the starting logic block address when the data mapping table stored in the flash memory particle does not have a mapping relationship of the starting logic block address.

[0018] In one embodiment of the present invention, the main controller is further configured to repeatedly query the mapping relationship of the logical address segment to obtain the physical block address of the next logical block address mapping when the read cache area is not full.

[0019] The present invention also provides a method for reading data from a storage device, comprising:

[0020] Responding to a read instruction from a host to obtain a logical address segment, wherein the logical address segment represents a plurality of continuous sequences of logical block addresses;

[0021] Query the mapping relationship of the logical address segments in sequence to obtain the host data in the storage page corresponding to the starting logical block address in the query, and write the host data into the page register, wherein the host data in the storage page includes a plurality of physical block addresses;

[0022] Writing part of the physical block addresses mapped by the logical address segment in the page register into the read cache area, wherein the part of the physical block addresses written into the read cache area include the physical block addresses mapped by the starting logical block address and the physical block addresses mapped by other logical block addresses, and the other logical block addresses satisfy: their serial numbers are within the range of the logical address segment, and their serial numbers are less than or equal to the sum of the serial number of the starting logical block address and the number of sectors in the read cache area;

[0023] When the read cache area is full, the data in the read cache area is transmitted to the host.

[0024] In one embodiment of the present invention, the step of sequentially querying the mapping relationship of the logical address segments to obtain the host data in the storage page corresponding to the starting logical block address in the query, and writing the host data into the page register, wherein the host data in the storage page includes multiple physical block addresses, comprises:

[0025] Querying whether a data mapping table stored in the main controller has a mapping relationship of the starting logic block address;

[0026] When a mapping relationship of the starting logic block address exists in the data mapping table stored in the main controller, obtaining a page corresponding to the starting logic block address;

[0027] When the mapping relationship of the starting logical block address does not exist in the data mapping table stored in the main controller, query whether the data mapping table stored in the flash memory particle has the mapping relationship of the starting logical block address;

[0028] When a mapping relationship of the starting logical block address exists in the data mapping table stored in the flash memory particle, obtaining a page corresponding to the starting logical block address;

[0029] When the mapping relationship of the starting logical block address does not exist in the data mapping table stored in the flash memory particle, all-0 data is written into the sector of the read cache area corresponding to the starting logical block address.

[0030] In one embodiment of the present invention, the step of writing part of the physical block addresses mapped by the logical address segment in the page register into the read cache area, wherein the part of the physical block addresses written into the read cache area include the physical block addresses mapped by the starting logical block address and the physical block addresses mapped by other logical block addresses, and the other logical block addresses satisfy: their serial numbers are within the range of the logical address segment, and their serial numbers are less than or equal to the sum of the serial number of the starting logical block address and the number of sectors in the read cache area, comprises:

[0031] Writing the physical block address mapped by the starting logical block address into the read cache area;

[0032] The physical block addresses mapped by the other logical block addresses are written into the read cache area.

[0033] In one embodiment of the present invention, the step of writing the physical block address mapped by the other logical block address into the read cache area includes:

[0034] Querying whether the data mapping table stored in the main controller has a mapping relationship of the other logical block addresses;

[0035] When the data mapping table stored in the main controller has a mapping relationship of the other logic block addresses, determining whether the other logic block addresses and the storage page corresponding to the start logic block address are the latest mapping relationships;

[0036] When the other logical block addresses and the storage pages corresponding to the start logical block address are in the latest mapping relationship, the physical block addresses mapped by the other logical block addresses are written into the read cache area.

[0037] As described above, a storage device and a data reading method thereof of the present invention have the following beneficial effects: the present invention can reduce the number of times a same page is read as much as possible, speed up data processing, and thus improve the reading performance of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0039] Figure 1 Shown is a structural schematic diagram of a storage device provided by the present invention.

[0040] Figure 2 Shown is a schematic diagram of the structure of a flash memory particle in an embodiment of the present invention.

[0041] Figure 3 It is a schematic diagram showing the process of transferring data from a page register to a read cache area in the prior art.

[0042] Figure 4 It is a schematic diagram showing an improved process of transferring data from a page register to a read cache area in one embodiment of the present invention.

[0043] Figure 5 Shown is a schematic structural diagram of another flash memory particle in an embodiment of the present invention.

[0044] Figure 6 Shown is a schematic flow chart of a data reading method of a storage device provided by the present invention.

[0045] Figure 7 Display as Figure 6 A schematic flow chart of a specific implementation of step S200.

[0046] Figure 8 Display as Figure 6 A schematic flow chart of a specific implementation of step S300.

[0047] Fig. 9 Display as Figure 8 A schematic flow chart of a specific implementation of step S320 in FIG. DETAILED DESCRIPTION

[0048] The following is an explanation of the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the features in the following embodiments and the embodiments can be combined with each other without conflict. It should also be understood that the terms used in the embodiments of the present invention are intended to describe specific embodiments, rather than to limit the scope of protection of the present invention. The test methods for which specific conditions are not indicated in the following examples are usually carried out under conventional conditions or according to the conditions recommended by the manufacturers.

[0049] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0050] It should be noted that the Logical Block Address (LBA) is a logical method used by the operating system or upper-layer applications to identify storage space. It provides an abstraction layer that makes data access look like directly reading and writing continuous logical addresses without having to worry about the actual distribution of data on the physical medium. The use of this logical address simplifies data management and makes the replacement or upgrade of storage devices more flexible. The Physical Block Address (PBA) refers to the actual physical storage location of data on the storage device. In flash memory particles such as NAND Flash, the physical block address directly corresponds to the physical storage block, reflecting the hardware location where the data is actually stored.

[0051] The present invention provides a storage device and a data reading method thereof, which relate to the field of static storage technology and can be specifically applied to improving the reading performance of the storage device. When a host needs to read data in a storage device, the technical solution of the present invention can reduce the number of times the same page is read as much as possible, speed up data processing, and thus improve the reading performance of the storage device. The following is a detailed description through specific embodiments.

[0052] See also Figure 1, the host 100 is in communication connection with the storage device 200. The host 100 sends a read instruction to the storage device 200, and the storage device 200 transmits the target data to the host 100 in response to the read instruction. The storage device 200 may include a main controller 210 and a flash memory particle 220. Among them, the main controller 210 can be used to manage all read and write operations, including error checking, data encryption, wear leveling, and address mapping (conversion from LBA to PBA). The main controller 210 includes a logic control unit and a hardware circuit to coordinate the communication between the storage device and the external interface (such as SATA, PCIe), and manage internal resources, such as a read cache area 211 and a page register 221. The flash memory particle 220 can be a NAND Flash flash memory, which is the most commonly used storage medium in storage devices and has the characteristics of non-volatility and high density. The flash memory particle 220 is composed of a plurality of storage blocks, and each storage block contains a plurality of storage pages. The data storage and reading operations of the flash memory particles 220 are managed by the main controller 210 through the data mapping table and the hardware control logic. A read buffer area (Read Buffer) 211 is set inside the main controller 210. The read buffer area 211 is a high-speed cache area that can be used to temporarily store data read from the flash memory particles 220 to reduce the direct access pressure of the flash memory particles 220, reduce the read delay, and improve the data transmission speed. The read buffer area 211 can play an important role in continuous reading or pre-reading operations to help improve system performance. A page register (Page Register) 221 is set inside the flash memory particles 220. The page register 221 is a temporary storage area for temporarily storing host data in the storage page during data writing or reading. During a write operation, the host data is first moved from the read buffer area 211 or the system memory to the page register 221, and then programmed into the storage page of the flash memory particles 220 at one time; during a read operation, the host data is first loaded from the storage page to the page register 221, and then quickly transferred to the read buffer area 211 or directly output to the system. The page register 221 can reduce the number of times of direct access to the storage page, thereby speeding up the data processing speed. In this embodiment, the read cache area 211 can temporarily store part of the host data read from the page register 221 .

[0053] See also Figure 2In one embodiment of the present invention, the flash memory particle 220 may include multiple planes. Each plane represents a relatively independent data read and write operation area in the flash memory particle 220, and has an independent data bus and control logic. Each plane can independently perform read, program (write) and erase operations. Therefore, in the multi-plane flash memory particle 220, different operations can be performed on different planes at the same time, which improves the parallel processing capability and thus improves the overall I / O performance of the storage device. Figure 2 As shown, each plane is provided with a corresponding page register 221 .

[0054] See also Figure 3 In the prior art, after the host 100 sends a read instruction to the storage device 200, the main controller 210 responds to the read instruction and first writes the host data in the storage page into the page register 221 (Page Register), and then moves the target read data to the read cache area 211 (Read Buffer) through DMA (Direct Memory Access) technology. However, the physical block address (PBA) stored in a storage page is usually discontinuous. In order to arrange the physical block addresses in sequence, the main controller 210 will cause a storage page to be read multiple times. For example, the host 100 sends a read instruction to the storage device 200, requesting to read LBA1, LBA2, LBA3,..., LBAm, LBAm+1,..., LBAN. Figure 1 As shown, LBA1 and LBAN are stored in Page A, and LBA2 is stored in Page B. The prior art requires that when executing a read instruction, it must be executed in the order of LBA numbers. Therefore, the main controller 210 first reads Page A to write it into the page register 221, and then writes LBA1 into the page register through DMA technology. Then, the main controller 210 reads Page B to write it into the page register 221, and then writes LBA2 into the page register through DMA technology. When it is necessary to move LBAN, because LBAN is stored in Page A, the main controller 210 needs to read Page A again to write it into the page register 221, and then write LBAN into the page register through DMA technology. Finally, the main controller 210 transmits the data in the page register to the host 100. It can be seen that in order to arrange the physical block addresses in sequence, the storage device 200 causes the same storage page to be read multiple times, which consumes additional reading time and significantly weakens the reading performance of the storage device 200.

[0055] See also Figure 1 , 24. The present invention improves the process of moving data from the page register 221 to the read cache area 211. Specifically, the host 100 sends a read command to the storage device 200 via the bus, and the read command contains the logical address segment information of the target read data, aiming to obtain data in a specific logical address sequence range. In this embodiment, the logical address segment represents a set of multiple continuous sequences of logical block addresses. For example, if the requested initial logical block address is LBA100, and the requested length is 50 continuous logical blocks, then the logical address segment covers LBA100 to LBA149. Each logical block address maps to a physical block address, and the physical block address is a fixed-size storage unit for storing data on the storage device 200, usually corresponding to a sector in the page register 221. As Figure 4 As shown, the page register 221 may include, for example, 64 sectors, and each sector may store, for example, 512B of data. The size of the storage page is equal to the size of the page register 221, and the storage page may be completely written into the page register 221, that is, the number of physical block addresses (PBA) that can be stored in each storage page is equal to the number of sectors in the page register 221, and each physical block address may be written into a corresponding sector.

[0056] It should be noted that in NAND Flash, the storage and erasure operations of data are limited by its physical structure, that is, data is written in units of storage pages, while erasure needs to be performed in units of larger storage blocks. In storage devices based on NAND Flash technology such as SSD (SolidState Drives), eMMC (Embedded MultiMediaCard), and UFS (Universal Flash Storage), the main controller maintains a data mapping table inside, which is responsible for converting LBA to actual PBA. The data mapping table is used to associate the mapping relationship between the logical address (LBA) and the physical storage location in the page. By using the logical address to query the mapping information in the data mapping table, the corresponding physical address can be found, and then the data at the corresponding physical address can be read, written, moved, and processed. Because NAND FLASH does not support overwriting, it must be erased before it can be written, and reading and writing are in pages, but erasing is in storage blocks (composed of multiple storage pages). Therefore, when it is necessary to overwrite the original data and write new data, the main controller in the storage device such as SSD will write the new data to a blank area that has been erased, and then update the mapping relationship between the logical address and the physical address, and point the logical block address to the newly written physical block address. It can be seen that with the use of storage devices, the data migration caused by the write operation may make the same logical block address mapped to different physical block addresses at different time points, that is, the logical block address and the physical block address are no longer a one-to-one mapping relationship, but a constantly changing relationship.

[0057] In one embodiment of the present invention, in the process of reading the target read data from the page to the page register 221, the main controller 210 is used to first query whether there is a mapping relationship between the starting logical block address of the current query in the data mapping table stored in itself. In this embodiment, it is defined that the page register 221 is full and transmits data to the host 100 once to complete a complete query, so the starting logical block address is defined as the logical block address initially requested to be read in this query. If there is a mapping relationship between the starting logical block address in the data mapping table stored in the main controller 210, then according to the data mapping table in the main controller 210, the storage page corresponding to the starting logical block address is obtained. If there is no mapping relationship between the starting logical block address in the data mapping table stored in the main controller 210, then further query whether there is a mapping relationship between the starting logical block address in the data mapping table stored in the flash memory particle 220. If there is a mapping relationship between the starting logical block address in the data mapping table stored in the flash memory particle 220, then according to the data mapping table in the flash memory particle 220, the storage page corresponding to the starting logical block address is obtained. If the mapping relationship of the starting logical block address does not exist in the data mapping table stored in the flash memory particle 220, all 0 data is written to the sector in the read cache area 211 corresponding to the starting logical block address, that is, all 0 data is written to the first sector in the read cache area 211.

[0058] In this embodiment, the data mapping table can be stored in the main controller 210 (Controller) and the flash memory particles 220 (NAND FLASH) of the storage device 200. As can be seen from the above, the data mapping table in the main controller 210 has the characteristics of the latest data and fast access speed. At the same time, the data mapping table in the main controller 210 also has the limitation of small amount of data and cannot cover all mapping relationships. Therefore, the main controller 210 first checks whether there is a mapping relationship of the starting logical block address of the current query in the data mapping table stored in itself. If there is a record of the starting logical block address in the data mapping table of the main controller 210, the corresponding storage page can be directly obtained according to the data mapping table information.

[0059] The main controller 210 can periodically update the data mapping table stored in the flash memory particle 220. Since the data mapping table has a large amount of data, the data mapping table stored in the main controller 210 only contains mapping information of some logical addresses and physical addresses. If no mapping relationship is found in the data mapping table of the main controller 210, it is necessary to further query the data mapping table stored in the flash memory particle 220. If there is a mapping relationship of the starting logical block address in the data mapping table of the flash memory particle 220, the corresponding storage page is obtained according to this mapping information.

[0060] In addition, in special cases, if the mapping relationship of the starting logical block address is not found in the data mapping table of the flash memory particle 220, this usually indicates that the data corresponding to the requested starting logical block address may have never been written or has been marked as invalid / deleted. At this time, the processing strategy that can be adopted is to write all 0 data to the corresponding sector in the read cache area 211 to ensure the integrity of the data reading operation.

[0061] When the main controller 210 determines the physical storage location of the data corresponding to the starting logical block address, the main controller 210 will locate the storage page where the data is located. Next, the main controller 210 will load the entire content of this storage page into the page register 221. The host data in the storage page includes multiple physical block addresses. The page register 221 is a temporary storage area in the flash memory particle 220, which is used to temporarily store the host data to be read or written for fast transmission.

[0062] In one embodiment of the present invention, in the process of moving the data in the page register 221 to the read buffer area 211, the main controller 210 first writes the physical block address mapped by the starting logical block address from the page register 221 to the read buffer area 211. Then, the physical block addresses mapped by other logical block addresses in the page are written from the page register 221 to the read buffer area 211. In this embodiment, the read buffer area (Read Buffer) 211 may include N sectors, and the host data in the page register 221 may be moved to the read buffer area 211 through the DMA technology. When the host data is written to each sector in the read buffer area 211, the main controller 210 may completely transfer the host data in the read buffer area 211 to the host 100 through the data bus. The main controller 210 executes the writing of data to the read buffer area 211 in a loop, and when the read buffer area 211 is full, the host data is transferred to the host 100 until the data transfer is completed.

[0063] In this embodiment, after the storage page corresponding to the starting logical block address is loaded into the page register 221, first, the main controller 210 extracts the physical block address corresponding to the starting logical block address and writes it into the read cache area 211. The read cache area 211 is an area reserved in the system memory for temporarily storing data read from the flash memory particles 220 so that the main controller 210 can quickly access it. Doing so can reduce the delay of reading data directly from the flash memory particles 220 and improve the data processing speed. The present invention uses technologies such as DMA (direct memory access) to achieve data movement from the page register 221 to the read cache area 211 without occupying too many resources of the main controller 210, further optimizing the efficiency of data reading.

[0064] Then, the main controller 210 will read the physical block address mapped by other logical block addresses from the page register 221, and write the physical block address to the read cache area 211. Specifically, the main controller 210 continues to query the mapping relationship of the logical block addresses of other logical block addresses in the page register 221. The present invention not only focuses on the logical block address of the current request, but also proactively checks the mapping of other logical block addresses in the page register 221 to determine whether batch or continuous data reading operations can be performed. This step helps to reduce the number of reads of the flash memory particle page and the number of queries of the data mapping table, laying the foundation for subsequent efficient data transmission.

[0065] In this embodiment, the other logical block addresses satisfy that their serial numbers are within the range of the logical address segment, and the serial numbers of the other logical block addresses are less than or equal to the sum of the serial number of the starting logical block address and the number of sectors in the read cache area 211. Specifically, the main controller 210 first obtains the mapping serial number of the remaining physical block address in the page register 221, and determines whether the mapping serial number meets the above-mentioned restriction condition. In this embodiment, the mapping serial number represents the serial number of the logical block address corresponding to the physical block address. Then, when the mapping serial number meets the above-mentioned restriction condition, the main controller 210 writes the physical block address corresponding to the other logical block address to the corresponding position of the read cache area 211. For example, the mapping serial numbers of the other physical block addresses remaining in the page register 221 can be LBA 110, LBA 115, and LBA 120, respectively, the serial number of the starting logical block address is LBA 100, the maximum serial number of the logical block address corresponding to the logical address segment of the read command is LBA112, and the number of physical block addresses that can be stored in the read cache area 211 is 15. Then the mapping sequence number of the three remaining other physical block addresses satisfies the restriction condition LBA110, and does not satisfy the restriction condition LBA 115 and LBA 120. Among them, LBA 115 does not satisfy the sequence number being within the range of the logical address segment, LBA 120 does not satisfy the sequence number being within the range of the logical address segment, and also does not satisfy the sequence number of the logical block address being less than or equal to the sum of the sequence number of the starting logical block address and the number of sectors in the read cache area 211.

[0066] In one embodiment of the present invention, the main controller 210 is responsible for maintaining a data mapping table from logical to physical addresses, and this data mapping table is dynamically updated. Whenever new data is written, the old data is marked as invalid and may be moved to a new physical location through a garbage collection process, and the mapping relationship is updated accordingly. As the storage device 200 is used, the data migration caused by the write operation may cause the same logical block address to be mapped to different physical block addresses at different time points, that is, the logical block address and the physical block address are no longer a one-to-one mapping relationship, but a constantly changing relationship. Therefore, after the serial number of the physical block address remaining in the current write page register 221 meets the above-mentioned restriction conditions, it is necessary to further detect whether the physical block address and the logical block address are the latest mapping relationship.

[0067] In this embodiment, it is determined whether the physical block addresses of other logical block addresses meet the latest mapping relationship condition. Specifically, first, the main controller 210 queries the data mapping table stored therein to determine whether there is a mapping relationship of other logical block addresses. And when there is a mapping relationship of other logical block addresses in the data mapping table stored therein, it is determined whether the mapping relationship between the other logical block addresses and the storage page corresponding to the starting logical block address is the latest mapping relationship. Then, when the mapping relationship between the other logical block addresses and the storage page corresponding to the starting logical block address is the latest mapping relationship, the main controller 210 writes the physical block address mapped by the other logical block addresses into the read cache area 211.

[0068] Further, since the amount of data in the data mapping table is large, the data mapping table stored in the main controller 210 only contains mapping information of some logical addresses and physical addresses. If the data mapping table stored in the main controller 210 does not have a mapping relationship of other logical block addresses, it is necessary to further judge whether there is a mapping relationship of other logical block addresses in the flash memory particle 220 according to the mapping table storage information in the main controller 210. It should be noted that the mapping table storage information is used to store the mapping range, storage address and mapping update status of each mapping table. When the storage device 200 is started, the main controller 210 first reads the mapping table storage information stored in the flash memory particle 220, updates the mapping table storage information during operation, and saves the updated mapping table storage information to the flash memory particle 220. In this embodiment, if it exists, in order to avoid overwriting the data in the page register 221 in the flash memory particle 220, it is necessary to directly judge whether the read cache area 211 is full, and perform subsequent steps according to the storage status of the read cache area 211. If it does not exist, the corresponding sector is filled with all 0 data.

[0069] In one embodiment of the present invention, the main controller 210 can write all the multiple physical block addresses that can be moved in the page written into the page register 221 into the read cache area 211, which may include the physical block address corresponding to the starting logical block address and the physical block addresses corresponding to other logical block addresses. It can be seen that the present invention can move as much data in a page as possible to the read cache area 211 in one reading process, reducing the number of page reads, thereby improving the reading performance of the storage device 200.

[0070] In one embodiment of the present invention, after completing the movement of the physical block addresses in a page, the main controller 210 will continue to write the mapping data of the logical block addresses into the read cache area 211 according to the serial number, and detect whether the read cache area 211 is full. Then, when the read cache area 211 is full, part of the physical block addresses in the read cache area 211 are transmitted to the host 100. Specifically, during the query process, after the main controller 210 writes all the physical block addresses that can be moved in the current page of the page register 221 into the read cache area 211, it can continue to query the mapping relationship of the logical block addresses with subsequent numbers according to the serial number in the logical address segment. If the logical block addresses with subsequent numbers have completed data movement in the previous step, the logical block addresses with this number can be directly skipped. If the logical block addresses with subsequent numbers have not been moved in the previous step, refer to the above execution process to write the corresponding data into the read cache area 211. Then, it is detected whether the read cache area 211 is full. After the read cache area 211 is full, part of the physical block addresses in the read cache area 211 are transmitted to the host 100 .

[0071] In one embodiment of the present invention, after completing a data transfer from the read cache area 211 to the host 100, it is possible to detect whether all physical block addresses associated with the logical address segment have been read. If the detection result is that the reading has not been completed, the starting logical block address is updated to the logical block address of the next query, and the data transmission is continued with reference to the above execution process until all physical block addresses associated with the logical address segment are read. If the detection result is that the reading has been completed, the response to the current read instruction ends.

[0072] See also Figure 5In one embodiment of the present invention, a page register (PageRegister) 221 and a cache register (Cache Register) 222 are provided inside the flash memory particle 220. Among them, the page register 221 is a temporary storage area for temporarily storing page data during data writing or reading. During a write operation, the host data is first moved from the read cache area 211 or the system memory to the page register 221, and then programmed into the page of the flash memory particle 220 at one time; during a read operation, the host data is first loaded from the page to the page register 221, and then quickly transferred to the read cache area 211 or directly output to the system. The cache register 222 can be configured as an intermediate buffer. In scenarios involving continuous read and write operations or the need to increase the speed of continuous data processing, the cache register 222 can be used to temporarily store data that is about to be written or just read from the storage unit and is waiting for further processing. In this embodiment, when the main controller 210 responds to a read command, it first writes the host data in the storage page to be read to the page register 221, and then moves the data of the page register 221 to the cache register 222. At this time, the vacated page register 221 can store the host data in the next storage page to be read. It can be seen that the flash memory particle 220 based on the above structure is also applicable to the data reading method provided in the above embodiment.

[0073] See also Figure 6 The present invention provides a method for reading data from a storage device, which may include the following steps:

[0074] Step S100, responding to a read instruction from a host to obtain a logical address segment, where the logical address segment represents a plurality of continuous sequences of logical block addresses;

[0075] Step S200, sequentially querying the mapping relationship of the logical address segments to obtain the host data in the storage page corresponding to the starting logical block address in the query, and writing the host data into the page register, wherein the host data in the storage page includes a plurality of physical block addresses;

[0076] Step S300, writing part of the physical block addresses mapped by the logical address segment in the page register into the read cache area, wherein the part of the physical block addresses written into the read cache area include the physical block addresses mapped by the starting logical block address and the physical block addresses mapped by other logical block addresses, and the other logical block addresses meet the following conditions: their serial numbers are within the range of the logical address segment, and their serial numbers are less than or equal to the sum of the serial number of the starting logical block address and the number of sectors in the read cache area;

[0077] Step S400: When the read cache area is full, the data in the read cache area is transmitted to the host.

[0078] In one embodiment of the present invention, when step S100 is executed, that is, in response to a read instruction from the host, a logical address segment is obtained, and the logical address segment represents a plurality of continuous sequences of logical block addresses. Specifically, the host 100 sends a read command to the storage device 200 via the bus, and the read command contains the logical address segment information of the target read data, aiming to obtain data in a specific logical address sequence range. In this embodiment, the logical address segment represents a set of logical block addresses in a plurality of continuous sequences. Each logical block address maps a fixed-size storage unit of data on a storage device 200, usually corresponding to a sector in the storage device 200. For example, if the requested initial logical block address is LBA100 and the requested length is 50 continuous logical blocks, then the logical address segment covers LBA100 to LBA149.

[0079] See also Figure 7 In one embodiment of the present invention, when executing step S200, the mapping relationship of the logical address segments is sequentially queried to obtain the host data in the storage page corresponding to the starting logical block address in the query, and the host data is written into the page register. The host data in the storage page includes multiple physical block addresses. Specifically, the following steps may be included:

[0080] Step S210, querying whether there is a mapping relationship of the starting logical block address in the data mapping table stored in the main controller;

[0081] Step S220: when there is a mapping relationship of the starting logical block address in the data mapping table stored in the main controller, obtain a page corresponding to the starting logical block address;

[0082] Step S230: when there is no mapping relationship of the starting logical block address in the data mapping table stored in the main controller, query whether there is a mapping relationship of the starting logical block address in the data mapping table stored in the flash memory particle;

[0083] Step S240: when there is a mapping relationship of the starting logical block address in the data mapping table stored in the flash memory particle, obtain a page corresponding to the starting logical block address;

[0084] Step S250: When there is no mapping relationship of the starting logical block address in the data mapping table stored in the flash memory particle, write all-0 data into the sector of the read cache area corresponding to the starting logical block address.

[0085] In one embodiment of the present invention, when executing step S210 to step S220, specifically, the data mapping table can be stored in the main controller 210 (Controller) and the flash memory particle 220 (NAND FLASH) of the storage device 200. Among them, the data mapping table stored in the main controller 210 has the characteristics of the latest data and fast access speed. The main controller 210 can regularly update the data mapping table stored in the NAND FLASH chip. At the same time, the data mapping table in the main controller 210 has the limitation of less data volume and cannot cover all mapping relationships. In this embodiment, the main controller 210 first checks whether there is a mapping relationship of the starting logical block address of the current query in the data mapping table stored in itself. The starting logical block address is the LBA initially requested to read in this query. If there is a record of the starting logical block address in the data mapping table of the main controller 210, the corresponding storage page can be directly obtained according to the data mapping table information.

[0086] In one embodiment of the present invention, when executing step S230 to step S240, specifically, since the data amount of the data mapping table is large, the data mapping table stored in the main controller 210 only contains mapping information of part of the logical address and the physical address. If no mapping relationship is found in the data mapping table of the main controller 210, it is necessary to further query the data mapping table stored in the flash memory particle 220. If there is a mapping relationship of the starting logical block address in the data mapping table of the flash memory particle 220, the corresponding storage page is obtained according to this mapping information.

[0087] In one embodiment of the present invention, when executing step S250, specifically, in special cases, if the mapping relationship of the starting logical block address is not found in the data mapping table of the flash memory particle 220, this usually indicates that the data corresponding to the requested starting logical block address may have never been written, or has been marked as invalid / deleted. At this time, the processing strategy that can be adopted is to write all 0 data to the corresponding sector in the read cache area 211 to ensure the integrity of the data reading operation.

[0088] When the main controller 210 determines the physical storage location of the data corresponding to the starting logical block address, the main controller 210 will locate the storage page where the data is located. Next, the main controller 210 will load the entire content of this storage page into the page register 221. The page register 221 is a temporary storage area in the flash memory particle 220, which is used to temporarily store the host data to be read or written for fast transmission.

[0089] See also Figure 8In one embodiment of the present invention, when executing step S300, part of the physical block addresses mapped by the logical address segment in the page register are written into the read cache area, wherein the part of the physical block addresses written into the read cache area include the physical block addresses mapped by the starting logical block address and the physical block addresses mapped by other logical block addresses, and the other logical block addresses meet the following conditions: their serial numbers are within the range of the logical address segment, and their serial numbers are less than or equal to the sum of the serial numbers of the starting logical block address and the number of sectors in the read cache area. Specifically, the following steps may be included:

[0090] Step S310, writing the physical block address mapped by the starting logical block address into the read cache area;

[0091] Step S320: Write the physical block addresses mapped by other logical block addresses into the read cache area.

[0092] In one embodiment of the present invention, when executing step S310 to step S320, specifically, in the process of moving the data in the page register 221 to the read cache area 211, the main controller 210 first writes the physical block address mapped by the starting logical block address from the page register 221 to the read cache area 211. Then, the physical block addresses mapped by other logical block addresses in the page are written from the page register 221 to the read cache area 211. In this embodiment, when the storage page corresponding to the starting logical block address is loaded into the page register 221, first, the main controller 210 extracts the physical block address corresponding to the starting logical block address from it and writes it into the read cache area 211. The read cache area 211 is an area reserved in the system memory for temporarily storing data read from the flash memory particles 220 so that the main controller 210 can quickly access it. This can reduce the delay of reading data directly from the flash memory particles 220 and improve the data processing speed. The present invention uses technologies such as DMA (direct memory access) to achieve data movement from the page register 221 to the read cache area 211 without occupying too many resources of the main controller 210, further optimizing the efficiency of data reading.

[0093] Then, the main controller 210 will read the physical block address mapped by other logical block addresses from the page register 221, and write the physical block address to the read cache area 211. Specifically, the main controller 210 continues to query the mapping relationship of the logical block addresses of other logical block addresses in the page register 221. The present invention not only focuses on the logical block address of the current request, but also proactively checks the mapping of other logical block addresses in the page register 221 to determine whether batch or continuous data reading operations can be performed. This step helps to reduce the number of reads of the flash memory particle page and the number of queries of the data mapping table, laying the foundation for subsequent efficient data transmission.

[0094] In this embodiment, the other logical block addresses satisfy that their serial numbers are within the range of the logical address segment, and the serial numbers of the other logical block addresses are less than or equal to the sum of the serial number of the starting logical block address and the number of sectors in the read cache area 211. Specifically, the main controller 210 first obtains the mapping serial number of the remaining physical block address in the page register 221, and determines whether the mapping serial number meets the above-mentioned restriction condition. In this embodiment, the mapping serial number represents the serial number of the logical block address corresponding to the physical block address. Then, when the mapping serial number meets the above-mentioned restriction condition, the main controller 210 writes the physical block address corresponding to the other logical block address to the corresponding position of the read cache area 211. For example, the mapping serial numbers of the other physical block addresses remaining in the page register 221 can be LBA 110, LBA 115, and LBA 120, respectively, the serial number of the starting logical block address is LBA 100, the maximum serial number of the logical block address corresponding to the logical address segment of the read command is LBA112, and the number of physical block addresses that can be stored in the read cache area 211 is 15. Then the mapping sequence number of the three remaining other physical block addresses satisfies the restriction condition LBA110, and does not satisfy the restriction condition LBA 115 and LBA 120. Among them, LBA 115 does not satisfy the sequence number being within the range of the logical address segment, LBA 120 does not satisfy the sequence number being within the range of the logical address segment, and also does not satisfy the sequence number of the logical block address being less than or equal to the sum of the sequence number of the starting logical block address and the number of sectors in the read cache area 211.

[0095] See also Fig. 9 In one embodiment of the present invention, in the process of executing step S320, that is, reading the physical block addresses mapped by other logical block addresses from the page register 221, it is also necessary to determine whether the physical block addresses of other logical block addresses meet the latest mapping relationship condition. Specifically, the following steps may be included:

[0096] Step S321, querying the data mapping table stored in the main controller to see whether there is a mapping relationship of other logical block addresses;

[0097] Step S322: when the data mapping table stored in the main controller has a mapping relationship of other logical block addresses, determine whether the mapping relationship between the other logical block addresses and the storage page corresponding to the start logical block address is the latest mapping relationship;

[0098] Step S323: When the other logical block addresses and the storage pages corresponding to the start logical block address are in the latest mapping relationship, the physical block addresses mapped by the other logical block addresses are written into the read cache area.

[0099] In one embodiment of the present invention, when executing step S310 to step S330, specifically, first, the main controller 210 queries whether there is a mapping relationship of other logical block addresses in the data mapping table stored therein. And when there is a mapping relationship of other logical block addresses in the data mapping table stored therein, it is determined whether the mapping relationship between the other logical block addresses and the storage page corresponding to the starting logical block address is the latest mapping relationship. Then, when the mapping relationship between the other logical block addresses and the storage page corresponding to the starting logical block address is the latest mapping relationship, the main controller 210 writes the physical block address mapped by the other logical block addresses into the read cache area 211.

[0100] Furthermore, since the data mapping table has a large amount of data, the data mapping table stored in the main controller 210 only contains mapping information of some logical addresses and physical addresses. If the data mapping table stored in the main controller 210 does not have a mapping relationship of other logical block addresses, it is necessary to further determine whether there is a mapping relationship of other logical block addresses in the flash memory particle 220 based on the recorded information. If so, in order to avoid overwriting the data in the page register 221 in the flash memory particle 220, it is necessary to directly determine whether the read cache area 211 is full, and perform subsequent steps according to the storage status of the read cache area 211. If not, the corresponding sector is filled with all 0 data.

[0101] In one embodiment of the present invention, when step S400 is executed, that is, when the read cache area is full, part of the physical block address is transmitted to the host. Specifically, after completing the physical block address transfer within a page, the main controller 210 will continue to write the mapping data of the logical block address into the read cache area 211 according to the sequence number, and detect whether the read cache area 211 is full. Then, when the read cache area 211 is full, part of the physical block address in the read cache area 211 is transmitted to the host 100. Specifically, during the query process, after the main controller 210 writes all the physical block addresses that can be transferred in the current page of the page register 221 into the read cache area 211, it can continue to query the mapping relationship of the logical block address with the subsequent number according to the sequence number in the logical address segment. If the logical block address with the subsequent number has completed data transfer in the previous step, the logical block address with the number can be directly skipped. If the logical block address with the subsequent number has not been transferred in the previous step, refer to the above execution process to write the corresponding data into the read cache area 211. Then, it is detected whether the read cache area 211 is full. After the read cache area 211 is full, part of the physical block addresses in the read cache area 211 are transmitted to the host 100 .

[0102] In one embodiment of the present invention, before executing step S400 , that is, when the read cache area 211 is not full, the main controller 210 may be used to repeatedly query the mapping relationship of the logical address segment to obtain the physical block address of the next logical block address mapping.

[0103] In one embodiment of the present invention, after completing a data transfer from the read cache area 211 to the host 100, it is possible to detect whether all physical block addresses associated with the logical address segment have been read. If the detection result is that the reading has not been completed, the starting logical block address is updated to the logical block address of the next query, and the data transmission is continued with reference to the above execution process until all physical block addresses associated with the logical address segment are read. If the detection result is that the reading has been completed, the response to the current read instruction ends.

[0104] In summary, the present invention proposes a storage device and a data reading method thereof, which relates to the field of static storage technology and can be specifically applied to improving the reading performance of the storage device. When the host needs to read data in the storage device, the technical solution of the present invention can reduce the number of reads of the same storage page as much as possible, speed up data processing, and thus improve the reading performance of the storage device.

[0105] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A storage device, characterized in that: include: The flash memory particle is provided with a page register, and the page register is used to temporarily store the host data in the storage page of the flash memory particle; A main controller is provided with a read cache area, wherein the read cache area is used to temporarily store part of the host data in the page register; Wherein, the main controller is used to respond to a read instruction of the host to obtain a logical address segment, wherein the logical address segment represents a plurality of continuous sequences of logical block addresses; The main controller is also used to query the mapping relationship of the logical address segments in sequence to obtain the host data in the storage page corresponding to the starting logical block address in the query, and write the host data into the page register, wherein the host data in the storage page includes a plurality of physical block addresses; The main controller is further used to write part of the physical block addresses mapped by the logical address segment in the page register into the read cache area, wherein the part of the physical block addresses includes the physical block addresses mapped by the starting logical block address and the physical block addresses mapped by other logical block addresses, and the other logical block addresses meet the following conditions: their serial numbers are within the range of the logical address segment, and their serial numbers are less than or equal to the sum of the serial number of the starting logical block address and the number of sectors in the read cache area; The main controller is further configured to transmit the data in the read cache area to the host when the read cache area is full.

2. The storage device according to claim 1, characterized in that The main controller is further configured to obtain a storage page corresponding to the starting logic block address when a mapping relationship of the starting logic block address exists in the data mapping table stored therein; The main controller is further configured to query whether the data mapping table stored in the flash memory particle has a mapping relationship of the starting logical block address when the data mapping table stored therein does not have a mapping relationship of the starting logical block address.

3. The storage device according to claim 1, characterized in that: The main controller is further configured to determine whether the mapping relationship between the other logic block address and the storage page corresponding to the start logic block address is the latest mapping relationship when the data mapping table stored therein has the mapping relationship of the other logic block address; The main controller is further configured to write the physical block address mapped by the other logical block address into the read cache area when there is a latest mapping relationship between the other logical block address and the storage page corresponding to the start logical block address.

4. The storage device according to claim 3, characterized in that: The main controller is further configured to determine whether the data mapping table stored in the flash memory particle has the mapping relationship of the other logical block addresses when it is determined that the data mapping table stored therein does not have the mapping relationship of the other logical block addresses.

5. The storage device according to claim 2, characterized in that: The main controller is further configured to obtain a storage page corresponding to the starting logic block address when a mapping relationship of the starting logic block address exists in the data mapping table stored in the flash memory particle; The main controller is further configured to write all-0 data into a sector corresponding to the read cache area with the starting logic block address when the data mapping table stored in the flash memory particle does not have a mapping relationship of the starting logic block address.

6. The storage device according to claim 1, characterized in that: The main controller is also used to repeatedly query the mapping relationship of the logical address segment when the read cache area is not full, so as to obtain the physical block address of the next logical block address mapping.

7. A method for reading data from a storage device, characterized in that: include: Responding to a read instruction from a host to obtain a logical address segment, wherein the logical address segment represents a plurality of continuous sequences of logical block addresses; Query the mapping relationship of the logical address segments in sequence to obtain the host data in the storage page corresponding to the starting logical block address in the query, and write the host data into the page register, wherein the host data in the storage page includes a plurality of physical block addresses; Writing part of the physical block addresses mapped by the logical address segment in the page register into the read cache area, wherein the part of the physical block addresses written into the read cache area include the physical block addresses mapped by the starting logical block address and the physical block addresses mapped by other logical block addresses, and the other logical block addresses satisfy: their serial numbers are within the range of the logical address segment, and their serial numbers are less than or equal to the sum of the serial number of the starting logical block address and the number of sectors in the read cache area; When the read cache area is full, the data in the read cache area is transmitted to the host.

8. The method for reading data from a storage device according to claim 7, wherein: The step of sequentially querying the mapping relationship of the logical address segments to obtain the host data in the storage page corresponding to the starting logical block address in the query, and writing the host data into the page register, wherein the host data in the storage page includes a plurality of physical block addresses, comprises: Querying whether a data mapping table stored in the main controller has a mapping relationship of the starting logic block address; When a mapping relationship of the starting logic block address exists in the data mapping table stored in the main controller, obtaining a page corresponding to the starting logic block address; When the mapping relationship of the starting logical block address does not exist in the data mapping table stored in the main controller, query whether the data mapping table stored in the flash memory particle has the mapping relationship of the starting logical block address; When a mapping relationship of the starting logical block address exists in the data mapping table stored in the flash memory particle, obtaining a page corresponding to the starting logical block address; When the mapping relationship of the starting logical block address does not exist in the data mapping table stored in the flash memory particle, all-0 data is written into the sector of the read cache area corresponding to the starting logical block address.

9. The method for reading data from a storage device according to claim 7, wherein: The step of writing part of the physical block addresses mapped by the logical address segment in the page register into the read cache area, wherein the part of the physical block addresses written into the read cache area include the physical block addresses mapped by the starting logical block address and the physical block addresses mapped by other logical block addresses, and the other logical block addresses satisfy: their serial numbers are within the range of the logical address segment, and their serial numbers are less than or equal to the sum of the serial number of the starting logical block address and the number of sectors in the read cache area, comprises: Writing the physical block address mapped by the starting logical block address into the read cache area; The physical block addresses mapped by the other logical block addresses are written into the read cache area.

10. The data reading method of the storage device according to claim 9, characterized in that: The step of writing the physical block address mapped by the other logical block address into the read cache area comprises: Querying whether the data mapping table stored in the main controller has a mapping relationship of the other logical block addresses; When the data mapping table stored in the main controller has a mapping relationship of the other logic block addresses, determining whether the other logic block addresses and the storage page corresponding to the start logic block address are the latest mapping relationships; When the other logical block addresses and the storage pages corresponding to the start logical block address are in the latest mapping relationship, the physical block addresses mapped by the other logical block addresses are written into the read cache area.

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