Integrated circuit layout similarity analysis method and system
By extracting and matching the straight line feature information of circuit modules in integrated circuit chips, the problems of low efficiency and difficulty in migrating in traditional similarity analysis methods are solved, and more efficient and accurate similarity analysis is achieved.
Patent Information
- Application Number
- CN202411586090.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-07
- Publication Date
- 2025-02-28
- Estimated Expiration
- 2044-11-07
AI Technical Summary
The traditional integrated circuit similarity analysis method requires a lot of manpower to calculate and match attribute similarity, which is inefficient and difficult to migrate between multiple fields.
By obtaining the feature layer image data of the target chip, the straight line feature information of the target circuit module, including boundary feature information and internal feature information, and matching them based on these feature information to obtain similarity analysis results.
The efficiency and accuracy of similarity analysis are improved, and the similarity can be determined based solely on the flat linear feature information of the circuit module, reducing manual intervention and improving analysis efficiency.
Smart Images
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Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated circuit layout similarity analysis method and system. Background Art
[0002] The integrated circuit similarity analysis method can be implemented through entity alignment. Traditional entity alignment methods are mainly carried out through attribute similarity matching, using supervised learning machine learning models such as decision trees, support vector machines, ensemble learning, etc. These methods rely on the attribute information of entities and infer cross-platform entity alignment relationships through attribute similarity.
[0003] However, traditional entity alignment methods have some disadvantages. First, these methods require a lot of manpower to calculate and match attribute similarities. Such similarity analysis methods have poor applicability and low analysis efficiency. Summary of the invention
[0004] Based on the above problems, the present application provides an integrated circuit layout similarity analysis method and system to improve the accuracy of similarity analysis.
[0005] To solve the above problems, the technical solutions provided in the embodiments of the present application are as follows:
[0006] The first aspect of the present application provides an integrated circuit layout similarity analysis method, comprising:
[0007] Acquire characteristic layer image data of the target chip;
[0008] Determine a target circuit module included in the target chip based on the feature layer image data;
[0009] Extracting the flat line feature information of the target circuit module, wherein the flat line feature information includes boundary feature information and internal feature information, wherein the boundary feature information is used to characterize the closed polygon formed by the outermost flat lines of the target circuit module;
[0010] Based on the boundary feature information and internal feature information of the target circuit module, the target circuit module and the reference circuit module included in the target chip are matched respectively to obtain a similarity analysis result.
[0011] In a possible implementation manner, extracting the flat line feature information of the target circuit module includes:
[0012] When the feature layer image data is Diff layer image data, edge information is used as a feature element to extract the flat line feature information of the target circuit module, and the edge information is used to characterize the edge position information of Pdiff and Ndiff;
[0013] When the feature layer image data is Poly layer image data, through holes in the Poly layer image and / or edge information in the Poly layer image are used as feature elements to extract straight line feature information of the target circuit module.
[0014] In a possible implementation, the target circuit module and the reference circuit module included in the target chip are matched based on the boundary feature information and the internal feature information of the target circuit module to obtain a similarity analysis result, including:
[0015] Based on the boundary feature information of the target circuit module, matching is performed with the boundary features of the reference circuit module to obtain a candidate circuit module whose similarity is greater than a first preset threshold;
[0016] Adjusting the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module until the relative position of the corresponding internal flat line in the target circuit module matches that in the candidate circuit module;
[0017] Based on the result obtained by the adjustment, the similarity between the internal feature information of the target circuit module and the internal feature information of the candidate circuit module is calculated.
[0018] In a possible implementation, the step of matching the boundary feature information of the target circuit module with the boundary feature of the reference circuit module to obtain a candidate circuit module having a similarity greater than a first preset threshold includes:
[0019] Calculating and determining the image moments corresponding to the target circuit module and the reference circuit module respectively;
[0020] Calculating a difference percentage between an image moment corresponding to the target circuit module and an image moment corresponding to the reference circuit module, and obtaining a similarity between the target circuit module and the reference circuit module based on the difference percentage;
[0021] When the similarity is greater than a first preset threshold, the reference circuit module is used as a candidate circuit module.
[0022] In a possible implementation, the step of matching the boundary feature information of the target circuit module with the boundary feature of the reference circuit module to obtain a candidate circuit module having a similarity greater than a first preset threshold includes:
[0023] Based on the boundary feature information of the target circuit module, the boundary feature information of the candidate circuit module is matched to obtain a direction matching result, wherein the direction matching result is used to indicate that the spatial position of the target circuit module and / or the candidate circuit module is adjusted based on the relative position of the target circuit module and the candidate circuit module, so that the similarity of the boundary feature information of the target circuit module and the candidate circuit module meets the first preset standard;
[0024] Based on the direction matching result, adjusting the spatial position of the target circuit module and / or the candidate circuit module;
[0025] Based on the direction adjustment result, the similarity between the boundary feature information of the target circuit module and the boundary feature information of the candidate circuit module is calculated to obtain the candidate circuit module whose similarity is greater than a first preset threshold.
[0026] In a possible implementation, the adjusting the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module until the relative position of the target circuit module matches the relative position of the corresponding internal flat line in the candidate circuit module, includes:
[0027] When the closed polygon corresponding to the boundary feature information of the target circuit module and / or the boundary feature information of the candidate circuit module is an asymmetric figure, based on the direction adjustment result, the spatial position of the internal feature information of the target circuit module and / or the spatial position of the internal feature information of the candidate circuit module are adjusted until the relative position of the target circuit module and the corresponding internal straight line in the candidate circuit module match.
[0028] In a possible implementation, the adjusting the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module until the relative position of the target circuit module matches the relative position of the corresponding internal flat line in the candidate circuit module, includes:
[0029] When the closed polygon corresponding to the boundary feature information of the target circuit module and / or the boundary feature information of the candidate circuit module is a symmetrical figure and the similarity of the flat lines in the target circuit module and the candidate circuit module does not meet the second preset standard, the target circuit module or the candidate circuit module is flipped until the similarity of the flat lines in the target circuit module and the candidate circuit module meets the second preset standard;
[0030] The spatial position of the internal characteristic information of the target circuit module and / or the spatial position of the internal characteristic information of the candidate circuit module are adjusted until the relative position of the corresponding internal flat line in the target circuit module and the candidate circuit module matches.
[0031] In a possible implementation, the adjusting the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module until the relative position of the target circuit module matches the relative position of the corresponding internal flat line in the candidate circuit module, includes:
[0032] When the boundary feature information of the target circuit module and / or the boundary feature information of the candidate circuit module are the same, the target circuit module or the candidate circuit module is flipped until the similarity of the flat lines in the target circuit module and the candidate circuit module meets the second preset standard;
[0033] The spatial position of the internal characteristic information of the target circuit module and / or the spatial position of the internal characteristic information of the candidate circuit module are adjusted until the relative position of the corresponding internal flat line in the target circuit module and the candidate circuit module matches.
[0034] In a possible implementation, the adjusting the spatial position of the internal characteristic information of the target circuit module and / or the spatial position of the internal characteristic information of the candidate circuit module until the relative position of the corresponding internal flat line in the target circuit module matches that in the candidate circuit module includes:
[0035] Obtaining positioning points in the closed polygon corresponding to the target circuit module and the candidate circuit module;
[0036] Adjusting the position of the target circuit module and / or the candidate circuit module based on the positioning point until the target circuit module and the candidate circuit module are aligned based on the positioning point;
[0037] Enumerate each internal flat line in the target circuit module, find the internal flat line in the reference circuit module at the same relative position according to the relative position of each internal flat line and the positioning point, and adjust the spatial positions of the two internal flat lines until the overlapping area of the target flat line and the reference flat line is the largest, the target flat line is the flat line in the internal characteristic information of the target circuit module, and the reference flat line is the flat line in the internal characteristic information of the candidate circuit module corresponding to the target flat line.
[0038] In a possible implementation, adjusting the spatial positions of the two inner plane lines includes:
[0039] When the target plane and the reference plane are horizontal planes, matching and adjusting the spatial positions of the target plane and / or the reference plane in the vertical direction;
[0040] When the target plane and the reference plane are vertical planes, the spatial positions of the target plane and / or the reference plane are matched and adjusted in the horizontal direction.
[0041] In a possible implementation, the calculating, based on the result obtained by the adjustment, the similarity between the internal feature information of the target circuit module and the internal feature information of the candidate circuit module includes:
[0042] When the overlapping area of each flat line in the target circuit module and the corresponding flat line in the reference circuit module is the largest, the XOR result of the internal characteristic information of the target circuit module and the internal characteristic information of the candidate circuit module is calculated, and the length ratio of the preset difference position is calculated, and the preset difference position is the position where the length difference between the target flat line and the reference flat line is greater than the preset length value after the position adjustment;
[0043] Based on the length ratio and the XOR result, the similarity between the target circuit module and the candidate circuit module is obtained.
[0044] The second aspect of the present application provides a similarity analysis system, comprising:
[0045] An acquisition unit, used for acquiring characteristic layer image data of a target chip;
[0046] A circuit module determination unit, configured to determine a target circuit module included in the target chip based on the feature layer image data;
[0047] A flat line feature information extraction unit, used to extract the flat line feature information of the target circuit module, wherein the flat line feature information includes boundary feature information and internal feature information, wherein the boundary feature information is used to characterize a closed polygon formed by the outermost flat lines of the target circuit module;
[0048] The similarity analysis result determination unit is used to match the target circuit module and the reference circuit module respectively included in the target chip based on the boundary feature information and the internal feature information of the target circuit module to obtain a similarity analysis result.
[0049] Compared with the prior art, this application has the following beneficial effects:
[0050] By acquiring the feature layer image data of the target chip; determining the target circuit module contained in the target chip based on the feature layer image data; extracting the straight line feature information of the target circuit module, the straight line feature information includes boundary feature information and internal feature information, and the boundary feature information is used to characterize the closed polygon formed by the outermost straight lines of the target circuit module; based on the boundary feature information and internal feature information of the target circuit module, matching the target circuit module contained in the target chip respectively to obtain the similarity analysis result. That is, by comparing and matching the boundary feature information and internal feature information of the target circuit module in the target chip, the similarity analysis result can be obtained. Compared with the manual identification of circuit similarity in the prior art, the solution provided by the present application can determine the similarity based only on the straight line feature information of the circuit module, thereby improving the analysis efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] In order to more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0052] Figure 1 A flowchart of an integrated circuit layout similarity analysis method provided in an embodiment of the present application;
[0053] Figure 2 A schematic diagram of Diff layer image data provided in an embodiment of the present application;
[0054] Figure 3 A schematic diagram of the flat straight line feature information of the Diff layer image provided in an embodiment of the present application;
[0055] Figure 4 A schematic diagram of Poly layer image data provided in an embodiment of the present application;
[0056] Figure 5 A schematic diagram of flat straight line feature information of a Poly layer image provided in an embodiment of the present application;
[0057] Figure 6 A schematic diagram of flat straight line characteristic information of a target circuit module provided in an embodiment of the present application;
[0058] Figure 7 A schematic diagram of flat straight line characteristic information of a reference circuit module provided in an embodiment of the present application;
[0059] Figure 8 A schematic diagram of boundary feature information of a target circuit module provided in an embodiment of the present application;
[0060] Fig. 9 A schematic diagram of boundary characteristic information of a reference circuit module provided in an embodiment of the present application;
[0061] Fig.10 A schematic diagram of internal characteristic information of a target circuit module provided in an embodiment of the present application;
[0062] Fig.11 A schematic diagram of internal characteristic information of a candidate circuit module provided in an embodiment of the present application;
[0063] Fig.12 A schematic diagram of the upper left corner fixed point positioning provided in an embodiment of the present application;
[0064] Fig.13 A schematic diagram of completing precise positioning of a flat line provided in an embodiment of the present application;
[0065] Fig.14 A structural diagram of an integrated circuit layout similarity analysis system provided in an embodiment of the present application. DETAILED DESCRIPTION
[0066] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0067] To facilitate understanding of the technical solutions provided by the embodiments of the present application, the background technology involved in the embodiments of the present application will be described below.
[0068] As mentioned above, the prior art integrated circuit similarity analysis method can be implemented by entity alignment. Traditional entity alignment methods are mainly carried out by attribute similarity matching, using supervised learning machine learning models such as decision trees, support vector machines, ensemble learning, etc. These methods rely on the attribute information of the entity and infer the cross-platform entity alignment relationship through attribute similarity. However, traditional entity alignment methods have some disadvantages. First, these methods require a lot of manpower to calculate and match attribute similarity. Secondly, these methods are difficult to migrate between multiple fields because different attribute similarity functions need to be designed for different fields. Finally, since the expression of attributes is discrete, this calculation method ignores the semantic similarity of attributes, thereby limiting the effect of entity alignment.
[0069] In order to solve this problem, a similarity analysis method and system are provided in an embodiment of the present application. By acquiring the feature layer image data of the target chip; determining the target circuit module contained in the target chip based on the feature layer image data; extracting the straight line feature information of the target circuit module, the straight line feature information includes boundary feature information and internal feature information, the boundary feature information is used to characterize the closed polygon formed by the outermost straight lines of the target circuit module, and the internal feature information is used to characterize the internal straight lines of the target circuit module; based on the boundary feature information and internal feature information of the target circuit module, the target circuit module contained in the target chip is matched respectively to obtain the similarity analysis result. That is, by comparing and matching the boundary feature information and the internal feature information of the target circuit module in the target chip, the similarity analysis result can be obtained. Compared with the manual identification of circuit similarity in the prior art, the solution provided by the present application can determine the similarity based only on the straight line feature information of the circuit module, thereby improving the efficiency of the similarity analysis of the circuit module.
[0070] Typical application scenarios of this technology can be: First, layout design infringement analysis: find evidence of isomorphism of two chip layouts through module matching. Second, non-compliant use of IP cores: IP cores are generally divided into three types: soft cores, solid cores, and hard cores. Among them, the layout of the same IP hard core used in different chips has higher stability. Through module matching, find out whether the specified IP hard core is used in the target chip, so as to obtain evidence of unauthorized use of the IP hard core.
[0071] It should be noted that the similarity analysis method, system, device and storage medium provided in this application can be applied to the field of network security. The above is only an example and does not limit the application field of the similarity analysis method, system, device and storage medium provided in this application. Among them, the terminal device can be an electronic device such as a smart phone, a computer, a personal digital assistant (PDA), a tablet computer, etc. The server can be a stand-alone server, a cloud server, or a cluster server composed of multiple servers.
[0072] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0073] The following is an example of an integrated circuit layout similarity analysis method provided by the present application. Figure 1 ,Should Figure 1 A flowchart of a method for analyzing integrated circuit layout similarity provided in an embodiment of the present application, the method comprising:
[0074] S101, acquiring characteristic layer image data of a target chip.
[0075] For the target chip, the characteristic layer image can be obtained by using a scanning electron microscope after the chip is dissected. The chip contains multiple layers, and the layers with the richest chip design information, such as Diff and Poly, can usually be selected as the characteristic layer image. When the selected characteristic layer is the Diff layer, the image data of the Diff layer can be obtained by using a scanning electron microscope, such as Figure 2 As shown, Figure 2 This is a schematic diagram of the Diff layer image data provided in an embodiment of the present application, wherein the position marked on the border is the isolation zone formed by the Dummy Diff.
[0076] S102: Determine a target circuit module included in the target chip based on the feature layer image data.
[0077] In actual application scenarios, the circuit modules of most chips usually have closed polygons formed by through holes around the Poly layer, and closed polygons formed by Diff on the Diff layer, or isolation zones formed by Dummy Diff. Based on this feature of the target chip, machine learning, pattern recognition, manual labeling, etc. can be used to label the target circuit modules contained in the target chip.
[0078] S103: Extracting the flat line feature information of the target circuit module.
[0079] The straight line feature information includes boundary feature information and internal feature information. The boundary feature information is used to characterize the closed polygon formed by the outermost straight lines of the target circuit module, that is, the closed polygon formed by connecting several outermost straight lines in the straight line feature information extracted from the target circuit module. The closed polygon can include all other straight line feature information of the target circuit module in the closed area.
[0080] There are a large number of naturally formed straight lines in the integrated circuit chip. Most of the circuit module boundaries are polygons, and each side of the polygon is a horizontal and vertical straight line, with almost no diagonal lines. The edges of various devices and routings inside the circuit module also form horizontal and vertical straight lines. Therefore, the straight lines at the boundaries of the circuit modules constitute the boundary features of the circuit modules, and the straight lines inside the circuit modules constitute the texture features of the circuit modules. In the embodiments provided in the present application, the internal straight lines can also be expressed as texture straight lines. Based on the chip feature layer image, the embodiments of the present application can use a straight line detection-related algorithm to identify the module boundaries and internal straight lines, and use them as features of the circuit modules. Among them, the straight line detection algorithm can be a Hough transform, etc.
[0081] In a possible implementation, when the feature layer image data is Diff layer image data, edge information of Pdiff and Ndiff is used as feature elements to extract flat line feature information of the target circuit module.
[0082] In actual application scenarios, the above Figure 2 The target circuit module represented by the horizontal line feature information is extracted, and the following is obtained: Figure 3 The flat line extraction result of the Diff layer image is shown. Figure 3 Schematic diagram of the flat line feature information of the Diff layer image provided in the embodiment of the present application, that is, the edges of Pdiff and Ndiff are selected as feature elements, and the flat lines are extracted to obtain Figure 3 In the actual recognition process, in order to distinguish the horizontal lines and the vertical lines, the horizontal lines and the vertical lines in the extraction results can be marked with different colors for the convenience of distinction.
[0083] In a possible implementation, when the feature layer image data is Poly layer image data, through holes in the Poly layer image and / or edge information in the Poly layer image are used as feature elements to extract straight line feature information of the target circuit module.
[0084] When the feature layer image data is Poly layer image data, the feature layer data information of the Poly layer image data can be found in Figure 4 , Figure 4 A schematic diagram of Poly layer image data provided in an embodiment of the present application.
[0085] In the extraction process, in addition to extracting straight lines using the edge information that is directly visible in the Poly layer image, that is, directly extracting edge information in the same way as the above-mentioned DIFF extraction method, the through holes in the Poly layer image can also be used as feature elements to extract straight lines. In integrated circuit design, the spacing between through holes is subject to certain process rule constraints. After the through holes are identified, according to the constraints of the process rules, the through holes in the horizontal and vertical directions are connected using this spacing to form a straight line. Therefore, the through holes as the identification result can also be used to extract straight line feature information. Figure 4 The results of the feature layer image data extraction can be found in Figure 5 , Figure 5 This is a schematic diagram of the straight line feature information of the Poly layer image provided in an embodiment of the present application. Similarly, in order to distinguish horizontal lines from vertical lines in the actual recognition process, the horizontal lines and vertical lines in the extraction results can be marked with different colors for easy distinction.
[0086] S104 , based on the boundary feature information and internal feature information of the target circuit module, respectively match the target circuit module and the reference circuit module included in the target chip to obtain a similarity analysis result.
[0087] The target circuit module in the target chip is selected to match with the reference circuit module, and the reference circuit module can be one or more circuit modules from one or more chips. That is, according to the flat line extraction result of the feature layer image data of the target circuit module in the above step, it is determined whether there is a circuit module with high similarity with the boundary feature information and internal feature information of the target circuit module, and the similarity analysis result obtained by matching is obtained.
[0088] See also Figure 6 and Figure 7 , Figure 6 and Figure 7 It is used to characterize the flat line feature information extracted from the two circuit modules to be matched. Figure 6 A schematic diagram of flat line characteristic information of a target circuit module provided in an embodiment of the present application, Figure 7 A schematic diagram of the flat straight line characteristic information of the reference circuit module provided in an embodiment of the present application.
[0089] Accordingly, in the matching process, it is necessary to extract the boundary feature information of the target circuit module and the reference circuit module, and determine the closed polygon formed by the outermost flat lines of the circuit module based on the extracted flat line feature information, so as to obtain the boundary feature information corresponding to the current target circuit module, see Figure 8 and Fig. 9 The closed polygon shown, Figure 8A schematic diagram of boundary feature information of a target circuit module provided in an embodiment of the present application, Fig. 9 A schematic diagram of boundary feature information of a reference circuit module provided in an embodiment of the present application.
[0090] In a possible implementation, matching the target circuit modules included in the target chip based on the boundary feature information and the internal feature information of the target circuit modules to obtain similarity analysis results includes:
[0091] Step A1: Based on the boundary feature information of the target circuit module, match the boundary features of the reference circuit module to obtain candidate circuit modules whose similarity is greater than a first preset threshold.
[0092] That is, matching is performed based on the flat line features of the target circuit module and the reference circuit module, and the matching is divided into two rounds. In the first round, the boundary feature information of the target circuit module is used to match the boundary feature information of the reference circuit module to obtain a candidate circuit module whose similarity is greater than a first preset threshold. Among them, the number of candidate circuit modules can be one or more, and the boundary feature matching algorithm can be performed using methods such as Hu image moments in shape matching algorithms. The matching algorithm can be adaptively adjusted according to actual needs, and is not limited here.
[0093] When "Hu" is translated into Chinese, it can refer to "Hu moments", which are a set of image moments widely used in the fields of image processing and computer vision to describe the shape characteristics of images. Hu moments are a set of image moments with translation, rotation and scale invariance, and are often used for shape analysis and recognition in image processing and computer vision.
[0094] In a possible implementation, step A1, i.e., matching the boundary feature information of the target circuit module with the boundary feature of the reference circuit module to obtain a candidate circuit module having a similarity greater than a first preset threshold, includes the following steps:
[0095] Step a1: Calculate and determine the Hu image moments corresponding to the target circuit module and the reference circuit module respectively.
[0096] The Hu image moment corresponding to the target circuit module and the Hu image moment corresponding to the reference circuit module are calculated respectively, wherein the Hu image moment is a specific value obtained by calculation.
[0097] Step a2: Calculate the difference percentage between the Hu image moment corresponding to the target circuit module and the Hu image moment corresponding to the reference circuit module, and obtain the similarity between the target circuit module and the reference circuit module based on the difference percentage.
[0098] By calculating the difference percentage between the two Hu image moments determined in the above step, the similarity of the boundary features of the two modules can be obtained, which is the difference of the difference percentages calculated above.
[0099] Step a3: when the similarity is greater than a first preset threshold, taking the reference circuit module as a candidate circuit module.
[0100] The first preset threshold value can be set according to actual needs and can be adaptively adjusted. For example, it can be set to 90%. If the similarity between two modules is less than or equal to 90%, it is determined that the similarity between the two modules is low, and the second round of matching is no longer performed. In the embodiment of the present application, if the similarity between the two modules is greater than 90%, the second round of matching is continued.
[0101] That is, the first round of matching is first performed, and the purpose of the first round of matching is to confirm the similarity of the boundary closed polygons corresponding to the target circuit module and the reference circuit module. The selected method can be to use the Hu image moment in the shape matching algorithm to calculate the distance of the Hu image moment of the boundary feature information of the target circuit module and the reference circuit module to obtain the similarity of the boundary features of the two modules. After the reference circuit meets the first round of matching, the subsequent second round of matching is performed.
[0102] Step A2: adjusting the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module until the relative position of the corresponding internal flat line in the target circuit module matches that in the candidate circuit module.
[0103] In a possible implementation, after the step A1, i.e. matching the boundary feature information of the target circuit module with the boundary feature of the reference circuit module to obtain a candidate circuit module having a similarity greater than a first preset threshold, further includes:
[0104] Based on the boundary feature information of the target circuit module, matching is performed with the boundary feature information of the candidate circuit module to obtain a directional matching result, wherein the directional matching result is used to indicate adjustment of the spatial position of the boundary feature information of the target circuit module and / or the candidate circuit module so that the similarity of the boundary feature information of the target circuit module and the candidate circuit module meets the first preset standard.
[0105] During the first round of matching, a direction matching result is also obtained based on the boundary feature information of the target circuit module. The direction matching result is used to characterize the directions of the target circuit module and the candidate circuit module. That is, it can be determined based on the direction matching result that, with the target circuit module as the benchmark, when the candidate circuit module is rotated / flipped to which direction, the boundary similarity of the two modules is the highest; or, when the candidate circuit module is rotated / flipped to which direction, the boundary similarity of the two modules is the highest, which meets the first preset standard.
[0106] Then, based on the direction matching result thus obtained, the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module are adjusted until the relative position of the corresponding internal flat line in the target circuit module matches that in the candidate circuit module, including:
[0107] Step b1: When the closed polygon corresponding to the boundary feature information of the target circuit module and / or the boundary feature information of the candidate circuit module is an asymmetric figure, based on the direction matching result, adjust the spatial position of the straight line feature information of the target circuit module and / or the straight line feature information of the candidate circuit module until the similarity between the boundary feature information of the target circuit module and the candidate circuit module meets the first preset standard.
[0108] That is, when it is determined that the boundary polygon is an asymmetric figure, the spatial position of the target circuit module and / or the candidate circuit module is adjusted only according to the direction matching result. It should be noted that the adjustment is performed until the similarity of the boundary feature information of the target circuit module and the candidate circuit module meets the first preset standard. During the adjustment process, the boundary feature information and the internal feature information of the target circuit module are adjusted synchronously, that is, when the boundary feature information is rotated 30 degrees to the left, the internal feature information is also rotated 30 degrees to the left. Similarly, the boundary feature information and the internal feature information of the candidate circuit module are also adjusted synchronously.
[0109] Step b2: adjusting the spatial position of the internal characteristic information of the target circuit module and / or the spatial position of the internal characteristic information of the candidate circuit module until the relative position of the corresponding internal straight line in the target circuit module matches that in the candidate circuit module.
[0110] That is, after completing the above-mentioned direction adjustment, the internal feature information in the two circuit modules, that is, the position of each internal flat line in the circuit module, is adjusted and matched to achieve texture precision positioning. Texture precision positioning refers to adjusting the internal flat lines in the two circuit modules to be compared in space so that the relative positions of the corresponding flat lines in the two circuit modules match, thereby reducing the error caused by the subsequent texture feature matching due to the offset of the flat line position.
[0111] In a possible implementation, the adjusting the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module until the relative position of the corresponding internal flat line in the target circuit module matches that in the candidate circuit module includes steps c1 and c2:
[0112] Step c1: When the closed polygon corresponding to the boundary feature information of the target circuit module and / or the boundary feature information of the candidate circuit module is a symmetrical figure and the similarity of the flat lines in the target circuit module and the candidate circuit module does not meet the second preset standard, the target circuit module or the candidate circuit module is flipped until the similarity of the flat lines in the target circuit module and the candidate circuit module meets the second preset standard.
[0113] That is, if the boundary polygons of the target circuit module and / or the candidate circuit module are symmetrical figures, such as rectangles, then in the second round of matching, the candidate circuit module needs to be adjusted in directions such as vertical and horizontal flipping, that is, precise positioning and similarity calculation need to be performed in each direction until the similarity of the flat lines in the target circuit module and the candidate circuit module meets the second preset standard. The second preset standard can be when the similarity of the flat lines reaches a certain preset value or when the similarity reaches the maximum value during multiple flipping processes.
[0114] Step c2: adjusting the spatial position of the internal characteristic information of the target circuit module and / or the spatial position of the internal characteristic information of the candidate circuit module until the relative position of the corresponding internal straight line in the target circuit module matches that in the candidate circuit module.
[0115] That is, after completing the above-mentioned direction adjustment, the internal feature information in the two circuit modules, that is, the position of the internal flat lines in the circuit modules, is adjusted and matched to achieve texture precision positioning. Texture precision positioning refers to adjusting the spatial position of the internal flat lines in the two circuit modules to be compared so that the relative positions of the corresponding flat lines in the two circuit modules match, thereby reducing the error caused by the subsequent texture feature matching due to the offset of the flat line position.
[0116] When any of the following two situations is met, the internal feature information of the texture feature information in the two circuit modules, that is, the internal flat line position of each texture flat line inside the circuit module, is adjusted and matched until the relative positions of the corresponding flat lines in the target circuit module and the reference circuit module match, thereby achieving precise texture positioning. The first situation is that the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module have been adjusted. The second situation is that the boundary feature information of the target circuit module and the reference circuit module are the same and do not need to be adjusted. In this case, only the texture information features inside the target circuit module and the reference circuit module need to be adjusted.
[0117] Exemplarily, adjusting the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module until the relative position of the corresponding internal flat line in the target circuit module matches that in the candidate circuit module includes:
[0118] Step d1: Obtain positioning points in the closed polygons corresponding to the target circuit module and the candidate circuit modules.
[0119] Step d2: adjusting the position of the target circuit module and / or the candidate circuit module based on the positioning point until the target circuit module and the candidate circuit module are aligned based on the positioning point.
[0120] Step d3, enumerate each internal flat line in the target circuit module, find the internal flat line with the same relative position in the reference circuit module according to the relative position of each internal flat line and the positioning point, adjust the spatial positions of the two internal flat lines until the overlapping area of the target flat line and the reference flat line is the largest, the target flat line is the flat line in the internal characteristic information of the target circuit module, and the reference flat line is the flat line in the internal characteristic information of the candidate circuit module that corresponds to the target flat line.
[0121] That is, firstly, any vertex in the boundary polygon is selected as the initial positioning point of the two modules, the two circuit modules are aligned with the initial positioning point, and then the position of the horizontal line in at least one circuit module is adjusted from all directions according to the preset order. Fig.10 and Fig.11 , Fig.10 A schematic diagram of internal characteristic information of a target circuit module provided in an embodiment of the present application, Fig.11 A schematic diagram of internal characteristic information of a candidate circuit module provided in an embodiment of the present application, Fig.10 and Fig.11The rectangle includes the boundary feature information of the rectangle. In the application process, the vertices of the boundary feature information or the endpoints of the boundary plane can be selected as the positioning points. Fig.10 The upper left vertex b1 in is used as the positioning point. Fig.11 The vertex b2 in the upper left corner is the positioning point. The two circuit modules are aligned based on vertex b1 and vertex b2. The result after alignment can be seen in Fig.12 , Fig.12 The upper left corner fixed point positioning schematic diagram provided in the embodiment of the present application is composed of Fig.12 It can be seen that the corresponding straight line positions in the target circuit module and the candidate circuit module are offset and not completely aligned, and the offset direction and offset distance of each pair of straight lines are inconsistent.
[0122] Therefore, it is necessary to adjust the position of each flat line one by one to reduce the matching error. For each flat line in the target circuit module, determine the reference flat line corresponding to the flat line. For example, select a flat line a in the target circuit module, find the reference flat line a' in the candidate circuit module associated with it, and adjust the position of a' and / or a in the specified direction. For example, for Fig.12 The adjustment direction in can be to move a', move a' upwards, and stop when the overlap area of a and a' is the largest. The position after the precise positioning of the horizontal line is completed can be seen in Fig.13 , Fig.13 A schematic diagram of completing precise positioning of a flat line provided in an embodiment of the present application.
[0123] In actual application scenarios, the average grayscale value can be used to represent the overlap between two straight lines. That is, the spatial position of each set of corresponding target straight lines and reference straight lines can be adjusted, and the average grayscale value can be calculated for each adjusted position. The position with the largest average grayscale value is taken as the best positioning position for this set of straight lines. After the positions of the straight lines are adjusted one by one, the internal straight lines after the precise positioning of the entire circuit module are obtained.
[0124] In a possible implementation, the spatial position of the target plane and / or the reference plane is adjusted until the overlapping area of the target plane and the reference plane is maximized, including the following two cases:
[0125] When the target plane and the reference plane are horizontal planes, the spatial positions of the target plane and / or the reference plane are matched and adjusted in the vertical direction; when the target plane and the reference plane are vertical planes, the spatial positions of the target plane and / or the reference plane are matched and adjusted in the horizontal direction.
[0126] That is, for the horizontal straight lines in the two modules, position stepping and adjustment will only be performed in the vertical direction, and for the vertical straight lines, position stepping and adjustment will only be performed in the horizontal direction.
[0127] Step A3: Based on the result obtained by the adjustment, the similarity between the internal feature information of the target circuit module and the internal feature information of the candidate circuit module is calculated.
[0128] In a possible implementation, the calculating, based on the result obtained by the adjustment, the similarity between the internal feature information of the target circuit module and the internal feature information of the candidate circuit module includes:
[0129] Step e1, when the overlapping area of each flat line in the target circuit module and the corresponding flat line in the reference circuit module is the largest, calculate the XOR result of the internal characteristic information of the target circuit module and the internal characteristic information of the candidate circuit module, and calculate the length ratio of a preset difference position, wherein the preset difference position is a position where the length difference between the target flat line and the reference flat line is greater than a preset length value after the position is adjusted;
[0130] Step e2: Based on the length ratio and the XOR result, obtain the similarity between the target circuit module and the candidate circuit module.
[0131] After the internal straight lines of the target circuit module and the candidate circuit module are precisely located according to the above steps, the XOR results of the internal straight lines of the two circuit modules are calculated, and the length ratio of the straight lines at the difference is calculated to obtain the similarity of the two modules.
[0132] In a possible implementation, step A3 may further include:
[0133] Step A4: Determine a similarity analysis result based on the magnitude relationship between the similarity and a second preset threshold.
[0134] If the similarity between the two modules is lower than 90% (the second preset threshold), the two modules are judged to have a low matching degree, otherwise, the matching degree is high. The second preset threshold can be adaptively set and adjusted according to actual needs, and is not limited here.
[0135] In summary, the solution provided by the embodiment of the present application is to obtain the similarity analysis result by comparing and matching the boundary feature information and internal feature information of the target circuit module in the target chip. Compared with the manual identification of circuit similarity in the prior art, the solution provided by the present application can determine the similarity based only on the flat line feature information of the circuit module, thereby improving the analysis efficiency. There are also significant improvements in actual application scenarios. For example, evidence of isomorphism of two chip layouts can be found through module matching. Through module matching, it is possible to find out whether a known IP hard core is used in the target chip, thereby obtaining evidence of unauthorized use of the IP hard core.
[0136] The above are some specific implementations of the similarity analysis method provided in the embodiment of the present application. Based on this, the present application also provides a corresponding system for similarity analysis. The system provided in the embodiment of the present application will be introduced from the perspective of functional modularization. Fig.14 A structural diagram of an integrated circuit layout similarity analysis system provided in an embodiment of the present application.
[0137] The system comprises:
[0138] An acquisition unit 110 is used to acquire characteristic layer image data of a target chip;
[0139] A circuit module determining unit 111, configured to determine a target circuit module included in the target chip based on the feature layer image data;
[0140] A flat line feature information extraction unit 112, used to extract the flat line feature information of the target circuit module, wherein the flat line feature information includes boundary feature information and internal feature information, wherein the boundary feature information is used to characterize the closed polygon formed by the outermost flat lines of the target circuit module;
[0141] The similarity analysis result determining unit 113 is used to match the target circuit modules included in the target chip based on the boundary feature information and the internal feature information of the target circuit modules to obtain a similarity analysis result.
[0142] The embodiment of the present application also provides corresponding devices and computer storage media for implementing the similarity analysis method provided in the embodiment of the present application.
[0143] The device includes a memory and a processor, the memory is used to store instructions or codes, and the processor is used to execute the instructions or codes so that the device executes the similarity analysis method described in any embodiment of the present application.
[0144] The computer storage medium stores codes, and when the codes are executed, a device executing the codes implements the similarity analysis method described in any embodiment of the present application.
[0145] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system or device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.
[0146] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.
[0147] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0148] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
[0149] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for analyzing integrated circuit layout similarity, characterized in that: include: Acquire characteristic layer image data of the target chip; Determine a target circuit module included in the target chip based on the feature layer image data; Extracting the flat line feature information of the target circuit module, the flat line feature information includes boundary feature information and internal feature information, the boundary feature information is used to characterize the closed polygon formed by the outermost flat lines of the target circuit module, and the internal feature information is used to characterize the flat lines extracted based on the internal elements of the target circuit module; Based on the boundary feature information and internal feature information of the target circuit module, the target circuit module and the reference circuit module included in the target chip are matched respectively to obtain a similarity analysis result.
2. The method according to claim 1, characterized in that The extracting the flat line feature information of the target circuit module includes: When the feature layer image data is diffusion layer Diff layer image data, edge information is used as a feature element to extract the flat line feature information of the target circuit module, wherein the edge information is used to characterize the edge position information of the P-type diffusion layer Pdiff and the N-type diffusion layer Ndiff; When the feature layer image data is polysilicon layer Poly layer image data, through holes in the Poly layer image and / or edge information in the Poly layer image are used as feature elements to extract straight line feature information of the target circuit module.
3. The method according to claim 1 or 2, characterized in that: The step of matching the target circuit module and the reference circuit module respectively included in the target chip based on the boundary feature information and the internal feature information of the target circuit module to obtain a similarity analysis result includes: Based on the boundary feature information of the target circuit module, matching is performed with the boundary features of the reference circuit module to obtain a candidate circuit module whose similarity is greater than a first preset threshold; Adjusting the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module until the relative position of the corresponding internal flat line in the target circuit module matches that in the candidate circuit module; Based on the result obtained by the adjustment, the similarity between the internal feature information of the target circuit module and the internal feature information of the candidate circuit module is calculated.
4. The method according to claim 3, characterized in that The step of matching the boundary feature information of the target circuit module with the boundary feature of the reference circuit module to obtain a candidate circuit module having a similarity greater than a first preset threshold comprises: Calculating and determining the image moments corresponding to the target circuit module and the reference circuit module respectively; Calculating a difference percentage between an image moment corresponding to the target circuit module and an image moment corresponding to the reference circuit module, and obtaining a similarity between the target circuit module and the reference circuit module based on the difference percentage; When the similarity is greater than a first preset threshold, the reference circuit module is used as a candidate circuit module.
5. The method according to claim 3, characterized in that: The step of matching the boundary feature information of the target circuit module with the boundary feature of the reference circuit module to obtain a candidate circuit module having a similarity greater than a first preset threshold comprises: Based on the boundary feature information of the target circuit module, the boundary feature information of the candidate circuit module is matched to obtain a direction matching result, wherein the direction matching result is used to indicate that the spatial position of the target circuit module and / or the candidate circuit module is adjusted based on the relative position of the target circuit module and the candidate circuit module, so that the similarity of the boundary feature information of the target circuit module and the candidate circuit module meets the first preset standard; Based on the direction matching result, adjusting the spatial position of the target circuit module and / or the candidate circuit module; Based on the direction adjustment result, the similarity between the boundary feature information of the target circuit module and the boundary feature information of the candidate circuit module is calculated to obtain the candidate circuit module whose similarity is greater than a first preset threshold.
6. The method according to claim 5, characterized in that The step of adjusting the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module until the relative position of the target circuit module matches the relative position of the corresponding internal flat line in the candidate circuit module, comprises: When the closed polygon corresponding to the boundary feature information of the target circuit module and / or the boundary feature information of the candidate circuit module is an asymmetric figure, based on the direction adjustment result, the spatial position of the internal feature information of the target circuit module and / or the spatial position of the internal feature information of the candidate circuit module are adjusted until the relative position of the target circuit module and the corresponding internal straight line in the candidate circuit module match.
7. The method according to claim 5, characterized in that The step of adjusting the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module until the relative position of the target circuit module matches the relative position of the corresponding internal flat line in the candidate circuit module, comprises: When the closed polygon corresponding to the boundary feature information of the target circuit module and / or the boundary feature information of the candidate circuit module is a symmetrical figure and the similarity of the flat lines in the target circuit module and the candidate circuit module does not meet the second preset standard, the target circuit module or the candidate circuit module is flipped until the similarity of the flat lines in the target circuit module and the candidate circuit module meets the second preset standard; The spatial position of the internal characteristic information of the target circuit module and / or the spatial position of the internal characteristic information of the candidate circuit module are adjusted until the relative position of the corresponding internal flat line in the target circuit module and the candidate circuit module matches.
8. The method according to claim 3, characterized in that The step of adjusting the spatial position of the flat line feature information of the target circuit module and / or the spatial position of the flat line feature information of the candidate circuit module until the relative position of the target circuit module matches the relative position of the corresponding internal flat line in the candidate circuit module, comprises: When the boundary feature information of the target circuit module and / or the boundary feature information of the candidate circuit module are the same, the target circuit module or the candidate circuit module is flipped until the similarity of the flat lines in the target circuit module and the candidate circuit module meets the second preset standard; The spatial position of the internal characteristic information of the target circuit module and / or the spatial position of the internal characteristic information of the candidate circuit module are adjusted until the relative position of the corresponding internal flat line in the target circuit module and the candidate circuit module matches.
9. The method according to claim 5 or 8, characterized in that: The step of adjusting the spatial position of the internal characteristic information of the target circuit module and / or the spatial position of the internal characteristic information of the candidate circuit module until the relative position of the target circuit module matches the relative position of the corresponding internal flat line in the candidate circuit module, comprises: Obtaining positioning points in the closed polygon corresponding to the target circuit module and the candidate circuit module; Adjusting the position of the target circuit module and / or the candidate circuit module based on the positioning point until the target circuit module and the candidate circuit module are aligned based on the positioning point; Enumerate each internal flat line in the target circuit module, find the internal flat line at the same relative position in the reference circuit module according to the relative position of each internal flat line and the positioning point, and adjust the spatial positions of the two internal flat lines until the overlapping area of the target flat line and the reference flat line is the largest, wherein the target flat line is a flat line in the internal characteristic information of the target circuit module, and the reference flat line is a flat line in the internal characteristic information of the candidate circuit module corresponding to the target flat line.
10. The method according to claim 9, characterized in that The step of adjusting the spatial positions of the two internal plane lines comprises: When the target plane and the reference plane are horizontal planes, matching and adjusting the spatial positions of the target plane and / or the reference plane in the vertical direction; When the target plane and the reference plane are vertical planes, the spatial positions of the target plane and / or the reference plane are matched and adjusted in the horizontal direction.
11. The method according to claim 9, characterized in that The calculating, based on the result obtained by the adjustment, the similarity between the internal feature information of the target circuit module and the internal feature information of the candidate circuit module comprises: When the overlapping area of each flat line in the target circuit module and the corresponding flat line in the reference circuit module is the largest, the XOR result of the internal characteristic information of the target circuit module and the internal characteristic information of the candidate circuit module is calculated, and the length ratio of the preset difference position is calculated, and the preset difference position is the position where the length difference between the target flat line and the reference flat line is greater than the preset length value after the position adjustment; Based on the length ratio and the XOR result, the similarity between the target circuit module and the candidate circuit module is obtained.
12. A similarity analysis system, characterized in that: include: An acquisition unit, used for acquiring characteristic layer image data of a target chip; A circuit module determination unit, configured to determine a target circuit module included in the target chip based on the feature layer image data; A flat line feature information extraction unit, used to extract flat line feature information of the target circuit module, wherein the flat line feature information includes boundary feature information and internal feature information, wherein the boundary feature information is used to characterize a closed polygon formed by the outermost flat lines of the target circuit module, and the internal feature information is used to characterize a flat line extracted based on internal elements of the target circuit module; The similarity analysis result determination unit is used to match the target circuit module and the reference circuit module respectively included in the target chip based on the boundary feature information and the internal feature information of the target circuit module to obtain a similarity analysis result.