Fast phase sequence judgment method, system and equipment based on FPGA (Field Programmable Gate Array) and medium

Abstract

The invention discloses a fast phase sequence judgment method, system and device based on an FPGA and a medium, and the method comprises the steps: sampling voltages of an A phase, a B phase and a C phase of a power grid, shaping the sampling waveform of the A phase, and obtaining a shaped square wave; performing rising edge detection on the shaped square wave; and judging the positive-negative relationship between the B-phase voltage sampling value and the C-phase voltage sampling value of the power grid at the rising edge moment according to a detection result to obtain a phase sequence judgment result. Complex calculation is not needed, the phase sequence judgment efficiency is improved, the real-time performance of phase sequence judgment is guaranteed, and rapid phase sequence judgment is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of phase sequence determination, and in particular to a fast phase sequence determination method, system, device and medium based on FPGA. Background Art

[0002] Currently, there are many methods for determining phase sequence, but most of them require complex calculations, such as calculating the positive and negative sequence components of the voltage under rotating coordinates, and consume a lot of CPU resources and time. Summary of the invention

[0003] To solve the above problems, the present invention provides a fast phase sequence judgment method, system, device and medium based on FPGA, which judges the phase sequence of the power grid voltage by judging the B and C phase voltages at the moment when the A phase voltage passes through zero. It does not require complex calculations, reduces the pressure on hardware equipment, improves the efficiency of phase sequence judgment, and ensures the real-time nature of phase sequence judgment.

[0004] The present invention provides a fast phase sequence determination method based on FPGA, and the specific technical solution is as follows:

[0005] S1: Sample the voltages of phase A, phase B and phase C of the power grid, and shape the sampled waveform of phase A to obtain a shaped square wave;

[0006] S2: Perform rising edge detection on the shaped square wave;

[0007] S3: Based on the detection results, the positive and negative relationship between the sampling values ​​of the phase B and phase C voltages of the power grid at the rising edge moment is determined to obtain the phase sequence determination result.

[0008] Furthermore, in step S1, the shaping is specifically as follows:

[0009] Get the sampled data, output the waveform whose sampling value is greater than 0 in the sampled data, and reshape it into a high-level output.

[0010] Further, in step S2, the rising edge detection is specifically as follows:

[0011] According to the shaped square wave, the previous state and the next state are stored;

[0012] If the previous state is a low level and the next state is a high level, it is a rising edge.

[0013] Further, in step S3, according to the positive and negative relationship between the voltage sampling values ​​of phase B and phase C of the power grid at the current moment, the phase sequence is determined as follows:

[0014] When the B phase voltage sampling result is negative and the C phase voltage sampling result is positive, the phase sequence judgment result is a positive phase sequence; the other sampling results are judged as negative phase sequences.

[0015] The present invention also provides a fast phase sequence judgment system based on FPGA, and the specific technical solution is as follows:

[0016] The system includes a sampling module, a shaping output module, a storage module, a rising edge detection module, a processor module and a phase sequence judgment module;

[0017] The sampling module includes a first sampling unit, a second sampling unit and a third sampling unit, which respectively perform synchronous sampling on phase A, phase B and phase C of the power grid;

[0018] The shaping output module is connected to the first sampling unit, receives the sampling data of the phase A of the power grid, and performs shaping output;

[0019] The storage module receives the sampled data output by the shaping output module and stores it;

[0020] The rising edge detection module is connected to the storage module, obtains the waveform data stored in the storage module, and performs rising edge detection according to the data of the previous state and the next state;

[0021] The phase sequence judgment module is connected to the rising edge detection module, the second sampling unit and the third sampling unit, and judges the positive and negative relationship between the B-phase and C-phase voltage sampling values ​​corresponding to the rising edge moment according to the detection result, and outputs the phase sequence judgment result.

[0022] Furthermore, the shaping output module shapes the waveform with a sampling value greater than 0 into a high-level output according to the received sampling data of phase A of the power grid.

[0023] Furthermore, the storage module includes two registers for storing the previous state and the next state respectively.

[0024] Furthermore, the rising edge detection module obtains the waveform data of the previous state and the next state from two registers respectively. If the previous state is a low level and the next state is a high level, it is determined to be a rising edge and output.

[0025] The present invention also provides an FPGA-based fast phase sequence judgment device, which includes: a memory, a processor, and an FPGA-based fast phase sequence judgment program stored in the memory and executable on the processor. When the FPGA-based fast phase sequence judgment program is executed by the processor, the steps of the above-mentioned FPGA-based fast phase sequence judgment method are implemented.

[0026] The present invention also provides a computer storage medium, on which is stored a FPGA-based fast phase sequence determination program, which, when executed by a processor, implements the steps of the above-mentioned FPGA-based fast phase sequence determination method.

[0027] The beneficial effects of the present invention are as follows:

[0028] The present invention samples and shapes the A-phase voltage of the power grid, performs edge detection according to the obtained shaped square wave, and obtains the positive and negative relationship between the sampling values ​​of the B-phase and C-phase voltages of the power grid based on the detection result to judge the phase sequence of the power grid voltage. No complicated calculation is required, the efficiency of phase sequence judgment is improved, and the real-time performance of phase sequence judgment is ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic flow chart of the method of the present invention. DETAILED DESCRIPTION

[0030] The following description clearly and completely describes the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] In the description of the embodiments of the present invention, it should be noted that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the invention product is usually placed when in use, or the orientation or positional relationship commonly understood by those skilled in the art, or the orientation or positional relationship in which the invention product is usually placed when in use, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0032] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] Example 1

[0034] Embodiment 1 of the present invention discloses a fast phase sequence determination method based on FPGA, such as Figure 1 As shown, the specific steps are as follows:

[0035] S1: Sample the voltages of phase A, phase B and phase C of the power grid, and shape the sampled waveform of phase A to obtain a shaped square wave;

[0036] The details are as follows:

[0037] Get the sampled data, output the waveform whose sampling value is greater than 0 in the sampled data, and reshape it into a high-level output.

[0038] S2: Perform rising edge detection on the shaped square wave;

[0039] The rising edge detection is specifically as follows:

[0040] According to the shaped square wave, the previous state and the next state are stored;

[0041] If the previous state is a low level and the next state is a high level, it is a rising edge.

[0042] S3: S3: Through the detection results, determine the positive and negative relationship between the grid B phase and C phase voltage sampling values ​​corresponding to the rising edge moment, and obtain the phase sequence judgment result.

[0043] Specifically, when the B-phase voltage sampling result is negative and the C-phase voltage sampling result is positive, the phase sequence judgment result is a positive phase sequence; the remaining sampling results are judged as negative phase sequences.

[0044] Example 2

[0045] Embodiment 2 of the present invention discloses a fast phase sequence judgment system based on FPGA, the system includes a sampling module, a shaping output module, a storage module, a rising edge detection module, a processor module and a phase sequence judgment module;

[0046] The sampling module includes a first sampling unit, a second sampling unit and a third sampling unit, which respectively perform synchronous sampling on phase A, phase B and phase C of the power grid;

[0047] The processor module is used to coordinate the work of various modules and execute phase sequence judgment logic. The processor module can adopt FPGA.

[0048] The shaping output module is connected to the first sampling unit, receives the sampling data of the phase A of the power grid, and performs shaping output;

[0049] As a preferred embodiment, the shaping output module shapes the waveform with a sampling value greater than 0 into a high-level output according to the received sampling data of phase A of the power grid.

[0050] The storage module receives the sampled data output by the shaping output module and stores it;

[0051] As a preferred embodiment, the register module includes two registers for storing the previous state and the next state respectively.

[0052] The rising edge detection module obtains the waveform data of the previous state and the next state from two registers respectively. If the previous state is a low level and the next state is a high level, it is determined to be a rising edge and output.

[0053] The rising edge detection module is connected to the storage module, obtains the waveform data stored in the storage module, and performs rising edge detection according to the data of the previous state and the next state;

[0054] The phase sequence judgment module is connected to the rising edge detection module, the second sampling unit and the third sampling unit, and judges the positive and negative relationship between the B-phase and C-phase voltage sampling values ​​corresponding to the rising edge moment according to the detection result, and outputs the phase sequence judgment result;

[0055] Specifically, when the B-phase voltage sampling result is negative and the C-phase voltage sampling result is positive, the phase sequence judgment result is a positive phase sequence; the remaining sampling results are judged as negative phase sequences.

[0056] Example

[0057] Embodiment 3 of the present invention discloses a fast phase sequence judgment device based on FPGA, and the device may be a user equipment (UE), handheld device, vehicle-mounted device, wearable device, computing device or other processing device connected to a wireless modem, mobile station (MS), etc., for executing the fast phase sequence judgment method based on FPGA, such as a mobile phone, a smart phone, a laptop computer, a digital broadcast receiver, a personal digital assistant (PDA), a tablet computer (PAD), etc. The device may be called a user terminal, a portable terminal, a desktop terminal, etc.

[0058] Typically, the device includes: at least one processor, a memory, and an FPGA-based fast phase sequence judgment program stored in the memory and executable on the processor, wherein the FPGA-based fast phase sequence judgment program is configured to implement the steps of the FPGA-based fast phase sequence judgment method as described in Example 1.

[0059] The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. The processor may also include an AI (Artificial Intelligence) processor, which is used to process calculation operations related to the FPGA-based fast phase sequence judgment program, so that the FPGA-based fast phase sequence judgment method can be trained and learned autonomously to improve efficiency and accuracy.

[0060] The memory may include one or more computer-readable storage media, which may be non-transitory. The memory may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory is used to store at least one instruction, which is used to be executed by the processor to implement the FPGA-based fast phase sequence judgment method described in the above embodiment 1.

[0061] In some embodiments, the terminal may also optionally include: a communication interface and at least one peripheral device. The processor, the memory and the communication interface may be connected via a bus or a signal line. Each peripheral device may be connected to the communication interface via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit, a display screen and a power supply.

[0062] The communication interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. The communication interface is used to receive the movement trajectories and other data of multiple mobile terminals uploaded by users through the peripheral device. In some embodiments, the processor, memory and communication interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, memory and communication interface can be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0063] The radio frequency circuit is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit communicates with the communication network and other communication devices through electromagnetic signals, so that the movement trajectory and other data of multiple mobile terminals can be obtained. The radio frequency circuit converts the electrical signal into an electromagnetic signal for transmission, or converts the received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, etc. The radio frequency circuit can communicate with other terminals through at least one wireless communication protocol. The wireless communication protocol includes but is not limited to: a metropolitan area network, various generations of mobile communication networks (2G, 3G, 4G and 5G), a wireless local area network and / or a WiFi (Wireless Fidelity) network. In some embodiments, the radio frequency circuit may also include circuits related to NFC (Near Field Communication), which is not limited in this application.

[0064] The display screen is used to display the UI (User Interface). The UI may include graphics, text, icons, videos and any combination thereof. When the display screen is a touch display screen, the display screen also has the ability to collect touch signals on the surface or above the surface of the display screen. The touch signal can be input to the processor as a control signal for processing. At this time, the display screen can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen can be one, the front panel of the electronic device; in other embodiments, the display screen can be at least two, respectively arranged on different surfaces of the electronic device or in a folding design; in some further embodiments, the display screen can be a flexible display screen, arranged on a curved surface or a folding surface of the electronic device. Even, the display screen can also be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode) and the like.

[0065] The power supply is used to power various components in the electronic device. The power supply can be AC, DC, a disposable battery or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0066] Example 4

[0067] Embodiment 4 of the present invention discloses a computer storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the FPGA-based fast phase sequence determination method described in the above embodiment 1 are implemented.

[0068] The readable storage medium may specifically be a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or other readable storage medium that can store program codes.

[0069] The present invention is not limited to the above-mentioned specific embodiments, but extends to any new features or any new combination disclosed in this specification, as well as any new method or process steps or any new combination disclosed.

Claims

1. A fast phase sequence judgment method based on FPGA, characterized in that: include: S1: Sample the voltages of phase A, phase B and phase C of the power grid, and shape the sampled waveform of phase A to obtain a shaped square wave; S2: Perform rising edge detection on the shaped square wave; S3: Based on the detection results, the positive and negative relationship between the sampling values ​​of the phase B and phase C voltages of the power grid at the rising edge moment is determined to obtain the phase sequence determination result.

2. The FPGA-based fast phase sequence determination method according to claim 1, characterized in that: In step S1, the shaping is specifically as follows: Get the sampled data, output the waveform whose sampling value is greater than 0 in the sampled data, and reshape it into a high-level output.

3. The FPGA-based fast phase sequence determination method according to claim 1, characterized in that: In step S2, the rising edge detection is as follows: According to the shaped square wave, the previous state and the next state are stored; If the previous state is a low level and the next state is a high level, it is a rising edge.

4. The FPGA-based fast phase sequence determination method according to claim 1, characterized in that: In step S3, according to the positive and negative relationship between the voltage sampling values ​​of phase B and phase C of the power grid at the current moment, the phase sequence is determined as follows: When the B phase voltage sampling result is negative and the C phase voltage sampling result is positive, the phase sequence judgment result is a positive phase sequence; the other sampling results are judged as negative phase sequences.

5. A fast phase sequence judgment system based on FPGA, characterized in that: The system includes a sampling module, a shaping output module, a storage module, a rising edge detection module, a processor module and a phase sequence judgment module; The sampling module includes a first sampling unit, a second sampling unit and a third sampling unit, which respectively perform synchronous sampling on phase A, phase B and phase C of the power grid; The shaping output module is connected to the first sampling unit, receives the sampling data of the phase A of the power grid, and performs shaping output; The storage module receives the sampled data output by the shaping output module and stores it; The rising edge detection module is connected to the storage module, obtains the waveform data stored in the storage module, and performs rising edge detection according to the data of the previous state and the next state; The phase sequence judgment module is connected to the rising edge detection module, the second sampling unit and the third sampling unit, and judges the positive and negative relationship between the B-phase and C-phase voltage sampling values ​​corresponding to the rising edge moment according to the detection result, and outputs the phase sequence judgment result.

6. The FPGA-based fast phase sequence determination system according to claim 5, characterized in that: The shaping output module shapes the waveform with a sampling value greater than 0 into a high level output according to the received sampling data of the A phase of the power grid.

7. The FPGA-based fast phase sequence determination system according to claim 5, characterized in that: The register module includes two registers for storing the previous state and the next state respectively.

8. The FPGA-based fast phase sequence determination system according to claim 7, characterized in that: The rising edge detection module obtains the waveform data of the previous state and the next state from two registers respectively. If the previous state is a low level and the next state is a high level, it is determined to be a rising edge and output.

9. A fast phase sequence judgment device based on FPGA, characterized in that: The FPGA-based fast phase sequence judgment device includes: a memory, a processor, and an FPGA-based fast phase sequence judgment program stored in the memory and executable on the processor. When the FPGA-based fast phase sequence judgment program is executed by the processor, the steps of the FPGA-based fast phase sequence judgment method as described in any one of claims 1 to 4 are implemented.

10. A computer storage medium, characterized in that: The storage medium stores a fast phase sequence determination program based on FPGA, and when the fast phase sequence determination program based on FPGA is executed by the processor, the steps of the fast phase sequence determination method based on FPGA as described in any one of claims 1-4 are implemented.

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