Starting circuit and starting method of system equipment and system equipment thereof

Abstract

The invention discloses a starting circuit and method of system equipment and the system equipment. The starting circuit comprises a multiplexer, a first flash memory chip, a second flash memory chip and a control circuit. A common end of the multiplexer is connected with a processor of the system equipment; the first flash memory chip is connected with a first end of the multiplexer, and the second flash memory chip is connected with a second end of the multiplexer; and the control circuit is respectively connected with the control ends of the central processor and the multiplexer. Wherein the control circuit is used for acquiring a selection signal from the processor and generating a control signal based on the selection signal; the multiplexer is used for selecting to be connected with one of the first flash memory chip and the second flash memory chip based on the control signal, that is, the switching of the first flash memory chip or the second flash memory chip is realized through the multiplexer and the control circuit, a special chip is not needed for switching, and the cost is greatly saved.

Description

Technical Field

[0001] The present invention relates to the technical field of system startup, and in particular to a startup circuit and a startup method of a system device and a system device thereof. Background Art

[0002] Currently, the processor is a necessary chip in the system, and its startup mode is mostly guided by the flash memory chip. The processor needs to obtain the startup information from the flash memory chip to enter the normal working state. When the processor fails to obtain the startup information, the hardware backup method is usually used to control the processor to switch to another flash memory chip to obtain the startup information through a dedicated chip. However, dedicated chips are expensive, and there are software failures or abnormal startup conditions, which cause the flash memory chip to fail to switch normally. Summary of the invention

[0003] In view of this, the present application discloses a startup circuit and a startup method of a system device and a system device thereof to solve the above technical problems.

[0004] In a first aspect, the present application discloses a startup circuit of a system device, comprising: a multiplexer, wherein a common end of the multiplexer is connected to a processor of the system device; a first flash memory chip and a second flash memory chip, wherein the first flash memory chip is connected to a first end of the multiplexer, and the second flash memory chip is connected to a second end of the multiplexer; a control circuit, connected to the processor and a control end of the multiplexer, respectively; wherein the control circuit is used to obtain a selection signal from the processor and generate a control signal based on the selection signal; and the multiplexer is used to select a connection with one of the first flash memory chip or the second flash memory chip based on the control signal.

[0005] In some embodiments, the control circuit includes a clock circuit and a trigger circuit, the clock circuit is connected to the processor, and is used to obtain the selection signal from the processor and generate a clock signal based on the selection signal; the trigger circuit is connected to the clock circuit, and is used to generate the control signal based on the clock signal; when it is necessary to switch between the first flash memory chip and the second flash memory chip, the clock signal is used to trigger the trigger circuit so that the control signal generated by the trigger circuit undergoes a level conversion to control the multiplexer to switch between the first flash memory chip and the second flash memory chip.

[0006] In some embodiments, the clock circuit includes a watchdog circuit and a first gate circuit, the selection signal includes a first signal and a second signal, the watchdog circuit is connected to the processor, for receiving the second signal and generating a watchdog signal based on the second signal; the first input end of the first gate circuit is connected to the watchdog circuit, for receiving the watchdog signal; the second input end of the first gate circuit is connected to the processor, for receiving the first signal; the output end of the first gate circuit is connected to the trigger circuit, and the first gate circuit generates the clock signal based on the watchdog signal and the first signal.

[0007] In some embodiments, the trigger circuit includes a trigger and a third signal generating circuit; the clock input terminal of the trigger is connected to the output terminal of the first gate circuit for receiving the clock signal; the data input terminal of the trigger is connected to the output terminal of the third signal generating circuit for receiving the third signal; the output terminal of the trigger is connected to the input terminal of the third signal generating circuit and the control terminal of the multiplexer; the trigger is used to generate the control signal based on the clock signal and the third signal, and the third signal generating circuit is used to generate the third signal based on the control signal.

[0008] In some embodiments, the trigger is an edge trigger. When the clock signal is a rising edge, the trigger is triggered, and the control signal generated by the trigger undergoes a level conversion to control the multiplexer to switch between the first flash memory chip and the second flash memory chip.

[0009] In some embodiments, the third signal generating circuit includes an inverter, the input of the inverter is connected to the output of the trigger, the output of the inverter is connected to the data input of the trigger, and the inverter is used to generate the third signal based on the control signal.

[0010] In some embodiments, the third signal generating circuit also includes a delay circuit and a second gate circuit; the first input end of the second gate circuit is connected to the output end of the inverter, the second input end of the second gate circuit is connected to the delay circuit, and the output end of the second gate circuit is connected to the data input end of the trigger; the delay circuit is used to generate a delay signal, the inverter is used to generate an inverted signal based on the control signal, and the second gate circuit is used to generate the third signal based on the inverted signal and the delay signal.

[0011] In some embodiments, after the system device is powered on, the delay signal generated by the delay circuit undergoes a level conversion after the watchdog circuit starts working, so that the system device is connected to the first flash memory chip through the multiplexer each time it is powered on.

[0012] The second aspect of the present application discloses a method for starting a system device, which is applied to the starting circuit as described in the first aspect, and the starting method includes: the control circuit obtains a selection signal from the processor and generates a control signal based on the selection signal; the multiplexer selects a connection with one of the first flash memory chip or the second flash memory chip based on the control signal; and the processor starts starting.

[0013] In some embodiments, the startup method also includes: if the processor fails to start successfully within a preset time, executing the control signal to perform a level conversion, the processor selects a switching operation connected to the other of the first flash memory chip and the second flash memory chip, and the processor restarts; if the processor fails to start successfully within the preset time, continuing to execute the switching operation until the processor starts successfully.

[0014] In some embodiments, after the processor is successfully started, the startup method further includes: if the processor needs to update data on the first flash memory chip or the second flash memory chip, the processor converts the level of the first signal so that the level of the control signal is converted, and the processor selects to connect to the flash memory chip that needs to update data.

[0015] A third aspect of the present application discloses a system device, comprising the starting circuit as described in the first aspect.

[0016] The beneficial effects of the present application are: a selection signal is obtained from a processor through a control circuit, and a control signal is generated based on the selection signal; a multiplexer selects a connection with one of the first flash memory chip or the second flash memory chip based on the control signal; and there is no need to use a dedicated chip to achieve switching between the first flash memory chip and the second flash memory chip, thereby greatly saving costs.

[0017] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 is a circuit diagram of a first embodiment of a startup circuit of a system device of the present application;

[0020] Figure 2is a circuit diagram of a second embodiment of a startup circuit of a system device of the present application;

[0021] Figure 3 is a circuit diagram of a first embodiment of a third signal generating circuit of the present application;

[0022] Figure 4 is a circuit diagram of a second embodiment of a third signal generating circuit of the present application;

[0023] Figure 5 is a circuit diagram of a third embodiment of a startup circuit of a system device of the present application;

[0024] Figure 6 is a circuit timing diagram corresponding to the third embodiment of the startup circuit of the system device of the present application;

[0025] Figure 7 It is a flowchart of another embodiment of the method for starting the system device of the present application. DETAILED DESCRIPTION

[0026] The present application is further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present application, but are not intended to limit the scope of the present application. Similarly, the following examples are only some embodiments of the present application rather than all embodiments, and all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of the present application.

[0027] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] In the description of this application, it is necessary to explain that, unless otherwise clearly specified and limited, the terms "install", "set", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or connected through an intermediate medium. For ordinary technicians in this field, the above-mentioned specific meanings belonging to this application can be connected according to specific circumstances.

[0029] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradicting each other.

[0030] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated before and after are in an "or" relationship. In addition, "many" in this article means two or more than two. In addition, the term "at least one" in this article means any combination of at least two of any one or more of a plurality of, for example, including at least one of A, B, and C, can mean including any one or more elements selected from the set consisting of A, B, and C.

[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0032] At present, the CPU is a necessary chip in the system, and its startup mode is mostly guided by the flash memory chip. The CPU needs to obtain the startup information from the flash memory chip to enter the normal working state. When the CPU fails to obtain the startup information, the hardware backup method is usually used to control the CPU to switch to another flash memory chip to obtain the startup information through a dedicated chip. However, the dedicated chip is expensive, and there are software failures or abnormal startup conditions, which make the flash memory chip unable to switch normally.

[0033] In order to solve the above problems, the present application proposes a startup circuit, a startup method and a system device of a system device. In order to enable technicians in this field to better understand the technical solution of the present application, the technical solution of the present application is further described in detail below in combination with the accompanying drawings and specific implementation methods.

[0034] See also Figure 1 , Figure 1 1 is a circuit diagram of the first embodiment of the startup circuit of the system device of the present application. The startup circuit 10 is applied to the processor of the system device, and the processor 100 includes but is not limited to a CPU (Central Processing Unit), FPGA (Field Programmable Gate Array), SOC (System On Chip), etc. that need to be started using an external flash memory chip. The startup circuit of the present application is described in detail below by taking the processor 100 as a central processor as an example.

[0035] The startup circuit 10 of this embodiment includes a multiplexer 200, a first flash memory chip 301, a second flash memory chip 302 and a control circuit 400. The common terminal 203 of the multiplexer 200 is connected to the processor 100 of the system device, the first flash memory chip 301 is connected to the first terminal 201 of the multiplexer 200, the second flash memory chip 302 is connected to the second terminal 202 of the multiplexer 200, and the control circuit 400 is connected to the processor 100 and the control terminal 204 of the multiplexer 200 respectively.

[0036] The processor 100 is the computing and control core of the startup circuit 10 and is the final execution unit for information processing and program running.

[0037] In this embodiment, the first level may be a high level, and the second level may be a low level. In other embodiments, the first level may be a low level, and the second level may be a high level.

[0038] The multiplexer 200 (MUX) is a digital / analog signal switch, which is a combinational logic circuit with multiple signal terminals and one common terminal. In the present application, when the control terminal 204 of the multiplexer 200 receives a low level, the multiplexer 200 selects the first flash memory chip 301 to connect to the processor 100; when the control terminal 204 of the multiplexer 200 receives a high level, the multiplexer 200 selects the second flash memory chip 302 to connect to the processor 100.

[0039] Flash memory chips are also called non-volatile memories, and their characteristic is that data does not disappear after power failure, so they can be used as a startup chip for the processor 100. In the present application, the first flash memory chip 301 can be used as a main flash memory chip, and startup information is obtained from the first flash memory chip 301 each time the processor 100 is powered on.

[0040] The control circuit 400 of this embodiment is used to obtain a selection signal from the processor 100, and generate a control signal based on the selection signal to control the processor 100 to connect to one of the first flash memory chip 301 or the second flash memory chip 302 through the multiplexer 200. That is, the present application implements the switching of the first flash memory chip 301 or the second flash memory chip 302 through the multiplexer 200 and the control circuit 400, without using a dedicated chip for switching, which greatly saves costs.

[0041] Optional, see Figure 2 , Figure 2 4 is a circuit diagram of a second embodiment of a startup circuit of a system device of the present application. The control circuit 400 includes a clock circuit 410 and a trigger circuit 420. The clock circuit 410 is connected to the processor 100 and is used to obtain a selection signal from the processor 100 and generate a clock signal based on the selection signal. The trigger circuit 420 is connected to the clock circuit 410 and is used to generate a control signal based on the clock signal.

[0042] When it is necessary to switch between the first flash memory chip 301 and the second flash memory chip 302, the clock signal is used to trigger the trigger circuit 420 so that the control signal generated by the trigger circuit 420 undergoes a level conversion to control the multiplexer 200 to switch between the first flash memory chip 301 and the second flash memory chip 302.

[0043] Optional, see Figure 2 The clock circuit 410 includes a watchdog circuit 411, the selection signal includes a first signal and a second signal, the watchdog circuit 411 is connected to the processor 100, and is used to receive the second signal and generate a watchdog signal based on the second signal.

[0044] The watchdog circuit 411 may include a timer 430, and the timer 430 is set with a preset time. In some embodiments, the watchdog circuit 411 receives a second signal that is converted from a low level to a high level within the preset time, indicating that the processor 100 is operating normally, and the watchdog signal output by the watchdog circuit 411 is a high level. In other embodiments, the second signal received by the watchdog circuit 411 within the preset time does not undergo a level conversion, that is, the level of the second signal does not convert from a low level to a high level, indicating that the processor 100 is operating abnormally, and the flash memory chip connected to the processor 100 is faulty, and the watchdog signal output by the watchdog circuit 411 switches between a high level and a low level, for example, the watchdog signal changes from a high level to a low level, and then changes from a low level to a high level.

[0045] In some embodiments, the control circuit 400 can determine whether the processor 100 is in a normal working state based on the second signal. Specifically, if the second signal received by the control circuit 400 has a high level and a low level conversion within a preset time, it indicates that the processor 100 is operating normally; if the second signal received by the control circuit 400 has no high level and a low level conversion within the preset time, it indicates that the processor 100 is operating abnormally, and the control circuit 400 sends a reset signal to the processor 100, and controls the processor 100 to clear the operating data and restart through the reset signal.

[0046] In some embodiments, after the processor 100 is successfully started, the first flash memory chip 301 and the second flash memory chip 302 can be switched through the first signal to update the data of the flash memory chip. Specifically, the first signal sent by the processor 100 switches between a high level and a low level, and the control circuit 400 generates a control signal to control the multiplexer 200 to switch the flash memory chip to update the data of the flash memory chip.

[0047] In digital circuits, the change from low level to high level is called a rising edge, and the change from high level to low level is called a falling edge.

[0048] Optionally, the second signal received by the watchdog circuit 411 within a preset time does not undergo a level conversion, that is, the level of the second signal does not convert from a low level to a high level, indicating that the processor 100 operates abnormally. The watchdog circuit 411 sends a reset signal to the processor 100, and controls the processor 100 to clear the operating data and restart through the reset signal.

[0049] Optional, see Figure 2 The clock circuit 410 further includes a first gate circuit 412, wherein a first input terminal 413 of the first gate circuit 412 is connected to the watchdog circuit 411 for receiving a watchdog signal. A second input terminal 414 of the first gate circuit 412 is connected to the processor 100 for receiving a first signal. An output terminal 415 of the first gate circuit 412 is connected to the trigger circuit 420, and the first gate circuit 412 generates a clock signal based on the watchdog signal and the first signal. Optionally, the first gate circuit 412 may be an AND gate logic circuit, and the first gate circuit 412 performs an AND gate logic operation on the watchdog signal and the first signal to obtain a clock signal.

[0050] In some embodiments, the first signal is a rising edge, and the watchdog signal is a high level, the clock signal output by the first gate circuit 412 is a rising edge, triggering the trigger circuit 420. In some embodiments, the watchdog signal is a rising edge, and the first signal is a high level, the clock signal output by the first gate circuit 412 is a rising edge, triggering the trigger circuit 420.

[0051] In some embodiments, when the processor 100 receives an instruction to actively switch the flash memory chip, the processor 100 controls the first signal to undergo a level conversion, for example, the first signal changes from a high level to a low level, and then changes from a low level to a high level. In some embodiments, the first signal is a rising edge, and the watchdog signal is a high level, and the clock signal obtained by the first gate circuit 412 through the AND gate logic operation is a rising edge, triggering the trigger circuit 420.

[0052] In some embodiments, when the second signal received by the watchdog circuit 411 within the preset time does not undergo level conversion, that is, when the level of the second signal does not convert from a low level to a high level, it indicates that the processor 100 is operating abnormally, and the flash memory chip connected to the processor 100 is faulty, and the watchdog signal output by the watchdog circuit 411 undergoes level conversion, for example, the first signal changes from a high level to a low level, and then changes from a low level to a high level. In some embodiments, the watchdog signal is a rising edge, and the first signal is a high level, and the clock signal obtained by the first gate circuit 412 through the AND gate logic operation is a rising edge, triggering the trigger circuit 420.

[0053] Optional, see Figure 2 The trigger circuit 420 may include a trigger 421 and a third signal generating circuit 440. The clock input terminal 422 of the trigger 421 is connected to the output terminal 415 of the first gate circuit 412 for receiving the clock signal. The data input terminal 423 of the trigger 421 is connected to the output terminal 442 of the third signal generating circuit 440 for receiving the third signal. The output terminal 424 of the trigger 421 is connected to the input terminal 441 of the third signal generating circuit 440 and the control terminal 204 of the multiplexer 200. The trigger 421 is used to generate a control signal based on the clock signal and the third signal. The third signal generating circuit 440 is used to generate a third signal based on the control signal.

[0054] In some embodiments, the trigger 421 is an edge trigger, and the edge trigger includes a D trigger, an edge JK trigger, a CMOS edge trigger, etc. The trigger circuit of the present application is described in detail below by taking a D trigger as an example.

[0055] The trigger 421 includes a clock input terminal 422, a data input terminal 423 and an output terminal 424. The trigger 421 is an information storage device with a memory function. When the clock signal is a rising edge, the trigger 421 is triggered, and the control signal generated by the trigger 421 undergoes a level conversion to control the multiplexer 200 to switch between the first flash memory chip 301 and the second flash memory chip 302. Specifically, when the clock signal received at the clock input terminal 422 is not a rising edge signal, the control signal generated by the output terminal 424 does not change; when the clock signal received at the clock input terminal 422 is a rising edge signal, the trigger 421 is triggered, and the control signal generated by the output terminal 424 changes based on the third signal received at the data input terminal 423. For example, when the clock signal is a rising edge signal and the third signal is a high level, the control signal output by the trigger 421 is a high level; when the clock signal is a rising edge signal and the third signal is a low level, the control signal output by the trigger 421 is a low level.

[0056] Optional, see Figure 3 , Figure 3 4 is a circuit diagram of the first embodiment of the third signal generating circuit of the present application. The third signal generating circuit 440 may include an inverter 450, an input terminal 451 of the inverter 450 is connected to an output terminal 424 of the trigger 421, and receives a control signal; an output terminal 452 of the inverter 450 is connected to a data input terminal 423 of the trigger 421, and the inverter 450 is used to generate a third signal based on the control signal.

[0057] In some embodiments, when the control signal is at a high level, the third signal is at a low level. In some embodiments, when the control signal is at a low level, the third signal is at a high level. Through the inverter 450, it is ensured that the third signal received by the data input terminal 423 of the trigger 421 and the control signal generated by the output terminal 424 of the trigger 421 are different in level, so that according to the trigger characteristic of the trigger 421, when the trigger 421 is triggered, the control signal generated by the output terminal 424 is level-converted, and the multiplexer 200 switches the flash memory chip based on the control signal.

[0058] Optional, see Figure 4 , Figure 44 is a circuit diagram of the second embodiment of the third signal generating circuit of the present application. The third signal generating circuit 440 may include an inverter 450, a delay circuit 460 and a second gate circuit 470. Among them, the first input terminal 471 of the second gate circuit 470 is connected to the output terminal 452 of the inverter 450, the second input terminal 472 of the second gate circuit 470 is connected to the delay circuit 460, and the output terminal 473 of the second gate circuit 470 is connected to the data input terminal 423 of the trigger 421; the delay circuit 460 is used to generate a delay signal, the inverter 450 is used to generate an inverted signal based on the control signal, and the second gate circuit 470 is used to generate a third signal based on the inverted signal and the delay signal. Specifically, the input terminal 451 of the inverter 450 is connected to the output terminal 424 of the trigger 421 to receive the control signal; the output terminal 452 of the inverter 450 is connected to the first input terminal 471 of the second gate circuit 470 to generate an inverted signal based on the control signal; the delay circuit 460 is connected to the second input terminal 472 of the second gate circuit 470 to generate a delay signal; the output terminal 473 of the second gate circuit 470 is connected to the data input terminal 423 of the trigger 421, and the second gate circuit 470 performs an AND gate logic operation on the inverted signal and the delay signal to obtain a third signal. In some embodiments, when the delay signal is low level and the inverted signal is low level or high level, the third signal output by the second gate circuit 470 is low level. In some embodiments, when the delay signal is high level and the inverted signal is high level, the third signal output by the second gate circuit 470 is high level. In some embodiments, when the delay signal is high level and the inverted signal is low level, the third signal output by the second gate circuit 470 is low level.

[0059] In this example, see Figure 2 and Figure 4 After the system device is powered on, the delay signal generated by the delay circuit 460 undergoes a level conversion after the watchdog circuit 411 starts working, so that the system device is connected to the first flash memory chip 301 through the multiplexer 200 each time it is powered on, and the first flash memory chip 301 is used as the main flash memory chip. Specifically, when the watchdog circuit 411 is started, the watchdog signal output by the watchdog circuit 411 is a low level, and after a first time period, the watchdog signal becomes a high level, and a rising edge appears in the watchdog signal; when the delay circuit 460 is started, the delay signal output by the delay circuit 460 is a low level, and after a second time period, the watchdog signal becomes a high level. Among them, the second time period is greater than the first time period. When the watchdog circuit 411 is started, the watchdog signal output by the watchdog circuit 411 is a rising edge, and the first signal is a high level, the clock signal is a rising edge, triggering the trigger 421, the delay signal is a low level at this time, the third signal is a low level, and the control signal output by the trigger 421 is a low level. The multiplexer 200 selects the first flash memory chip 301 to connect to the processor 100.

[0060] Optional, see Figure 2 When the control signal received by the control end 204 of the multiplexer 200 is at a low level, the first flash memory chip 301 is connected to the processor 100 through the multiplexer 200 to drive the processor 100; when the control signal received by the control end 204 of the multiplexer 200 is at a high level, the second flash memory chip 302 is connected to the processor 100 through the multiplexer 200 to drive the processor 100.

[0061] See also Figure 5 , Figure 5 1 is a circuit diagram of the third embodiment of the startup circuit of the system device of the present application. Figure 5 For a description of each circuit, see Figure 2 and Figure 4 , I will not go into details here.

[0062] See also Figure 6 , Figure 6This is a circuit timing diagram corresponding to the third embodiment of the startup circuit of the system device of the present application. In this embodiment, the startup circuit 10 is powered on, the first signal is at a high level by default, the watchdog signal is at a low level, and the delay signal is at a low level. At time T1, the watchdog circuit 411 starts working, the watchdog signal is at a rising edge, the clock signal is at a rising edge, and the trigger 421 is triggered. Since the delay signal remains at a low level for a time greater than the start-up time of the watchdog circuit 411, the delay signal is at a low level at this time, the third signal is at a low level, the control signal is at a low level, and the multiplexer 200 selects the first flash memory chip 301 to connect to the processor 100, confirming that the first flash memory chip 301 is the main flash memory chip. At time T2, the second signal received by the watchdog circuit 411 within the preset time does not undergo level conversion, that is, the level of the second signal does not convert from a low level to a high level, indicating that the processor 100 operates abnormally and the flash memory chip connected to the processor 100 is faulty. The watchdog signal output by the watchdog circuit 411 switches between a high level and a low level. The watchdog signal is a rising edge, and the clock signal is a rising edge, triggering the trigger 421. At this time, the third signal is a high level, and the control signal rises to a high level. The multiplexer 200 selects the second flash memory chip 302 to connect to the processor 100. At time T3, the second signal received by the watchdog circuit 411 within the preset time does not undergo level conversion, that is, the level of the second signal does not convert from a low level to a high level, indicating that the processor 100 is operating abnormally and the flash memory chip connected to the processor 100 is faulty. The watchdog signal output by the watchdog circuit 411 switches between a high level and a low level. The watchdog signal is a rising edge, and the clock signal is a rising edge, triggering the trigger 421. At this time, the third signal is a low level, and the control signal drops to a low level. The multiplexer 200 selects the first flash memory chip 301 to connect to the processor 100. After the processor 100 is successfully started, at time T4, the processor 100 switches the first flash memory chip 301 and the second flash memory chip 302 through the first signal to update the data of the flash memory chip. The processor 100 controls the first signal to be a rising edge, the watchdog signal to be a high level, and the clock signal to be a rising edge, triggering the trigger 421. At this time, the third signal is a high level, the control signal rises to a high level, and the multiplexer 200 selects the second flash memory chip 302 to connect to the processor 100, so as to update the data of the second flash memory chip 302. At time T5, the processor 100 switches the first flash memory chip 301 and the second flash memory chip 302 through the first signal to update the data of the flash memory chip. The processor 100 controls the first signal to be a rising edge, the watchdog signal to be a high level, and the clock signal to be a rising edge, triggering the trigger 421. At this time, the third signal is a low level, the control signal drops to a low level, and the multiplexer 200 selects the first flash memory chip 301 to connect to the processor 100, so as to update the data of the first flash memory chip 301.

[0063] The present application also provides an embodiment of a method for starting a system device. The method for starting a system device of the present application is applied to a starting circuit of the system device of the present application. The method for starting a system device includes:

[0064] The control circuit 400 obtains a selection signal from the processor 100 and generates a control signal based on the selection signal;

[0065] The multiplexer 200 selects a connection with one of the first flash memory chip 301 or the second flash memory chip 302 based on the control signal;

[0066] The processor starts booting.

[0067] After the system device is powered on, the multiplexer 200 will be connected to one of the first flash memory chip 301 and the second flash memory chip 302 according to the control signal. After the connection, the processor 100 starts to start.

[0068] See also Figure 7 , Figure 7 1 is a flow chart of another embodiment of the startup method of the system device of the present application. The startup method of this embodiment is applied to the startup circuit of the system device of the present application. The startup method of this embodiment, based on the above-mentioned embodiments of the startup method, further includes:

[0069] Step S71: Determine whether the processor is successfully started within a preset time.

[0070] After the processor 100 starts to start, if the flash memory chip connected to it has no fault, that is, the processor 100 runs normally, the processor 100 starts successfully. If the flash memory chip connected to it has a fault, the processor 100 runs abnormally and the processor 100 fails to start. In response to the processor not starting successfully within the preset time, the process proceeds to step S72; in response to the processor starting successfully within the preset time, the process proceeds to step S73.

[0071] See also Figure 2 or Figure 5 In some embodiments, the second signal received by the watchdog circuit 411 within the preset time undergoes a level conversion, and the processor 100 is successfully started. In other embodiments, the second signal received by the watchdog circuit 411 within the preset time does not undergo a level conversion, and the processor 100 runs abnormally, that is, the processor 100 fails to start.

[0072] Step S72: the control signal undergoes a level conversion, the processor 100 selects a switching operation to connect to the other one of the first flash memory chip 301 and the second flash memory chip 302, and the processor 100 restarts.

[0073] See also Figure 2 or Figure 5In some embodiments, the trigger 421 receives a clock signal and a third signal to generate a control signal. When the clock signal received by the trigger 421 is not a rising edge signal, the control signal generated by the trigger 421 does not change; when the clock signal received by the trigger 421 is a rising edge signal, the trigger 421 is triggered, and the control signal changes based on the third signal. For example, when the clock signal is a rising edge signal and the third signal is at a high level, the control signal generated by the trigger 421 is at a high level; when the clock signal is a rising edge signal and the third signal is at a low level, the control signal generated by the trigger is at a low level.

[0074] See also Figure 3 In some embodiments, the inverter 450 is used to ensure that the third signal received by the trigger 421 and the generated control signal have different levels, so that according to the trigger characteristics of the trigger 421, when the trigger 421 is triggered, the generated control signal undergoes a level conversion, and the processor 100 selects the other one of the first flash memory chip 301 and the second flash memory chip 302 through the multiplexer 200 to connect to the processor, and the processor 100 is restarted.

[0075] After the processor 100 is restarted, the process proceeds to step S71.

[0076] Step S73 : Determine whether the processor needs to update data on the first flash memory chip 301 or the second flash memory chip 302 .

[0077] In response to the processor 100 needing to update data on the first flash memory chip 301 or the second flash memory chip 302 , the process proceeds to step S74 .

[0078] Step S74: the processor 100 converts the level of the first signal so that the level of the control signal is converted, and the processor 100 selects to connect to the flash memory chip that needs to update data.

[0079] See also Figure 2 or Figure 5 The first signal sent by the processor 100 switches between a high level and a low level, and the control circuit 400 generates a control signal to control the multiplexer 200 to switch the flash memory chip, thereby updating the data of the flash memory chip.

[0080] Based on the above-mentioned starting circuit 10, the present application also provides a system device, including the above-mentioned starting circuit 10. Since the starting circuit 10 has been described in detail above, it will not be described in detail here.

[0081] The above descriptions are only several embodiments of the present invention. Those skilled in the art may make various changes or modifications to the present invention based on the contents disclosed in the application documents without departing from the spirit and scope of the present invention.

Claims

1. A startup circuit of a system device, characterized in that: include: a multiplexer, wherein a common end of the multiplexer is connected to a processor of the system device; A first flash memory chip and a second flash memory chip, wherein the first flash memory chip is connected to a first end of the multiplexer, and the second flash memory chip is connected to a second end of the multiplexer; A control circuit connected to the processor and the control end of the multiplexer respectively; The control circuit is used to obtain a selection signal from the processor and generate a control signal based on the selection signal; the multiplexer is used to select a connection with one of the first flash memory chip or the second flash memory chip based on the control signal.

2. The starting circuit according to claim 1, characterized in that: The control circuit includes a clock circuit and a trigger circuit, wherein the clock circuit is connected to the processor and is used to obtain the selection signal from the processor and generate a clock signal based on the selection signal; The trigger circuit is connected to the clock circuit and is used to generate the control signal based on the clock signal; When it is necessary to switch between the first flash memory chip and the second flash memory chip, the clock signal is used to trigger the trigger circuit so that the control signal generated by the trigger circuit undergoes a level conversion to control the multiplexer to switch between the first flash memory chip and the second flash memory chip.

3. The starting circuit according to claim 2, characterized in that: The clock circuit includes a watchdog circuit and a first gate circuit, the selection signal includes a first signal and a second signal, the watchdog circuit is connected to the processor, and is used to receive the second signal and generate a watchdog signal based on the second signal; the first input end of the first gate circuit is connected to the watchdog circuit, and is used to receive the watchdog signal; the second input end of the first gate circuit is connected to the processor, and is used to receive the first signal; the output end of the first gate circuit is connected to the trigger circuit, and the first gate circuit generates the clock signal based on the watchdog signal and the first signal.

4. The starting circuit according to claim 3, characterized in that: The trigger circuit includes a trigger and a third signal generating circuit; The clock input end of the trigger is connected to the output end of the first gate circuit for receiving the clock signal; the data input end of the trigger is connected to the output end of the third signal generating circuit for receiving the third signal; the output end of the trigger is connected to the input end of the third signal generating circuit and the control end of the multiplexer; The trigger is used to generate the control signal based on the clock signal and the third signal, and the third signal generating circuit is used to generate the third signal based on the control signal.

5. The starting circuit according to claim 4, characterized in that: The trigger is an edge trigger. When the clock signal is at a rising edge, the trigger is triggered, and the control signal generated by the trigger undergoes a level conversion to control the multiplexer to switch between the first flash memory chip and the second flash memory chip.

6. The starting circuit according to claim 4, characterized in that: The third signal generating circuit includes an inverter, an input end of the inverter is connected to an output end of the trigger, an output end of the inverter is connected to a data input end of the trigger, and the inverter is used to generate the third signal based on the control signal.

7. The starting circuit according to claim 6, characterized in that: The third signal generating circuit also includes a delay circuit and a second gate circuit; The first input end of the second gate circuit is connected to the output end of the inverter, the second input end of the second gate circuit is connected to the delay circuit, and the output end of the second gate circuit is connected to the data input end of the trigger; The delay circuit is used to generate a delay signal, the inverter is used to generate an inverted signal based on the control signal, and the second gate circuit is used to generate the third signal based on the inverted signal and the delay signal.

8. The starting circuit according to claim 7, characterized in that: After the system device is powered on, the delay signal generated by the delay circuit undergoes level conversion after the watchdog circuit starts to work, so that the system device is connected to the first flash memory chip through the multiplexer every time it is powered on.

9. A method for starting a system device, applied to the starting circuit as claimed in claim 1, characterized in that: The startup method comprises: The control circuit obtains a selection signal from the processor and generates a control signal based on the selection signal; The multiplexer selects a connection with one of the first flash memory chip or the second flash memory chip based on the control signal; The processor begins booting.

10. The startup method according to claim 9, characterized in that: The startup method also includes: If the processor fails to start successfully within the preset time, the control signal is executed to undergo a level conversion, the processor selects a switching operation to connect to the other of the first flash memory chip and the second flash memory chip, and the processor restarts; If the processor fails to start successfully within the preset time, the switching operation continues to be performed until the processor starts successfully.

11. The startup method according to claim 9, characterized in that: After the processor is successfully started, the startup method also includes: if the processor needs to update data on the first flash memory chip or the second flash memory chip, the processor converts the level of the first signal so that the level of the control signal is converted, and the processor selects to connect to the flash memory chip that needs to update data.

12. A system device, characterized in that: The invention comprises a starting circuit as described in any one of claims 1 to 8.

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