Check matrix construction method, storage medium, computer program product and related device

Abstract

The embodiment of the invention provides a construction method of a check matrix, a storage medium, a computer program product and a related device, and the construction method of the check matrix comprises the steps: generating a basis matrix, and enabling the offset differences of adjacent blocks located in the same row in the basis matrix to be equal; selecting a plurality of effective blocks from each column of the basis matrix through a progressive edge growth algorithm; and setting the blocks except the valid blocks in the basis matrix as invalid blocks to obtain a check matrix for checking the low-density parity check code. According to the scheme, the hardware structure for decoding the low-density parity check code based on the check matrix can be simplified, and the cost of hardware shift in the decoding process of the low-density parity check code is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a method for constructing a check matrix, a storage medium, a computer program product, and related devices. Background Art

[0002] A solid state drive (SSD) includes a storage controller and multiple NAND flash memories. The host can read data from the NAND flash memories through the storage controller. When storing data in the SSD, the storage controller processes the data to be stored based on the generation matrix, obtains the Low Density Parity Check (LDPC) code, and stores the LDPC code in the NAND flash memory. When reading data from the SSD, the storage controller reads the corresponding LDPC from the NAND flash memory and decodes the LDPC code based on the check matrix for error checking and correction.

[0003] Currently, the check matrix is ​​randomly constructed based on graphs or algebraic structures.

[0004] However, in the process of decoding LDPC codes based on a randomly constructed check matrix, the shift is unpredictable, resulting in a large hardware overhead. Summary of the invention

[0005] In view of this, embodiments of the present application provide a method for constructing a check matrix, a storage medium, a computer program product, and related devices to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of an embodiment of the present application, a method for constructing a check matrix is ​​provided, comprising: generating a base matrix, wherein the differences in offsets of adjacent blocks in the same row of the base matrix are equal; selecting a plurality of valid blocks from each column of the base matrix through an asymptotic edge growth algorithm; and setting blocks other than the valid blocks in the base matrix as invalid blocks to obtain a check matrix for checking a low-density parity-check code.

[0007] According to a second aspect of an embodiment of the present application, a device for constructing a check matrix is ​​provided, comprising: a generation unit for generating a base matrix, wherein the differences in offsets of adjacent blocks in the same row of the base matrix are equal; a selection unit for selecting a plurality of valid blocks from each column of the base matrix by a progressive edge growth algorithm; and an invalidation unit for setting blocks in the base matrix other than the valid blocks as invalid blocks, so as to obtain a check matrix for checking a low-density parity-check code.

[0008] According to a third aspect of an embodiment of the present application, a solid-state hard disk is provided, comprising: a storage control chip and a solid-state electronic storage chip; the storage control chip is used to read data from the solid-state electronic storage chip, and perform error checking and correction on the read data based on the check matrix constructed by the method described in the first aspect above.

[0009] According to the fourth aspect of an embodiment of the present application, there is provided an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to perform operations corresponding to the method described in the first aspect above.

[0010] According to a fifth aspect of an embodiment of the present application, a computer storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the method described in the first aspect above is implemented.

[0011] According to a sixth aspect of an embodiment of the present application, a computer program product is provided, comprising computer instructions, wherein the computer instructions instruct a computing device to execute the method described in the first aspect above.

[0012] According to the construction scheme of the check matrix provided in the embodiment of the present application, the difference in the offsets of adjacent blocks in the same row in the base matrix is ​​equal, and after selecting valid blocks from each column of the base matrix by the progressive edge growth algorithm, the blocks other than the valid blocks in the base matrix are set as invalid blocks, and then a check matrix for checking low-density parity check codes is obtained. Since the difference in the offsets of blocks in the same row in the base matrix is ​​equal, when the check matrix generated by the base matrix based on the specific structure checks the low-density parity check code, when the adjacent columns in the check matrix are switched for processing, the number of shifts of each row remains unchanged, which can simplify the hardware structure for decoding low-density parity check codes based on the check matrix, and reduce the overhead of hardware shifting during the decoding of low-density parity check codes. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0014] Figure 1 is a schematic block diagram of a solid state drive according to an embodiment of the present application;

[0015] Figure 2 is a flow chart of a method for constructing a check matrix according to an embodiment of the present application;

[0016] Figure 3 is a schematic block diagram of a base matrix according to an embodiment of the present application;

[0017] Figure 4 is a schematic diagram of a basic matrix of an embodiment of the present application;

[0018] Figure 5 is a schematic diagram of a check matrix of an embodiment of the present application;

[0019] Figure 6 is a schematic diagram of an invalidation basic matrix according to an embodiment of the present application;

[0020] Figure 7 is a flowchart of a method for selecting an effective check node according to an embodiment of the present application;

[0021] Figure 8 is a schematic diagram of a construction device of a check matrix according to an embodiment of the present application;

[0022] Fig. 9 It is a schematic diagram of a single device according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0024] First, some nouns or terms that appear in the process of describing the embodiments of the present application are subject to the following explanations.

[0025] NAND flash memory: NAND flash memory is also called NAND flash memory, which is a non-volatile flash memory. NAND flash memory uses tunneling injection to write and tunneling release to erase, and the address line and data line are multiplexed.

[0026] Solid State Disk: Solid State Disk (SSD) is also called a solid state drive, which is a hard disk made of a solid-state electronic storage chip array. The solid state disk in the embodiment of the present application refers to a solid state disk composed of NAND flash memory chips.

[0027] Storage control chip: The storage control chip is the SDD controller, also known as the main control chip or main control. It is one of the key components of the solid-state drive and consists of an embedded processor that executes code and several hardware acceleration modules.

[0028] Low-density parity-check code: Low-density parity-check (LDPC) code is a linear block code. It is widely used in channel coding fields such as Wi-Fi, 5G, SSD, etc. due to its flexible construction method, low coding complexity and error correction characteristics close to the Shannon limit.

[0029] Check matrix: The check matrix of LDPC code is also called H matrix. The check matrix is ​​a sparse matrix, that is, most of the elements are 0 and only a few elements are 1. Each row of the check matrix represents a check equation, and each column corresponds to a bit of the encoded codeword. The design principle of LDPC code is to ensure that the check matrix has good cyclic characteristics so that it can converge effectively during decoding.

[0030] Generator matrix: The generator matrix of LDPC is also called G matrix. The generator matrix is ​​used to map information bits to codewords. The generator matrix and the check matrix satisfy GH T =0, the information can be encoded into LDPC code by generating the matrix.

[0031] Progressive Edge Growth Algorithm: Progressive Edge Growth (PEG) algorithm is a classic random construction method. Its core idea is to use the greedy algorithm to select the check node that satisfies the maximum ring length when adding a variable node under the condition of satisfying the degree distribution, that is, the check node with the smallest degree is connected to it, and the edges connecting the variable node and the check node are continuously added in this way. In the process of constructing the check matrix, the density evolution algorithm is used to obtain the degree distribution that suits the needs, and LDPC codes with different code lengths and code rates are constructed.

[0032] Application environment of this application

[0033] The embodiment of the present application proposes a construction scheme for the check matrix of LDPC code. The whole scheme is relatively general and can be used for various hardware devices including solid-state drives, such as data centers, servers, personal computers, Internet of Things (IoT) devices, embedded devices, etc. The check matrix construction scheme provided in the embodiment of the present application is independent of the hardware deployed by the computing device that executes the scheme.

[0034] Solid State Drive

[0035] Figure 1A schematic block diagram of a solid state drive 100 is shown. A solid state drive (SSD), also known as a solid state drive, is a hard disk made of a solid-state electronic storage chip array. Depending on the storage medium, the solid state drive can be divided into a solid state drive based on flash memory (flash) and a solid state drive based on dynamic random access memory (DRAM). The solid state drive 100 in the embodiment of the present application can be a solid state drive based on NAND flash memory or a solid state drive based on DRAM.

[0036] Solid-state drives have many advantages over traditional mechanical hard drives, such as greater security for stored data. For example, there is no need to worry about damaging the stored data when the solid-state drive is shaken during use, and a sudden power outage during use will not cause data loss in the solid-state drive. Based on this, solid-state drives are widely used in various complex working environments, such as high-availability servers, and solid-state drives are also ideal storage devices for individual users.

[0037] like Figure 1 As shown, the solid state drive 100 includes a storage control chip 10 and a plurality of solid state electronic storage chips 20. As an example, Figure 1 As shown, the solid-state hard disk 100 includes three solid-state electronic storage chips 20, but it should be understood that the number of solid-state electronic storage chips 20 should not be limited to this. The solid-state electronic storage chip 20 can be a NAND flash memory. The data of the NAND flash memory is stored in a memory cell in the form of bits. One memory cell can store one bit, and multiple memory cells constitute a bit line. The bit line is the bit width of the NAND flash memory. Multiple bit lines can form a flash memory page, and multiple flash memory pages form a flash memory block. NAND flash memory reads and writes data in units of flash memory pages, and erases data in units of flash memory blocks.

[0038] In addition to the solid-state electronic storage chip 20 for storing data, the solid-state hard disk 100 may also include a storage control chip 10, which is used to control the read and write operations of the solid-state hard disk. When storing data in the solid-state electronic storage chip 20, the storage control chip 10 encodes the data to be stored by generating a matrix to obtain an LDPC code, and then stores the LDPC code in the solid-state electronic storage chip 20. When reading data from the solid-state electronic storage chip 20, the storage control chip 10 reads the LDPC code from the solid-state electronic storage chip 20 and decodes the LDPC code through a check matrix. The decoding process can perform error checking and correction on the LDPC code, and the corresponding valid data is obtained after the decoding is completed.

[0039] One or more application programs 201 are deployed on the host 200. For example, Figure 1 As shown, application 1, application 2 and application 3 are deployed on the host 200, but it should be understood that the number of applications 201 should not be limited to this.

[0040] The application 201 may send a write instruction or a read instruction to the storage control chip 10. The write instruction carries the address information of the storage unit for storing data, and the read instruction carries the address information of the storage unit storing the data to be read. After receiving the write instruction, the storage control chip 10 writes the LDPC code obtained by encoding into the corresponding one or more storage units according to the address information carried by the write instruction, and sends an indication information indicating that the data is successfully stored to the application 201. After receiving the read instruction, the storage control chip 10 reads the LDPC code from the corresponding one or more storage units according to the address information carried by the read instruction, decodes the LDPC code to obtain the data required by the application 201, and sends the decoded data to the corresponding application 201.

[0041] The host 200 may be a device with read and write operation functions such as a personal computer (PC) or a server, and the present application does not limit the type of the host 200. The solid state drive 100 may be connected to the host 200 via a peripheral component interconnect express (PCIE) interface, and the host 200 and the storage control chip 10 transmit data via the PCIE interface.

[0042] After the storage control chip 10 reads the LDPC code from the solid-state electronic storage chip 20, it decodes the LDPC code based on the check matrix, and performs error checking and correction on the LDPC code during the decoding process, thereby obtaining the required valid data. The check matrix can be constructed by the storage control chip 10, or it can be generated by a processor with corresponding capabilities such as a central processing unit (CPU) and a graphics processing unit (GPU), and the generated check matrix is ​​sent to the storage control chip 10. The check matrix can be stored in the double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR) of the solid-state hard disk 10. When the storage control chip 10 decodes the LDPC code, the check matrix is ​​read from the DDR of the solid-state hard disk 10.

[0043] The check matrix can be obtained by invalidating some blocks of the base matrix. In order to reduce the hardware overhead when the storage control chip 10 performs decoding according to the check matrix, the base matrix can have a special format. For example, the difference between adjacent blocks in the same row in the base matrix is ​​the same. When the LDPC code is decoded by using the check matrix generated based on the base matrix with a special format, the shift of adjacent blocks in the same row in the check matrix during the decoding process is the same, which makes the check matrix more hardware-friendly and reduces the hardware overhead in the process of decoding the LDPC code.

[0044] The embodiments of the present application mainly focus on the construction process of the check matrix, and the construction process of the check matrix will be described in detail later.

[0045] Method for constructing a check matrix

[0046] Figure 2 FIG. 1 is a flow chart of a method for constructing a check matrix according to an embodiment of the present application. Figure 2 As shown, the construction method of the check matrix includes the following steps:

[0047] Step 201: Generate a basis matrix.

[0048] The basis matrix is ​​used to construct the check matrix. By selecting some valid blocks in the basis matrix, that is, invalidating some blocks in the basis matrix, the check matrix can be obtained. The blocks included in the basis matrix are sparse circulant matrices. The offset of a block is the number of cyclic shifts of the block relative to the unit matrix, so the basis matrix can be represented by the offset of each block relative to the unit matrix.

[0049] In an example, the basis matrix can be expressed as the following base matrix BG and lift value Z:

[0050]

[0051] Each element in the basic matrix BG represents a block in the basic matrix, Z = 3, element 0 represents the 3×3 unit matrix, element 1 represents the cyclic shift matrix obtained by cyclically shifting the unit matrix by 1 bit, and element 2 represents the cyclic shift matrix obtained by cyclically shifting the unit matrix by 2 bits. The basic matrix H represented by the above basic matrix BG and the lifting value Z is base like Figure 3 shown.

[0052] See also Figure 3 , element 0 in the base matrix BG represents the base matrix H base The unit matrix in The element 1 in the base matrix BG represents the base matrix H base The cyclic shift matrix in The element 2 in the base matrix BG represents the base matrix H baseThe cyclic shift matrix in

[0053] The basis matrix can be generated randomly or based on an algebraic structure, and the number of short rings (6-membered permutation, 8-membered ring, 10-membered ring) in the basis matrix is ​​relatively small.

[0054] The difference in offsets of adjacent blocks in the same row in the base matrix is ​​equal, that is, the offsets of blocks in the same row in the base matrix form an arithmetic progression. The check matrix constructed based on a base matrix with such a structure can simplify the hardware structure for decoding LDPC codes based on the check matrix and reduce the overhead of hardware shifting.

[0055] Figure 4 FIG. 1 is a schematic diagram showing a basic matrix of an embodiment of the present application. Figure 4 As shown, the basic matrix BG is a 10×20 matrix, each element in the basic matrix BG represents a 128×128 unit matrix or a cyclic shift matrix, the element 0 in the basic matrix BG represents a 128×128 unit matrix, and the element X in the basic matrix BG (X is greater than or equal to 0 and less than 128) represents a 128×128 cyclic shift matrix obtained by cyclically shifting the 128×128 unit matrix by X positions. It should be understood that by Figure 4 The basis matrix BG shown represents the basis matrix H base It is a matrix of 1280×2560.

[0056] See also Figure 4 , the basis matrix H base The difference in the offsets of adjacent blocks in the first row of is equal to 0, and the basis matrix H base The difference in the offsets of adjacent blocks in the second row of is equal to 126, and the basis matrix H base The difference in the offsets of adjacent blocks in the third row of is equal to 1, and the basis matrix H base The difference in the offsets of adjacent blocks in the 4th row of is equal to 125, and the basis matrix H base The difference in the offsets of adjacent blocks in the 5th row of is equal to 4, and the basis matrix H base The offset differences of adjacent blocks in the 6th row of are all equal to 1, and the basis matrix H base The difference in the offsets of adjacent blocks in the 7th row of is equal to 124, and the basis matrix H base The difference in the offsets of adjacent blocks in the 8th row of is equal to 4, and the basis matrix H base The difference in the offsets of adjacent blocks in the 9th row of is equal to 2, and the basis matrix H base The difference in offsets of adjacent blocks in the 10th row is equal to 3.

[0057] It should be noted that the above basis matrix H baseThe difference in offsets of adjacent blocks in the same row is the result of addition operation under the finite field GF(128), so 127+125=125, 127+124=123, 8+125=5.

[0058] In one example, when generating a base matrix, the blocks in the first column of the base matrix can be randomly generated based on the unit matrix, and the offset difference between adjacent blocks in each row of the base matrix can be randomly determined. Then, based on the offset difference between the first block in each row of the base matrix and the adjacent blocks in the row, the other blocks in the row of the base matrix can be determined, thereby determining all the blocks in the base matrix.

[0059] It should be noted that the difference in offset between adjacent blocks in different rows of the base matrix may be the same or different, and this embodiment of the present application does not limit this.

[0060] Step 202: Select multiple valid blocks from each column of the base matrix by using a progressive edge growth algorithm.

[0061] After the base matrix is ​​generated, multiple valid blocks can be selected from each column of the base matrix by using the progressive edge growth (PEG) algorithm. The valid blocks selected from the base matrix will be used as valid blocks of the check matrix, and the blocks in the base matrix that are not selected as valid blocks will be used as invalid blocks in the check matrix. It should be noted that a valid block refers to a non-all-zero matrix, and an invalid block refers to an all-zero matrix.

[0062] It should be noted that, in the subsequent embodiments, unless otherwise stated, the columns of the base matrix refer to block columns, that is, columns composed of blocks in the base matrix.

[0063] A column weight target value is set for each block column of the base matrix. The column weight is used to indicate the number of valid blocks included in the corresponding block column. The column weight target value corresponding to a block column refers to the number of valid blocks required for the block column. When selecting valid blocks from the base matrix, the same or different column weight target values ​​can be set for different block columns. For example, the column weight target value of each block column in the base matrix can be set to 4, or the column weight target value of the odd block columns in the base matrix can be set to 4, and the column weight target value of the even block columns in the base matrix can be set to 5.

[0064] When selecting valid blocks from each block column of the base matrix through the PEG algorithm, valid blocks are selected one by one from each block column of the base matrix. After the number of valid blocks selected from the current block column reaches the column weight target value of the current block column, valid blocks are selected one by one from the next block column until the number of valid blocks selected from each block column reaches the corresponding column weight target value.

[0065] Step 203: Set blocks other than valid blocks in the base matrix as invalid blocks to obtain a check matrix for checking the low-density parity-check code.

[0066] After determining the valid blocks from the base matrix, the blocks other than the valid blocks in the base matrix are set as invalid blocks to obtain the check matrix. The check matrix includes valid blocks and invalid blocks, the valid blocks are non-all-zero matrices, and the invalid blocks are all-zero matrices. In one example, since the check matrix is ​​a sparse matrix, the number of valid blocks in the check matrix is ​​less than the number of invalid blocks.

[0067] When setting blocks other than the valid block in the base matrix to invalid blocks, all elements included in the blocks other than the valid block in the base matrix may be set to 0, so that the blocks become invalid blocks (all-zero matrix).

[0068] In one example, the basis matrix representing the basis matrix The basis matrix H is transformed into base The first and second blocks of the first block column in are selected as valid blocks, the second and third blocks of the second block column are selected as valid blocks, the first and third blocks of the third block column are selected as valid blocks, and the first and third blocks of the fourth block column are selected as valid blocks, so that the basis matrix H base The third block in the first block column is set as an invalid block, the first block in the second block column is set as an invalid block, the second block in the third block column is set as an invalid block, and the second block in the fourth block column is set as an invalid block. The invalidation basic matrix after setting the invalid block In the invalidation base matrix BG′, the element -1 represents an all-zero matrix.

[0069] The check matrix H represented by the invalidated basic matrix BG′ is as follows: Figure 5 See Figure 5 , the matrix corresponding to the element -1 in the invalidated basic matrix BG′ in the check matrix H is an all-zero matrix The matrix in the check matrix H corresponding to the element 0 in the invalidated basic matrix BG′ is the unit matrix The matrix in the check matrix H corresponding to the element 1 in the invalidated basic matrix BG′ is the cyclic shift matrix The matrix in the check matrix H corresponding to element 2 in the invalidated basic matrix BG′ is the cyclic shift matrix

[0070] In another example, the PEG algorithm is used to Figure 4 After selecting valid blocks for each block column of the base matrix shown in the figure and setting the blocks that are not selected as valid blocks as invalid blocks, we can obtain Figure 6 The invalidation basic matrix BG′ is shown. Figure 4 and Figure 6As shown, the basic matrix BG and the invalidated basic matrix BG′ have the same number of rows and columns, each element in the invalidated basic matrix BG′ represents a 128×128 unit matrix, a cyclic shift matrix or an all-zero matrix, the element 0 in the invalidated basic matrix BG′ represents a 128×128 unit matrix, the element X (X is greater than or equal to 0 and less than 128) in the invalidated basic matrix BG′ represents a 128×128 cyclic shift matrix obtained by cyclically shifting the 128×128 unit matrix by X positions, and the element -1 in the invalidated basic matrix BG′ represents a 128×128 all-zero matrix.

[0071] See also Figure 4 and Figure 6 , the 3rd, 5th, 6th and 8th blocks in the 1st column of the basic matrix BG are selected as valid blocks, the 1st, 2nd, 7th and 9th blocks in the 2nd column of the basic matrix BG are selected as valid blocks, the 3rd, 5th, 7th and 9th blocks in the 3rd column of the basic matrix BG are selected as valid blocks, the 2nd, 4th, 6th and 7th blocks in the 4th column of the basic matrix BG are selected as valid blocks, the 3rd, 5th, 6th and 8th blocks in the 5th column of the basic matrix BG are selected as valid blocks, and the The 3rd, 5th, 7th and 10th blocks in the 6th column of the matrix BG are selected as valid blocks, the 1st, 5th, 6th and 8th blocks in the 7th column of the basic matrix BG are selected as valid blocks, the 5th, 7th, 8th and 9th blocks in the 8th column of the basic matrix BG are selected as valid blocks, the 3rd, 5th, 8th and 10th blocks in the 9th column of the basic matrix BG are selected as valid blocks, the 1st, 3rd, 4th and 8th blocks in the 10th column of the basic matrix BG are selected as valid blocks, and the basic matrix The 1st, 2nd, 5th and 9th blocks in the 11th column of the basic matrix BG are selected as valid blocks, the 2nd, 3rd, 4th and 5th blocks in the 12th column of the basic matrix BG are selected as valid blocks, the 1st, 2nd, 6th and 8th blocks in the 13th column of the basic matrix BG are selected as valid blocks, the 2nd, 3rd, 7th and 8th blocks in the 14th column of the basic matrix BG are selected as valid blocks, the 2nd, 4th, 5th and 8th blocks in the 15th column of the basic matrix BG are selected as valid blocks, and the 2nd, 4th, 5th and 8th blocks in the 15th column of the basic matrix BG are selected as valid blocks. The 1st, 2nd, 3rd and 8th blocks in the 16th column of the matrix BG are selected as valid blocks, the 2nd, 4th, 7th and 9th blocks in the 17th column of the basic matrix BG are selected as valid blocks, the 4th, 6th, 7th and 9th blocks in the 18th column of the basic matrix BG are selected as valid blocks, the 5th, 6th, 8th and 10th blocks in the 19th column of the basic matrix BG are selected as valid blocks, and the 2nd, 4th, 6th and 7th blocks in the 20th column of the basic matrix BG are selected as valid blocks.

[0072] In an embodiment of the present application, the difference in the offsets of adjacent blocks in the same row in the base matrix is ​​equal, and after selecting valid blocks from each column of the base matrix by the progressive edge growth algorithm, the blocks other than the valid blocks in the base matrix are set as invalid blocks, and a check matrix for checking low-density parity check codes is obtained. Since the difference in the offsets of blocks in the same row in the base matrix is ​​equal, when the check matrix generated by the base matrix based on the specific structure checks the LDPC code, when the adjacent columns in the check matrix are switched for processing, the number of shifts of each row remains unchanged, which can simplify the hardware structure for decoding the LDPC code based on the check matrix and reduce the overhead of hardware shifting during the decoding of the LDPC code.

[0073] In a possible implementation, when selecting valid blocks from a base matrix using the PEG algorithm, valid check nodes can be determined from multiple nodes based on the girth, approximate cycle extrinsic message degree (ACE), external message degree (EMD), cycle number, and row degree corresponding to the check nodes, and then blocks in the base matrix that have the same number of rows and the same number of block columns as the valid check nodes are determined as valid blocks.

[0074] The ring length is used to indicate the number of edges included in the ring, and the edges are used to connect variable nodes and check nodes.

[0075] ACE is used to approximately evaluate the proportion of information in the message received by a variable node from the check node during iterative decoding that is not contained in any loop (especially short loops). ACE attempts to quantify how much of the message is "new" information during the propagation of the message in the graph, rather than repeated information circulating in the loop.

[0076] EMD is an indicator to measure the quality of information carried by a message when it is transmitted between nodes within the decoder during iterative decoding of LDPC codes. EMD is defined as the ratio of the amount of "new" information of a message to the amount of original information after multiple iterations during iterative decoding. The "new" information here refers to the information obtained through the interaction between the check nodes and the variable nodes during the decoding process.

[0077] The number of rings refers to the number of rings that can be formed based on a check node if the check node is selected as a valid check node. When a check node is selected as a valid check node, at least one ring can be formed based on the check node.

[0078] The row weight is used to indicate the number of selected valid blocks in the corresponding row in the basis matrix.

[0079] When selecting valid blocks based on the PEG algorithm, the PEG algorithm will construct a ring including variable nodes and check nodes. The variable nodes correspond to the block columns of the base matrix, and the check nodes correspond to the blocks in the base matrix. In most cases, when different check nodes are selected as valid check nodes, at least part of the ring length, ACE, EMD, number of rings and row weight of the formed ring will change. Therefore, based on the ring length, ACE, EMD, number of rings and row weight of the ring formed when the check node is selected as the valid check node, a valid check node can be selected from the check nodes corresponding to each block column in the base matrix, and then the block corresponding to the valid check node in the block column in the base matrix is ​​determined as a valid block.

[0080] In an embodiment of the present application, due to the specific structure of the base matrix, a more sophisticated strategy is required to select valid blocks from the base matrix to ensure the accuracy of the constructed check matrix in checking the LDPC code. A valid block is selected from each column of the base matrix based on the ring length, ACE, EMD, number of rings and row weight corresponding to the check node, and then a check matrix is ​​constructed based on the selected valid blocks. While ensuring that the constructed check matrix can reduce the hardware shift overhead, the accuracy of the LDPC code check by the check matrix can also be guaranteed.

[0081] In one possible implementation, when selecting valid check nodes from check nodes based on ring length, ACE, EMD, number of rings and row weight through the PEG algorithm, the priorities of ring length, ACE, EMD, number of rings and row weight are from high to low, and then the valid check nodes are screened based on ring length, ACE, EMD, number of rings and row weight in order from high to low priority.

[0082] Figure 7 FIG. 1 is a flow chart of a method for selecting an effective check node according to an embodiment of the present application. Figure 7 As shown, the effective check node selection method includes the following steps:

[0083] Step 701: Perform breadth-first expansion with the variable node corresponding to the i-th block column in the base matrix as the root node.

[0084] i is a positive integer less than or equal to the number of columns of the block in the base matrix. For example, if the base matrix includes 10 rows × 20 block columns, then i is an integer in the interval [1,20]. The valid check nodes are determined starting from the first block column of the base matrix. After the valid check nodes corresponding to the first block column are determined, the valid check nodes corresponding to the second block column are determined, and so on, until the valid check nodes corresponding to the 20th block column are determined. It should be noted that the i-th block column refers to the i-th column of the base matrix when the block is the element, see Figure 3 , the basis matrix H base It includes 3 block columns, and each block column includes 3 blocks.

[0085] Each block column of the basis matrix corresponds to a variable node, and different block columns correspond to different variable nodes.

[0086] It should be noted that the method for determining the valid check nodes corresponding to each block column in the base matrix is ​​the same, and this embodiment is described by taking determining the valid check nodes corresponding to the i-th block column as an example.

[0087] Step 702: Determine a first check node from among a plurality of check nodes that correspond to the i-th block column and can be selected as valid check nodes based on the ring length and the score value determined by the ACE.

[0088] Each block in the base matrix corresponds to a check node, and different blocks correspond to different check nodes. When determining the valid check node corresponding to the i-th block column in the base matrix, the valid check node is selected from the check nodes corresponding to the block in the i-th block column in the base matrix. The check nodes that are not selected as valid check nodes can be selected as valid check nodes. In one example, see Figure 4 , each block column of the base matrix includes 10 blocks. After the check node corresponding to the block located in the 1st block column and the 1st block row in the base matrix is ​​determined as a valid check node, when the valid check node corresponding to the 1st block column is determined again, the check node is selected from the check nodes corresponding to the remaining 9 blocks in the 1st block column.

[0089] It should be noted that, for the sake of convenience of description, the check nodes described later in the embodiments of the present application, unless otherwise stated, all refer to the check nodes corresponding to the i-th block column and can be selected as valid check nodes. The valid check nodes described later in the embodiments of the present application, unless otherwise stated, all refer to the valid check nodes corresponding to the i-th block column.

[0090] For each verifiable node, the ring length and ACE of the ring formed when the check node is used as a valid check node can be determined, and then a valid check node can be selected from multiple check nodes according to the ring length and ACE corresponding to each check node. When each check node is used as a valid check node, the check node can form at least one ring with the variable node, and each ring has a corresponding ring length and ACE, so each check node corresponds to at least one ring length and at least one ACE.

[0091] In one example, the score value based on the ring length and ACE can be equal to the sum of the opposite number of the ring length and ACE. After determining the ring length and ACE corresponding to the check node, the score value of the ring can be calculated based on the ring length and ACE corresponding to the same ring. After calculating the score value of the ring formed based on each check node, the check node corresponding to the ring with the smallest score value is determined as the first check node. By calculating the first score value based on the ring length and ACE, there is no need to screen the check nodes based on the ring length and ACE respectively, which can improve the construction efficiency of the check matrix.

[0092] In another example, the score value includes a first score value and a second score value, the first score value is the ring length, and the second score value is ACE. When determining the first check node according to the score value, first select the check node with the largest first score value from multiple check nodes, and if the number of check nodes with the largest first score value is 1, then the check node with the largest first score value is determined as the first check node. If the number of check nodes with the largest first score value is greater than 1, then the check node with the smallest second score value among the multiple check nodes with the largest first score value is determined as the first check node.

[0093] Step 703 , determine whether the number of the first check nodes is equal to 1, if yes, execute step 704 , otherwise execute step 705 .

[0094] After the first check node is determined, it is determined whether the number of the first check node is equal to 1. If the number of the first check node is equal to 1, the first check node can be determined as a valid check node, and step 704 is performed accordingly. If the number of the first check node is greater than 1, a step of screening valid check nodes from the first check node is required, and step 705 is performed accordingly.

[0095] Step 704 : Determine the first check node as a valid check node corresponding to the i-th block column, and execute step 719 .

[0096] Step 705: Determine the EMD of the ring formed by each first check node and the variable node corresponding to the i-th block column.

[0097] If there are multiple first check nodes, the EMD of the ring formed by each first check node and the variable node corresponding to the i-th block column is determined respectively.

[0098] Each first check node may form at least one ring with the variable node corresponding to the i-th block column, and each formed ring has a corresponding EMD, so the EMD of each ring formed based on each first check node may be determined.

[0099] Step 706: According to the EMD corresponding to the first check node, determine a second check node corresponding to the minimum EMD from the plurality of first check nodes.

[0100] Each first check node corresponds to a plurality of EMDs, a minimum EMD is determined from the EMDs corresponding to the first check nodes, and the first check node corresponding to the minimum EMD among the first check nodes is determined as the second check node.

[0101] In one example, the number of first check nodes is 3, first check node 1 corresponds to EMD1, EMD2 and EMD3, first check node 2 corresponds to EMD1, EMD4 and EMD5, and first check node 3 corresponds to EMD2 and EMD4. If EMD1 is the smallest among EMD1, EMD2, EMD3, EMD4 and EMD5, first check node 1 is determined as the second check node. If EMD2 is the smallest among EMD1, EMD2, EMD3, EMD4 and EMD5, first check node 1 and first check node 3 are both determined as second check nodes.

[0102] Step 707 , determine whether the number of the second check nodes is equal to 1, if yes, execute step 708 , otherwise execute step 709 .

[0103] After determining the second check node, it is determined whether the number of the second check nodes is equal to 1. If the number of the second check nodes is equal to 1, the second check node can be determined as a valid check node, and step 708 is performed accordingly. If the number of the second check nodes is greater than 1, it is necessary to further screen the valid check nodes from the second check nodes, and step 709 is performed accordingly.

[0104] In the embodiment of the present application, since ACE is an approximation of EMD, obtaining EMD requires inversely checking the formed ring, and ACE can be determined in the process of forming the ring, so the time consumption of obtaining EMD is greater than ACE. Therefore, when the number of first check nodes corresponding to the same ring length and ACE is multiple, the second check node is selected from the first check node based on EMD. While ensuring the accuracy of the formed check matrix in checking the LDPC code, the efficiency of the check matrix construction can be guaranteed.

[0105] Step 708 : Determine the second check node as a valid check node corresponding to the i-th block column, and execute step 718 .

[0106] Step 709: Determine the number of rings formed by each second check node and the variable nodes corresponding to the i-th block column.

[0107] Each second check node can form at least one ring with the variable node corresponding to the i-th block column. The PEG algorithm can be used to determine how many rings each second check node can form with the variable node corresponding to the i-th block column, that is, the number of rings formed by the second check node and the variable node corresponding to the i-th block column.

[0108] Step 710: Determine a third check node corresponding to the minimum number of rings from the plurality of second check nodes.

[0109] Each second check node corresponds to a ring quantity, that is, the number of rings that the second check node can form with the variable nodes corresponding to the i-th block column, and the second check node corresponding to the minimum number of rings among the second check nodes is determined as the third check node.

[0110] Step 711: determine whether the number of the third check node is equal to 1, if yes, execute step 712, otherwise execute step 713.

[0111] After the third check node is determined, it is determined whether the number of the third check node is equal to 1. If the number of the third check node is equal to 1, the third check node can be determined as a valid check node, and step 712 is performed accordingly. If the number of the third check node is greater than 1, it is necessary to further screen valid check nodes from the third check nodes, and step 713 is performed accordingly.

[0112] Step 712 : Determine the third check node as a valid check node corresponding to the i-th block column, and execute step 718 .

[0113] Step 713: Determine the row weight of the block row corresponding to the third check node in the base matrix.

[0114] The check node corresponds to a block in the base matrix. The block row corresponding to the check node is the block row where the block corresponding to the check node is located in the base matrix. The block column corresponding to the check node is the block column where the block corresponding to the check node is located in the base matrix.

[0115] When there are multiple third check nodes, the row weight of the block row corresponding to each third check node in the base matrix can be determined respectively, and the row weight is used to indicate the number of blocks determined as valid blocks in the corresponding block row in the base matrix.

[0116] Step 714: Determine a fourth check node corresponding to the minimum row weight from the plurality of third check nodes.

[0117] Each third check node has a corresponding row weight, that is, the number of blocks in the block row corresponding to the third check node in the base matrix that are determined to be valid blocks, and the third check node with the minimum row weight among the third check nodes is determined as the fourth check node.

[0118] Step 715 , determine whether the number of the fourth check node is equal to 1, if so, execute step 716 , otherwise execute step 718 .

[0119] After the fourth check node is determined, it is determined whether the number of the fourth check node is equal to 1. If the number of the fourth check node is equal to 1, the fourth check node can be determined as a valid check node, and step 716 is performed accordingly. If the number of the fourth check node is greater than 1, it is necessary to further screen valid check nodes from the fourth check node, and step 717 is performed accordingly.

[0120] Step 716 : Determine the fourth check node as a valid check node corresponding to the i-th block column, and execute step 718 .

[0121] Step 717 : randomly select a fourth check node from the plurality of fourth check nodes as a valid check node corresponding to the i-th block column, and execute step 718 .

[0122] Step 718, determine whether the number of valid check nodes corresponding to the i-th block column is equal to the number of valid blocks required by the i-th block column of the base matrix, if so, end the current process, otherwise execute step 701.

[0123] The valid blocks required for each block column of the base matrix are the column weight target values ​​in the aforementioned embodiments. For example, the number of valid blocks required for the i-th block column of the base matrix is ​​N, and the column weight target value of the i-th block column of the base matrix is ​​N. The valid check nodes corresponding to the i-th block column are determined one by one. When the number of valid check nodes corresponding to the i-th block column is less than the column weight target value, a valid check node corresponding to the i-th block column can be determined each time steps 701 to 718 are performed until the number of valid check nodes corresponding to the i-th block column is equal to the column weight target value.

[0124] After determining that the number of valid check nodes corresponding to the i-th block column is equal to the column weight target value of the i-th block column, start determining the valid check nodes corresponding to the i+1-th block column until the number of valid check nodes corresponding to the last block column in the base matrix is ​​equal to the column weight target value of the last block column in the base matrix.

[0125] In an embodiment of the present application, in the process of determining the effective check node by the PEG algorithm, the effective check node is screened from the check node based on the ring length, ACE, EMD, the number of rings and the row weight. By determining the effective check node by multiple indicators such as the ring length, ACE, EMD, the number of rings and the row weight, the constructed check matrix can be made more refined, while reducing the hardware shift overhead, the accuracy of the LDPC code verification by the check matrix is ​​guaranteed. Since it takes longer to obtain EMD than to obtain ACE, after the effective check node cannot be determined based on ACE, the effective check node is determined by EMD. If the effective check node can be determined based on ACE, there is no need to obtain EMD, thereby reducing the number of times the EMD is obtained and ensuring the efficiency of the check matrix construction.

[0126] In a possible implementation manner, after obtaining the check matrix, at least one type of elementary trapping set (ETS) of the check matrix may be determined.

[0127] ETS is a key structure that causes the error floor phenomenon in low LDPC codes. ETS usually refers to a subgraph consisting of variable nodes and check nodes in the Tanner graph of LDPC codes, where the degree of the check nodes in these subgraphs is only 1 or 2. During iterative decoding, if the check nodes in ETS are not satisfied (i.e., the degree is an odd number), the decoder may fall into an erroneous stable state, resulting in incorrect decoding.

[0128] ETS includes many types, such as (8,6)ETS, (10,7)ETS, (11,8)ETS, etc. (a,b)ETS means that in the subgraph formed by a variable nodes, the degree of all check nodes does not exceed 2, and the degree of b check nodes is 1, and a and b are both positive integers. The number of ETS in the check matrix is ​​negatively correlated with the decoding performance of the check matrix. Corresponding quantity thresholds are set for different types of ETS, and the quantity thresholds corresponding to different types of ETS can be different.

[0129] After determining the ETS of the check matrix, it can be determined whether the number of each type of ETS is greater than the corresponding number threshold. If the number of at least one type of ETS is greater than the corresponding number threshold, the check matrix can be reconstructed according to the base matrix.

[0130] In one example, (8,6)ETS, (10,7)ETS and (11,8)ETS of the check matrix are determined, the number threshold corresponding to (8,6)ETS is number threshold 1, the number threshold corresponding to (10,7)ETS is number threshold 2, and the number threshold corresponding to (11,8)ETS is number threshold 3. When at least one of the following three conditions is detected, the check matrix is ​​reconstructed according to the base matrix:

[0131] (1)(8,6)The number of ETS is greater than the number threshold 1;

[0132] (2) (10,7) The number of ETS is greater than the number threshold 2;

[0133] (3)(11,8)The number of ETS is greater than the number threshold 3.

[0134] It should be noted that the basic trapping set of the check matrix can be obtained in various suitable ways, and the embodiment of the present application does not limit the way to obtain the basic trapping set.

[0135] In an embodiment of the present application, after constructing a check matrix, a basic trap set of at least one type of the check matrix is ​​obtained. If the number of basic trap sets of a certain type is greater than the corresponding number threshold, the check matrix is ​​reconstructed based on the base matrix to ensure the error correction capability of the constructed check matrix.

[0136] Device for constructing a check matrix

[0137] Figure 8 FIG. 8 is a schematic diagram of a device 800 for constructing a check matrix according to an embodiment of the present application. Figure 8 As shown, the construction device 800 of the check matrix includes:

[0138] A generating unit 801 is used to generate a base matrix, in which the differences in offsets of adjacent blocks in the same row are equal;

[0139] A selection unit 802, configured to select a plurality of valid blocks from each column of the base matrix by a progressive edge growth algorithm;

[0140] The invalidation unit 803 is used to set the blocks other than the valid blocks in the base matrix as invalid blocks, so as to obtain a check matrix for checking the low-density parity-check code.

[0141] In the embodiment of the present application, the difference in the offsets of adjacent blocks in the same row in the base matrix generated by the generating unit 801 is equal, and after the selecting unit 802 selects valid blocks from each column of the base matrix by the progressive edge growth algorithm, the invalid unit 803 sets the blocks other than the valid blocks in the base matrix as invalid blocks, and obtains a check matrix for checking the low-density parity check code. Since the difference in the offsets of blocks in the same row in the base matrix is ​​equal, when the check matrix generated by the base matrix based on the specific structure checks the LDPC code, when the adjacent columns in the check matrix are switched for processing, the number of shifts of each row remains unchanged, which can simplify the hardware structure for decoding the LDPC code based on the check matrix and reduce the overhead of hardware shifting in the decoding process of the LDPC code.

[0142] It should be noted that the apparatus for constructing a check matrix in this embodiment is used to implement the method for constructing a check matrix in the aforementioned method embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail herein.

[0143] Electronic devices

[0144] Fig. 9 This is a schematic block diagram of an electronic device provided in an embodiment of the present application. The specific embodiment of the present application does not limit the specific implementation of the electronic device. Fig. 9 As shown, the electronic device may include: a processor (processor) 902, a communication interface (Communications Interface) 904, a memory (memory) 906, and a communication bus 908. Among them:

[0145] The processor 902 , the communication interface 904 , and the memory 906 communicate with each other via a communication bus 908 .

[0146] The communication interface 904 is used to communicate with other electronic devices or servers.

[0147] The processor 902 is used to execute the program 910, and specifically can execute the relevant steps in any of the aforementioned embodiments of the method for constructing a check matrix.

[0148] Specifically, the program 910 may include program codes, which include computer operation instructions.

[0149] The processor 902 may be a CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present application. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0150] RISC-V is an open source instruction set architecture based on the Reduced Instruction Set (RISC) principle. It can be applied to various aspects such as single-chip microcomputers and FPGA chips. Specifically, it can be applied to the fields of IoT security, industrial control, mobile phones, personal computers, etc., and because it is designed with small, fast, and low-power realities in mind, it is particularly suitable for modern computing devices such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems. With the rise of artificial intelligence Internet of Things (AIoT), the RISC-V instruction set architecture has also received more and more attention and support, and is expected to become the next generation of widely used CPU architecture.

[0151] The computer operation instructions in the embodiment of the present application may be computer operation instructions based on the RISC-V instruction set architecture, and correspondingly, the processor 902 may be designed based on the RISC-V instruction set. Specifically, the chip of the processor in the electronic device provided in the embodiment of the present application may be a chip designed with the RISC-V instruction set, and the chip may execute executable code based on the configured instructions, thereby realizing the construction method of the check matrix in the above embodiment.

[0152] The memory 906 is used to store the program 910. The memory 906 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0153] The program 910 may be specifically used to enable the processor 902 to execute the method for constructing a check matrix in any of the aforementioned embodiments.

[0154] The specific implementation of each step in program 910 can refer to the corresponding description of the corresponding steps and units in any of the aforementioned embodiments of the method for constructing a check matrix, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described devices and modules can refer to the corresponding process description in the aforementioned method embodiment, which will not be repeated here.

[0155] Through the electronic device of the embodiment of the present application, the difference of the offsets of adjacent blocks in the same row in the generated base matrix is ​​equal, and after selecting valid blocks from each column of the base matrix through the progressive edge growth algorithm, the blocks other than the valid blocks in the base matrix are set as invalid blocks, and then a check matrix for checking low-density parity check codes is obtained. Since the difference of the offsets of blocks in the same row in the base matrix is ​​equal, when the check matrix generated by the base matrix based on the specific structure checks the LDPC code, when the adjacent columns in the check matrix are switched for processing, the number of shifts of each row remains unchanged, which can simplify the hardware structure for decoding the LDPC code based on the check matrix and reduce the overhead of hardware shifting during the decoding of the LDPC code.

[0156] Computer storage media

[0157] The present application also provides a computer-readable storage medium storing instructions for causing a machine to execute the method for constructing a check matrix as described herein. Specifically, a system or device equipped with a storage medium can be provided, on which a software program code for implementing the functions of any of the above embodiments is stored, and a computer (or CPU or MPU) of the system or device reads and executes the program code stored in the storage medium.

[0158] In this case, the program code read from the storage medium itself can implement the function of any one of the above embodiments, so the program code and the storage medium storing the program code constitute part of the present application.

[0159] The storage medium embodiments for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer by a communication network.

[0160] Computer program product

[0161] An embodiment of the present application also provides a computer program product, including computer instructions, which instruct a computing device to perform any corresponding operation in the above-mentioned multiple method embodiments.

[0162] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used to train the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0163] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present application.

[0164] The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as a computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded through a network and to be stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a special-purpose processor or programmable or special-purpose hardware (such as an ASIC or FPGA). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by a computer, a processor or hardware, the method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the method shown here, the execution of the code converts the general-purpose computer into a special-purpose computer for executing the method shown here.

[0165] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used to train the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0166] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for specific applications, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.

[0167] The above implementation methods are only used to illustrate the embodiments of the present application, and are not limitations on the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present application. The scope of patent protection of the embodiments of the present application should be limited by the claims.

Claims

1. A method for constructing a check matrix, include: Generate a base matrix, in which the differences in offsets of adjacent blocks in the same row are equal; Selecting a plurality of valid blocks from each column of the base matrix by a progressive edge growth algorithm; The blocks in the base matrix except the valid blocks are set as invalid blocks to obtain a check matrix for checking a low-density parity-check code.

2. The method according to claim 1, in, The step of selecting a plurality of valid blocks from each column of the base matrix by a progressive edge growth algorithm comprises: Determine a valid check node from multiple check nodes by using the progressive edge growth algorithm according to the ring length, approximate outer ring information degree, external information degree, number of rings and row weight corresponding to the check node; The blocks in the base matrix that have the same number of rows and the same number of columns as the valid check nodes are determined as the valid blocks.

3. The method according to claim 2, in, The method of determining a valid check node from a plurality of check nodes by the progressive edge growth algorithm according to the ring length, approximate outer ring information degree, external information degree, number of rings and row weight corresponding to the check node comprises: Perform breadth-first expansion with the variable node corresponding to the i-th block column in the base matrix as the root node, where i is a positive integer less than or equal to the number of columns of the block in the base matrix; Based on the score value determined according to the ring length and the approximate out-of-ring information degree, determining a first check node among a plurality of check nodes corresponding to the i-th block column and selectable as valid check nodes; If the number of the first check node is 1, the first check node is determined as a valid check node corresponding to the i-th block column.

4. The method according to claim 3, in, The score value is equal to the sum of the inverse of the ring length and the approximate outer-ring information degree.

5. The method according to claim 3, further comprising: include: If the number of the first check nodes is greater than 1, determining the external information degree of each ring formed by each of the first check nodes and the variable nodes corresponding to the i-th block column; According to the external information degree corresponding to the first check node, determining a second check node corresponding to the minimum external information degree from the plurality of first check nodes; If the number of the second check nodes is 1, the second check node is determined as a valid check node corresponding to the i-th block column.

6. The method according to claim 5, further comprising: include: If the number of the second check nodes is greater than 1, determining the number of rings formed by each of the second check nodes and the variable nodes corresponding to the i-th block column; Determine a third check node corresponding to the minimum number of rings from the plurality of second check nodes; If the number of the third check node is 1, the third check node is determined as a valid check node corresponding to the i-th block column.

7. The method according to claim 6, further comprising: include: If the number of the third check nodes is greater than 1, determining a row weight of a block row corresponding to the third check node in the base matrix, wherein the row weight is used to indicate the number of blocks determined to be valid blocks in the corresponding block row in the base matrix; Determining a fourth check node corresponding to the smallest row weight from the plurality of third check nodes; If the number of the fourth check node is 1, determining the fourth check node as a valid check node corresponding to the i-th block column; If the number of the fourth check nodes is greater than 1, one of the fourth check nodes is randomly selected from the plurality of the fourth check nodes as a valid check node corresponding to the i-th block column.

8. The method according to any one of claims 3 to 7, further comprising: include: After N valid check nodes corresponding to the i-th block column are determined, start determining the valid check nodes corresponding to the i+1-th block column of the base matrix, where N is the number of valid blocks required for the i-th block column of the base matrix, and i+1 is less than or equal to the number of block columns of the base matrix.

9. The method according to any one of claims 1 to 7, further comprising: include: After obtaining the check matrix, determining at least one type of basic trapping set of the check matrix; If the number of any of the basic trapping sets is greater than the corresponding number threshold, the check matrix is ​​reconstructed based on the base matrix.

10. A device for constructing a check matrix, include: A generating unit, used for generating a base matrix, wherein the differences of the offsets of adjacent blocks in the same row of the base matrix are equal; A selection unit, configured to select a plurality of valid blocks from each column of the base matrix by a progressive edge growth algorithm; The invalidation unit is used to set the blocks in the base matrix except the valid blocks as invalid blocks to obtain a check matrix for checking the low-density parity-check code.

11. A solid state hard disk, include: Storage control chips and solid-state electronic storage chips; The storage control chip is used to read data from the solid-state electronic storage chip and perform error checking and correction on the read data based on the check matrix constructed by any one of the methods described in claims 1-9.

12. An electronic device, include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute an operation corresponding to any one of the methods in claims 1-9.

13. A computer storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 9.

14. A computer program product comprising computer instructions, the computer instructions instructing a computing device to execute the method according to any one of claims 1 to 9.

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